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Digitall Electron
nics

Syynchron
nous Co
ounterss
In a syncchronous counnter, also kn
nown as a parallel
p
counnter, all the flip-

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flops in
n the couunter chan
nge state at the same
s
timee in
synchro
onism with the input clock
c
signaal. The clocck signal in this

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case is simultaneou
s
usly appliedd to the clo
ock inputs of all the flip-

flops. The delay in

nvolved in this
t case is equal to th
he propagattion delay of
o one flip--flop
only, irrrespective of
o the num
mber of flip
p-flops usedd to constrruct the co
ounter. In other
o
words, the
t delay is
i independdent of thee size of th
he counterr. Since thee different flipflops in
n a synchro
onous couunter are clocked
c
at the same time, therre needs to
o be
addition
nal logic cirrcuitry to ensure
e
that the variouus flip-flops toggle at the right time.
t

.s
a

MOD 8 Counter:

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the desiggn proceduure.

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sequences can be obtained by using

Using parallel
p
coun
nters, any binary
b
or non-binary
n
u

To obttain MOD 8 parallel counter, 3 flip-flopss are requiired. Clockk input willl be

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common
n for all flip-flops
f
a hence the flip-flo
and
ops shouldd not be in
n toggle mode
m
always and
a additio
onal hardwaare is requiired to obttain the seqquence. The state diaggram
and tablle for the reequired couunter is as shown
s
belo
ow.

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In the given count sequence, we find that flip-flop FF0 toggles with every clock pulse,
flip-flop FF1 toggles only when the output of FF0,

is in the 1 state, flip-flop FF2

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toggles only with those clock pulses when the outputs of FF0 and FF1 are both in the

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a

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logic 1 state. Such logic can be easily implemented with AND gates.

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MOD 8 DOWN Counter:

are

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The circuit diagram for DOWN counter is as shown below where

given to the inputs of flip-flop directly (or using AND gate).

Examples:

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1. Design a BCD counter using JK flip-flops.

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Sol:

.s
a

To design a BCD counter or decade counter or MOD 10 counter, 4 flip-flops are

required.

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State diagram:

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State table:
Present State (PS)

Next State (NS)

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0
1

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Circuit excitation and output table:

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0

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Flip-flop Input functions

.s
a

Next State (NS)

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Present State (PS)

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1
1
1
1
1
1
1
1
1
1

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By using K-maps, we get expressions for the flip-flop input functions.

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1;

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2. Design a counter using JK flip-flops for the following binary sequence: 0, 4, 2,

1, 6 and repeat.

Present State
(PS)

Next State
(NS)

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.s
a

Sol:

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Circuit Excitation and output table:
Next State
(NS)

1;

1
1

1;

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w

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a

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By using K-maps, we get.

Flip-flop Input functions

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Present State
(PS)

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1;

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Lockout:
The counter just discussed utilizes only five out the total number of eight states
available in a counter having three flip-flops. The counter may enter one of the
unused states and may keep moving between the unused states and not come out of

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this situation. This condition may develop because of external noise, which may affect
states of the flip-flops. If a counter has unused states with this characteristic, it is said
to suffer from lockout. The lockout situation can be avoided by so arranging the

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circuit that whenever the counter happens to be in an unused state, it reverts to one of
the used states. The above circuit can be designed to avoid lock out by making the
next states of unused states (3, 5, 7) to any valid state. Hence to avoid lockout or to
make the counter self-starting, the next state of any invalid state must be a valid initial
state.

The advantages of parallel counter are its speed of operation and any type of sequence
can be obtained. The drawback is its hardware part where we require additional gates

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.s
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ks

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along with required number of flip-flops.

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