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As you can see, the 4-bit entered was (0101) , the reset was 0, thus the system did not
reset. This made the output the same value ( 0101) and thus led to the system storing the
value. This shows evidence that the system functions properly.
A bus is a network topology or circuit arrangement in which all devices are attached to a
line directly and all signals pass through each of the devices. Each device has a unique
identity and can recognize those signals intended for it. This reduces the number of single
inputs for a system, thus making it one input signal and using a bus to identify the signal.
By observation one can see an 8-bit at the input. Since the reset is low, the system stores
the 8-bit thus the output displays the 8-bit in its memory, which concludes that the system
is functioning properly.
First we must know how the integrating circuit works inside the multiplexer so that we
use the correct selects (S0 , S1 ) to output our desired signal. Looking at the timing
behavioral we chose our selects as (S0 = 0 , S1 = 0). Since we know that this select
configuration outputs Ax, we can clearly see from above that it outputs the signal of Ax,
thus it functions properly.
Problems faced:
1) System did not run. (Schematics)
2) Modelsim did not run. (Libraries crashed)
3) Built my project on many computers since the timing behavioral only works in the
electronics lab.
Corrective measures taken:
1)
2)
3)
4)
POST LAB:
Design:
The way this was built is that we use two 4-bit hold register ( the schematic for the 4-bit
hold register is shown in Figure 1) with bus taps to acquire an 8-bit hold register. Then
two 8-bit hold register with bus tap was used to produce a 16-bit hold register as seen
above.
Verification:
From the functional behavior figure, a 16-bit was fed into the input and since the reset is
low that means the output should be the same as the input.
Question 2
Design:
4 macros of the 1-bit 4 to 1 line multiplexer were used with the addition of busses to
create the 4-bit 4 to 1 line multiplexer as shown above.
Verification:
As you can see from the functional diagram above, the selects S0 = 1 , S1 = 0 gives the
input of gate C, hence the output X should be the same input signal as C.
Question 3
( I built over the project as a different name because the current computer had the same
name files stored)
Design:
First a 1 bit 3 to 1 mux was built, then a macro was obtained.( There is an internal Vcc to
compensate for the select configuration of S0 = 1 , S1 = 1, this simply implies that for that
particular select of S0 = 1 , S1 = 1 ,I will obtain my Vcc signal. Now this macro was bus
tap with another macro just like it to create a 2-bit 3 to 1 mux. A macro was created and
then 2 of these macros was used to make a 4-bit 3 to 1 mux. A 4-bit 3 to 1 mux macro
was created and two of these were bus tap to make an 8-bit 3 to 1 mux. This macro was
created and two of these were bus tap to make a 16-bit 3 to 1 mux.
Verification:
As you can see from the functional diagram above, the selects S0 = 1 , S1 = 0 gives the
input of gate C, hence the output X should be the same input signal as C.