Writing VHDL Test Benches For System Verification

THE UNIVERSITY OF THE WEST INDIES
ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering
Writing VHDL Test Benches for Digital System Verification

Author: Marcus L George
Last Review: Thursday 15th October 2009
Introduction
Verification of the functionality of implemented digital circuits is crucial in order to determine
if the system is functioning according to required specifications. This manual demonstrates to the
user how to write VHDL test benches for digital system verification using Xilinx ISE. It is assumed
that the reader is proficient in the implementation of digital circuits using Xilinx Schematic Editor.
The reader is urged to treat this publication as a mini-laboratory exercise for maximum
understanding of the material. After performing this mini-exercise in the laboratory, the reader is
expected to:
1. Understand how to write VHDL test benches for the verification of an implemented digital
circuit
2. Use Modelsim 6.0SE/SE or any other version to simulate the behaviour of an implemented
digital circuit
3. Restart simulation waveforms using specific icons in the Modelsim environment
4. Run at once, simulation parameters pre-set in the VHDL test bench using specific icons in the
Modelsim environment
Required Equipment
1. 1 Computer
2. 1 copy of this manual

In-Lab Exercise
1. Open the Xilinx ISE environment and create a new project as shown in the diagram below.
2. Give the project a name, prefereably VHDL_Testbenches. Be sure to select the TopLevel Module Type as Schematic.
3. Click Next!

4. Select the device and design flow as shown I the diagram below. It is assumed that this is not
the first time that the reader has created a project in the Xilinx ISE environment.
5. Click Next for the next three dialog boxes!

6. Click Finish!

7. Add a new source to the project as shown in the diagram below.

8. Select a Schematic source and give it the name and_gate_2input
9. Click Next!
10. Click Finish!

11. In the schematic editor window select an and2 gate from the category Logic and place it in
the schematic window.

12. Inset I/O Markets at the ports of the and2 gate. Rename the I/O markers as shown in the
diagram below.

13. Synthesize the schematic module by double clicking the Synthesize tab in the Process
Window as shown in the diagram below.

14. Once the schematic successfully synthesizes, add a new VHDL Test Bench source as shown
in diagram below. Name this VHDL test bench source and_gate_2input_tb.
15. Click Next!
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16. In the new window, highlight the module in which we wish to attach this VHDL test bench
to. In this case we attach this VHDL test bench to the module and_gate_2input.
17. Click Next!

18. Click Finish!
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19. A new file should appear, similar to that shown in the diagram below. This is the VHDL Test
Bench source. You will realise that some VHDL code has already been generated. All you
need to do now is insert your simulation test cases.
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20. We must now insert our test cases in the space in the VHDL Test Bench file where the
following lines of comments are shown:
------------------------------------------------We write Test Bench Code Here-------------------------------------------------It is to be noted that comments are inserted by placing two dashes --.
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21. The following table gives the test cases to be considered in the writing of the VHDL Test
Bench. All we need to do now is represent these test cases by VHDL code. No need to worry.
This step is much easier than you anticipate it to be.
Inputs
Test Case #
1
2
3
4
Expected Outputs
X
0
1
0
1
0
0
1
1
0
0
0
1
Table 1: Test cases to be considered for VHDL Test Bench development
22. Look at the diagram below. Lines 50 to 70 have been inserted into the VHDL Test Bench.
These lines represent every aspect of Table 1 above. See how easy writing the VHDL Test
Bench for the and2 gate is.
23. Whenever you want to invoke a delay of say N microseconds you must use the directive
WAIT FOR followed by the number of microseconds. For example if we want to invoke a
delay of 100 microseconds we write:
WAIT FOR 100 us

24. We can also simply set inputs of the and2 gate by directly assigning values to them. For
example if we want to assign 1 to input A and 0 to input B we simply write the
following lines
A <= 1;
B <= 0;
25. We must finally invoke a delay, say 500 us to allow for the propagation of this test case and
its corresponding output for viewing.
26. Now observe how all four test cases from Table 1 have been represented in the VHDL Test
Bench.
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15

27. The VHDL code has been placed below for those of you all experiencing problems viewing
the diagram above.
WAIT FOR 100 us; --creates a delay of 100 micro seconds
--Test Case #1
A <= '0'; --assign 0 to A
B <= '0'; --assign 0 to B
--Test Case #2
--Test Case #3
--Test Case #4
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28. Now simulate the behavioural model for the system by first highlighting the VHDL Test
Bench source in the Module Window and double clicking on Simulate Behavioural
Model in the Process Window as shown in diagram below.
17

18

29. Initially when the test bench waveform appears it looks similar to the waveform shown
below. This is expected.
19

30. You must now double click on the Restart Icon in the Modelsim environment to restart the
wave. The icon looks like this:
31. A dialog box will appear as shown in the diagram below. Click on the Restart button. This
will restart the waveform.
20

32. Once the waveform is restarted it looks like the diagram below. There is no wave in the
Modelsim window. This is expected.
21

33. You must now double click on the Run-All Icon in the Modelsim environment to run the
entire waveform consisting of all test cases pre-set in the VHDL Test Bench source earlier.
The icon looks like this:
. The wave should resemble the wave in the diagram below.
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34. Finally we must click on the Zoom-All magnifying glass to display the test bench waveform.
35. The Modelsim environment consists of three magnifying glasses. One results in the
horizontally enlargement of the waveform. Another does the opposite. It reduces the
horizontal length of the waveform. The last (the solid dark blue magnifying glass) extends the
waveform to the maximum length specified in the VHDL Test Bench source so that the entire
waveform could be viewed without horizontal scrolling. This magnifying glass is the is used
to invoke the Zoom-All function.
36. All three magnifying glasses are shown in the small diagram below:
37. The resulting waveform is shown in the diagram below. Carefully look at the waveform, also
taking into consideration the waveform timing. Can you identify the parts of the waveform
which represents each line of code inserted in the VHDL Test Bench?
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Mini-Exercise
Add a new schematic file and insert a cb4ce counter. The schematic of this counter is shown
below. Write a new VHDL test Bench for the cb4ce counter. After writing the VHDL Test Bench,
simulate the behaviour of the cb4ce counter. Is it what you expect?
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THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

Writing VHDL Test Benches for Digital System Verification

THE UNIVERSITY OF THE WEST INDIES

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5. Click Next for the next three dialog boxes!

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15. Click Next!

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17. Click Next!

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Table 1: Test cases to be considered for VHDL Test Bench development

WAIT FOR 100 us

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. The wave should resemble the wave in the diagram below.

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