A Linear CMOS Voltage-to-Current Converter

Roger Yubtzuan Chen and Tsung-Shuen Hung

National Yunlin University of Science and Technology Electronics Engineering Department, Doulio, Yunlin 644002, Taiwan
chenrv@vuntech.edu.tw
Absfmcl--An improved CMOS voltage-to-currentconverter
is presented, PMOS transistors are employed in the
resistor-replacementand voltage-level shifting of the proposed
converter to avoid the body efrct. To accurately annihilate the
non-linear voltage terms, a better modeling of the
drain-to-sourcecurrent of the MOS transistor operating in the
linear region is essential and is adopted. Specifically the
substrate-bias effect of the MOS transistor is treated more
thoroughly in our design. Consequently, the non-linearityoP the
large-signal transresistance of the converter, caused mainly by
the body effect of a NMOS transislor in a previously published
converter, is greatly minimized. The voltage-to-current
converter is designed and fabricated in a 035 pm CMOS
technology. The,fabricated circuit occupies an area of 430 pm
x 260 p i (4.12mm') and dissipates I s s s than 2.2 m W from a
35 V supply. The measured and simulated data ate in good
agreement. For a 1 Vp.p input voltage, the total harmonic
distortion (THD) of the output current is less than 1.5%.

I. INTRODUCTION

The voltage-to-current converrers are employed in many

analog and mixed-signal circuits [1]-[3]. For example,
voltage-to-current converters serve as interface conversion in
switched-current circuits and signal processing. The
pcrformance of continuous-time current-mode signal
processing is a strong function of the interface circuits, such
as voltage-to-current converters and current-to-voltage
converters. Numerous analog computational circuits, such as
four-quadrant multipliers, can be constructed using the basic
voltage-to-current converters. Voltage-to-current converters
are used as basic building blocks to perform various
compurational functions, such as square-rooting, squaring,
multiplying, sum of squares, difference of squares, etc [4].In
addition, voltage-to-current converters are useful sub-circuits
in sensor interface circuits for biomedical applications [ 5 ] .
In order to circumvent the sheet resistance variation of the
polysilicon
resistors
used
in
the
conventional
voltage-to-current converters [6], a resistor-less all-MOS
voltage-to-current converter was presented [3], The resistor
employed in the conventional voltage-co-current converter is
replaced with two MOS transistors, one of which is operating
i n the linear region and the .other is operating in the
saturarion region, respectively..Although the drain currents in
each of the MOS transistors are nonlinear functions of the
input voltage, their sum, however, is made to be linear over a
wide range of input voltage. Because NMOS transistors are
adopted in the resistor-replacement and volrage level shifting,
the linearity of the voltage-to-current converter is degraded
mainly by the body effect of one of the transistor [3]. The
accuracy of the voltage-to-current converter is further limited
by relatively simplified modeling equations employed.

0-7803-9029-6/05/$20.00
02005 IEEE

Therefore the voltage-to-current converter suffers from

serious nonlinearity explicitly shown in its output
large-signal transresistance [3].
In this paper, we propose an accurate voltage-to- current
converter that does not suffer from the transistor body effect
and thus has a better linearity in its large-signal
transresistance. In addition, a. more accurate- modeling
equation to describe the drain-to-source current of a MOS
transistor operating in the linear region is employed, because
of which the linearity of the. large-signal transresistance of
the proposed voltage-to-current converter is further improved.
In some applications, the voltage inversion resulting from the
switching from NMOS transistors to PMOS transistors in the
resistor-replacement and voltage level shifting is
inconvenient, if not unacceptable. Thus a voltage-inversion
circuit is devised and placed in the input of the proposed
converter to circumvent this problem. Since the output
current i s proportional to the carrier mobility, its variation
with process will also be equal to the variation of mobility or
about f 15%. The improved all-MOS voltage-to-current
converter is compatible with submicron digital processes
where large-valued resistors are usually not available.

The proposed voltage-to-current converter is described i n .

Section 11. Section III covers a more accurate transistor
modeling equation
empIoyed , in the proposed
voltage-to-current converter. Simulation and experimental
results are reported in Section IV. Finally a discussion is
presented in Section V.
11. THEPROPOSED
VOLTAGE-TO-CURRENT
CONVERTER

In the proposed converter, WE adopt the same approach as

employed in [3], i.e., to replace the resistor of the
conventional voltage-to-current converter by two MOS
transistors, operating in the triode region and saturation
region, respectively, and combine their currents through a
current mirror to generate an output curredl which is a linear
function of the applied input voltage over a wide range of the
input voltage. The two resistor-replacement transistors,
however, are switched from NMOS transistors to PMOS
transistors to avoid the body effect, Level-shifting technique,
through the application of an operational amplifier (OPAMP)
and a large PMOS transistor biased at a small current. is
employed to achieve a condition required to annihilate the
non-linear squared voltage terms. For a p-sub n-well CMOS
technology, the body effect shown in the threshold voltage of
a PMOS transistor can be avoided and the accompanying
non-linearity of the output current is thus reduced.
The schematic diagram of the proposed voltage-to-current
converter is shown in Fig. 1 With OPAMPl and M18, MI9

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operates in the triode region for Vi, s W.I,

flowing through MI9 is thus given by

The current

converter, Fig. 1 .
IiI. TRANSlSTOR CURRENT MODELING

where B=pCoxWK . p is the camer mobility, Cox IS the gate

capacitance per centimeter squared, W is the channel width, L is the
channel length, VGS. Vos. VBs, and V, are the gate-to-source.
drain-to-source, bulk-to-source, and threshold voltages, respectively
The source-lo-drain current of M16,a long channel device and
operating in the saturation region, IS given by

Through OPAMPZ and M9, with a large W L ratio, as well as a

small current source implemented by M21 and M22, the output
node voltage of the OPAMP;! is ,level-shifted to V,,,'-lVt I. As a
result. we have IVGs1&VDD- Vi, 4- IV, 91. Consequently. the sum of
the currents flowinglhrough M19 and MI6 is
IDSZO

=! fDS19 +l1DS16 I

=&[(lVcsg I -IVl9 1) I Vm,I?

=

pig(I V

A 6

a,

~ SI ] I ~v,,9 I) I v,,,

I -*I

-vih+!v,9

O*

!-1v,16

I V D 1~ 2~A
] ~ ( I V I-I
~ V,
~ Le6 1)'

v,,,

121

In order to produce .a linear relationship between the applied

input voltage and the resultant output current, the amhilation of the
squared voltdge term by the converter circuit is essential. As shown
in (31. this also calls for an accurate modeling of the parameter a. in
addition to the level sbifting of the voltages. Therefore. a more
accurate modeling of the parameter a is included to further
minimize the non-linearity of the voltage-to-current converter. Note
that non-linearity of the large-signal transresistance of the converter
degrades the total harmonic distortion of the output current.
The drain current of a MOS transistor operating in the linear
region can be descrited by [ 7 ] .[8]

where y IS the body effect factor and Ds IS the surface inversion

potential. TI IS the drain-induced bamer-lowenng coefficient and is
given by

(7)

(3)

In order to speed up the circuit-simulation time. the dependence of

the drain currenion the substrate bias, specified by the function

For a p-sub n-well CMOS technology, PMOS transistor M9 can

be configured to be free of the body effect. Thus IVL91and Iv,)61
. cancel each other. Note that V ~ 1 9 = V ~ o - V , ,If
' . a19 is designed to
equal to Ul&d PIP, the squared voltage terms on the right hand
side cancel each other and we have
'cat

= IDS17 = ' D S m

=PIP(IVGS19(-/Vt101~(VDD

-'in)

is expanded in series [SI.It is approximated as

(4)

In some applications, the voltage inversion, Voo- V,n*,resulting

where g(@s-VBs) is determined by constraining (9) to give the best
from the employment of PMOS transistors in the
fit to F(Vos.%-VBs) in the desired voltage range. 11 is found [SI
resistor-replacement and voltage level shifting is inconvenient, if
that for.,0.7V5 (Vos,Ds-Vss) 5 20.7V over a range of OViVos
not unacceptable. %us a voltage-inversion circuit is needed in the
51OV.the factor g is given by
hput of the proposed voltage-to-current converter. A
voltage-inversion circuit is devised and shown in Fig. 2. The four
PMOS transistors are of the same size, (W~)pl,p2p3,~~=10cL/IO~.
Assume that P1 operates in the saturation region. The current of P1
The drain-to-source current for a MOS transistor operating in the
i s mirrored to P3. Both p2 and P3 operate in the saturation region
linear region can then be expressed as [8]
betause of their diode-connected .configuration. Thus
a
V;, =IV&=IVGSpIbVDO - V,, . ?he voltage-inversion circuit,
(11)
I D S = h ! ~ v G S - vt ) v , S
1
for 1.2V 5 V,,r 2.4V.
shown in Fig. 2, can produce V,'=V,-V,
n u s we have, from (4);
where V, i s the threshold voltage and is defined as

Tv6S

L'

By setting IVG~,~I
- iVtlgl to a fixed bias voltage, a linear
buland Vi, is o b t c n e d with p19 as the
proportionality constant. The sum of ISO~S and kola is
mirrored to Lut by a current mirror M20-Ml7. M23-M2X
form the bias circuit required by the small current source
M21-M22. Also because of the voltage inversion caused by
adopting the PMOS transistors, instead of NMOS transistors,
a folded cascode CMOS operational amplifier with an input
stage made of n-channel MOS transistors is designed and
used in ow converter. In order to minimize the effect of
temperature variation, a temperature-compensated current
souce, fbiLs,could b e employed to bias the voltage-to-current

relationship between

= 'FB

+ S'

'" f d w

-qvDS

(12)

and
a=1+.+

(13)

2 @ -vBs
Thus in order to describe the drain current of the MOS transistor
operating in the linear region, its dependence upon the substrate bias
should be accurately modeled as did in [ 7 ] . The factor g was
assumed as unity in the implementation of the.previous converter
131. Numerically the factor g, for most application. lies between 0.5
and 0.6. As a result, this could lead to error in calculating a,less
than ideal annihilation of the squared voltage terms, and eventually

678

voltage-to-current converter.

REFERENCES
P. P. Vervoort and R.E Wassenarr, A CMOS rail-to-rail linear
V-I converter, in Proc. 1995 IEEE Inkmarional Symposium
on Circuits undSystem, pp. 825-828, April 1995.

Iv. EXPERIMENTAL
AND SlMULATION RESULTS
The voltage-to-current converter is designed and fabricated
employing a 0.35um CMOS technology. Fig. 3 shows the
micruphotograph of the all-MOS voltage-to-current converter,
which occupies an active area of 0. t2mm2(= 430um x 26Oum).
The fabricated circuit dissipates less than 2.2mW from a 3.3V
supply. The measured ourput cumnt I, averaged over 8 samples,
as a function of the input voltage V, is shown in Fig. .4 as the
curve with diamonds. Also shown for comparison are the simulated
output current, the simuIated source-to-drain current5 of M19,M16,
as the curve with triangles, the curve with crosses, and the curve
with asterisks, respectively. The measured and simulated output
currents are in g w d agreement. Although the source-to-drain
currents in ,each of MI9 and M16 are nonlinear functions of the
input voltage, their sum, I, , however, is linear with respect to V,,
as described by (5). over a wide range of input voltage. he
input-output voltage relationship of the voltage-inversion circuit,
shown In Fig. 2, is given in Fig. 5 . h e measured and simulated data
are shown in diamonds and crosses, respectively. The measured
output voltage Vtn closely equals IO VDa - V,, for I .2V i V,,
52.4V.Fig. 6 shows the normalized (with respect to their own
mean values, respectively) large-signal transresistance of the
voltage-to-current converter as a function of V,, . The curve with
diamonds represents the simulated transresistances employing
u,,=1.25. i.e., employing the accurate g factor. Also shown for
coniparison is the curve with triangles which corresponds to the
simulated transresistances employing ai9 =1.50. i.e.. without proper
modeling of the substrate-bias effect. n e improvement of the
linearity of the large-signal transresistance of the voltage-to-current
converter, by including the accurate modeling of the substrate-bias
effect. is substantial. The total harmonic distortion (THD) of the
output current, as a function of the amplitude of the input voltage, is
shown in Fig. 7. The simulated data employing TT, FE, and SS
SPICE niodcls are shown in diamonds, asterisks. and crosses,
respectively. The rising of the THD with incremental input signal
unplitudes is attributed to the acconipanying increase of
non-linearjty. as shown in Fig. 6. For a , l Vp.pinput voltage, the
THD of the output current is less than 1.5%.

S . R. Zarabadi. M. Ismail. and C. Hunp. Hi h performance

analog VLSI computational circuits. /E& ~ O U m a i of
Solid-State Circuits, vol. 33, no. 4,pp.644-649, April 1998.

C. C. Hung, M. Ismail, K. Halonen, and V. Porra, A

low-voltage rail-to-rail CMOS V-I converter, IEEE
Transactions on Circuirs and Sysreins-IIb vol. 46, no.6,
pp.816-820, June 1999.

B. Palau, EV. Santos, J. M. Karam, B. Courtois, and H. Mus&,

New ISFET senSor interface circuits for biomedical
applicalions, Sensors and Actuators, B, 57, PP. 63-68, 1999.
R. Gre orian and G C. Temes, Ando MOS inregrated
Circuitsfor Signal Processing, New York &ley, 1986.

B. I. Sheu. D. L. Scharfetter, P. KO. and M. Jeng, BSIM;

Berkerl short-channel IGFET model for MOS transisto6
IEEE Youlna1 of.Solid-Stare Circuirs, vol. 22, no. 4, pp.
558.566, August 1987.

I? Antognetti and G Massobrio.

Semiconductor Device

Modeling with SPICE. New York: McGraw Hill, 1988.

V. CONCLUSION
Fig. 1 ?he schematic diagram of the proposed voltage-to-current

A lincar CMOS voltage-to-current convelter is described. We

employ two PMOS transistors, operating in the triode region and the
saturation region, respectively, and sum their currents by a current
mirror, as well as adopting level shift technique involving OPAMPs
and PMOS transiston to cancel the squared voltage terms. to create
an output current which is linear with respect to the applied input
voltage over a wide range of the input voltage. Since PMOS
transistors are used, non-linearity of the output current, caused
largely by the M y effect of a NMOS transistor in a previous
converter. is greatly reduced. A more accurate modeling of the
transistor current is also taken into account. T h e proposed
voltage-to-current converter shows a substantial improvement in the
linearity of its output large-signal transresistance and the THD of its
output currents. Experimental results of the fabricated converters
arc in good agreement with our simulation data.

converter.

ACKNOWLEDGMENT

Fig. 2 The circuit diagram of the voltage-inversioncircuit.

Financial support of National Science Council. Taiwan R.O.C.,

under contract no: NSC9 1-2215-E-224-OO8, and technical support
of the Chip Implementation Center (CIC), Taiwan, are gratefully
acknowledged.

679

Fig. 5 The input-output voltage relationship of the voltage-inversion

circuit, shown in Fig. 2. The measured and simulated data are
shown in diamonds and crosses, respectively. The measured output
voltage Vim'is closely equal to VDD- Vi, for 1.2V I Vi, 5 2.4V.

Fig. 3 The miaophoSographof the CMOS voltageto-cur" converter.

+*
1.2

1.6

2.0

2.4

Vin [Volt]

Fig.6 The normalized large-signal transresistance of the

voltage-to-current convener as a function of V,w The curves with
diamonds and the tnangles, respectively, represent the resultant
transresistances employing cr,,=l.25 and 1 50. i.e., with and without
accurate modeling of the substrate-bias effect, respectively
I

1.2

I .6

2.0

1.J

Vlll l V O l t 1

r:

Fig. 4 The measured output current I,,

as a function of the
input voltage V,, . is shown in diamond. Also shown for
comparison are the simulated output current and the simulated
source-to-drain currents of M I 9 and M16, as the curve with
triangles, the curve with crosses, and the curve with asterisks,
respectively. The measured and simulated output currents are
in good agreement.

3.0

'-...
I-.IU

0.0

0.2

0.4

0.6

Signal Amplitude [Vi

IR

0.0

Fig. 7 The total harmonic distortion (THD)of the output current as

a function of input voltage amplitude. The simulated data
employing IT. ET. and SS SPICE models are shown in diamonds,
asterisks, and crosses, respectively.
I.o

3.0

680