NOVEL CMOS SCHMITT TRIGGER

tions (3 /im and 5 /im) and three electrode widths (1 /im, 2 /im
and 3 fitn), the device areas were adjusted to obtain the target
capacitance values. A typical frequency response is depicted in

Indexing terms: Semiconductor devices and materials, MOS

structures and devices
A novel CMOS Schmitt trigger circuit has been realised,
using only five MOS transistors. The circuit always guarantees hysteresis, even with very large process variations. The
switching speed of the new Schmitt trigger is higher, compared to previously reported CMOS Schmitt triggers.

Introduction: The Schmitt trigger is a circuit that converts a

varying voltage into a stable logical signal (one or zero). The
DC transfer characteristic needs hysteresis to reduce the sensitivity to noise and disturbances. In many applications it is
necessary to control the hysteresis width from a few tens of
millivolts, up to volts. In the new Schmitt trigger circuit, this
hysteresis voltage is controlled by the dimension of only one
transistor. Even if the hysteresis voltage has been chosen very
small, the hysteresis is always guaranteed even under large
process variations.

Fig. 2 I/V characteristic of MIL PIN device

Fig. 3. The 3 dB roll-off frequency near 8 GHz appears to be

limited by the carrier transit time rather than the electrode
capacitance. This observation is also consistent with the
anticipated roll-off frequency of our largest detectors. (With
220 fF capacitances and 50 Q load resistances, the theoretical,
RC time-constant-limited bandwidth is 14 GHz.) Although it
is possible to attain even larger detector geometries without
affecting our observed 3 dB roll-off point, the limited real
estate available on an IC chip tends to discourage the development
of
extremely
large
detector
areas
( > 200 ;im x 200/^m).

The Schmitt trigger circuit: The integration of a CMOS

Schmitt trigger requires special circuits to cancel the resistors
commonly used in discrete Schmitt triggers.1 In Fig. la a
commonly used CMOS Schmitt trigger is shown, 2 ' 3 and in
Fig. \b the new CMOS Schmitt trigger. The new Schmitt

out

'dd

rfC
'int

M,M,

4&

Fig. 1
a Commonly used Schmitt trigger circuit
b New Schmitt trigger circuit

Fig. 3 Typical frequency response from 2 GHz to 8 GHz

Log of amplitude response is 5 dB/div and reference level is set at
10 dB. 5 dB fluctuations apparent in response curve between
3 GHz and 7 GHz are believed present because packaging has not
been optimised

trigger consists of two invertors (M 1; M 2 and M 4 , M 5 ) and an

extra feedback transistor (M3). It is this extra transistor that
always guarantees the hysteresis of the Schmitt trigger.
If Vin = Vss, Vint is high and Vout is low. It means that transistor M 3 is off. If Vin increases, the first invertor (M,, M 2 ) will
switch with a threshold voltage (VOi) defined by the transistors
M, and M 2 :

In summary, a detector design which can be implemented

on a substrate in common with other IC components allows
the fabrication of detector/amplifier ICs. We have demonstrated than an interdigitated MIL PIN device meets this
requirement without sacrificing the desirable features of high
speed and large detection area.
D. J. JACKSON
D. L. PERSECHINI

'out

1+ m

16th December 1985

(1)

with

Hughes Research Laboratories

Malibu, CA 90265, USA

l(kp(W/L)l\
References
1
2
3

SLAYMAN, c. w., and FIGUEROA, L. : IEEE Electron Device Lett.,

1981, EDL-2, p. 112; SUGETA, T., and URISU, T.: IEEE Transactions
Electron Devices, ED-26, 1979, 1855
FORREST, s. R.: J. Lightwave Technol., 1985, LT3, p. 347
DIADIUK, v., and GROVES, S. H.: Appl. Phys. Lett., 1985, 46, p. 157

ELECTRONICS LETTERS 13th February 1986

Vol. 22

where l^n, ^ p are the threshold voltages and kn, kp are the
transconductance parameters of the NMOS and PMOS transistors, respectively. If the first inverter is switching, the second
inverter (M 4 , M 5 ) will be switching as well. It means that M 3

No. 4

203

is switched on, and will generate positive feedback (Vint

1-82 V (Vtn = 0-7 V, Vtp = 0-78 V, kn = 40-7
kp p= 15-2
decrease> Vout increase M 3 is more on Vim decreases
/iA/V). The measured performance of the new Schmitt trigger
more* .. .) From this moment on the Schmitt trigger is in the
compares very well with the simulation.
other state.
If vin = Vdd, Vint is low and Vout is high. It means that transistor M 3 is now switched on, and works as a current source.
To switch the first inverter the threshold voltage Vl0 has to be
lower than V01 to compensate for this extra current sink from
transistor M 3 , or
v

(2)

2(1 + m)

with
kn(W/L)3\
n =

UW/QlJ

As soon as the input voltage is lower than Vl0, again positive

feedback switches the Schmitt trigger to the other state.
The hysteresis voltage of this Schmitt trigger is given by the
second part of eqn. 2 and can be controlled by (W/L) of transistor M 3 . As can be seen, there is always a hysteresis even
with large variations in dimensions {W/L ratio) or process
variations (kn, kp, Vtn and Vtp). If, for example, the parameter of
transistor M3(kn(W/L)3) is reduced by 50%, the hysteresis
width will be 30% reduced, but the hysteresis is still present
even if the hysteresis width is designed to be few tens of millivolts. In the previously reported CMOS Schmitt trigger, such
a large variation in one of the transistors M l 5 M 3 , M 5 or M 6
would cause the hysteresis to disappear if this is designed to
be smaller than 500 mV.
The advantage of this new circuit, compared with previously reported Schmitt triggers, is the higher switching
speed. This switching speed is limited to the slew rate of the
internal node (Vint). The slew rate is defined by the current
available divided by the load capacitor (C t ). In this circuit Cl
is only the gate-source capacitor (Cgs) of the next inverter
(only two transistors) and the drain-bulk capacitor (Cdb),
which in this case is negligible. In the Schmitt trigger of
Fig. la Cx is given by four Cgs values, whereby the extra two
transistors need to be very large for practical use, which
causes large values of Cgs. It means that in the first order the
switching speed of the new circuit is more than two times
higher for the same current consumption.
CMOS realisation and measurements: The new circuit has been
designed in a 3 /zm CMOS process. The design specifications
for the threshold voltages were: K01 = 2-5 V and Vl0 = 2 V.
The transistor dimensions are given in Table 1. The circuit has

Fig. 2 Simulated DC and AC transfer curve of Schmitt trigger

Fig. 3 Microphotograph of designed Schmitt trigger

Table 1 DIMENSIONS OF TRANSISTORS IN

DESIGNED NEW SCHMITT TRIGGER
W/L
Mt
M2
M3
M4
M5

5/7
5/18
5/40
5/7
5/18

-2
Fig. 4 Measured transfer curve of designed Schmitt trigger

Conclusion: A new CMOS Schmitt trigger has been designed

and measured. The relations to calculate the threshold voltbeen extensively simulated in SPICE level 2. In Fig. 2 the DC
ages and the hysteresis width are described. The hysteresis of
transfer and the AC transfer curve of Vint and Vout are given. As this new Schmitt trigger is always guaranteed, even with very
can be seen, the threshold voltages are VQl = 2-5 V and Vl0 =
large process variations. From the measurements, it is shown
2 1 V. The delay with a load of 200 fF is about 65 ns. In
that the new structure has a very excellent performance with a
Fig. 3 a microphotograph of the circuit is given. The Schmitt
very simple circuit.
trigger is used to realise a PDM-PPM convertor. In Fig. 4
measurement results of the integrated Schmitt trigger are
M. STEYAERT*
6th December 1985
shown. The input signal is a triangular wave. Out of this
W. SANSEN
measurement, the threshold voltages were deduced to be
Katholieke Universiteit Leuven
V0l = 2-48 V and Vl0 = 1-8 V (spread a = 50 mV). The differDepartement Elektrotechniek-Ajdeling E.S.A.T.
ences between measurements and the simulations are mainly
Kardinaal Mercierlaan 94
found in the used threshold voltages. The results of a SPICE
B-3030 Heverlee, Belgium
simulation using the extracted transistor parameters and
threshold voltages of that run are: V0l = 2-56 V and Vl0 =
* Supported by the Belgium IWONL
204

ELECTRONICS LETTERS 13th February 1986 Vol. 22

No. 4

References

assumed as a perfect error-detecting code, able to detect all

the error patterns, while nL = 2. The communication channel
introduces a white and Gaussian noise; by denoting the
channel error probability by p, the block error probability Pb
is defined as the probability that the channel will introduce at
least one error in a codeword, i.e.

RIDDERS, 'Accurate determination of threshold voltage levels of a

Schmitt trigger', IEEE Trans., 1985, CAS-32
2 BRANKO, 'Modified CMOS invertors', Microelectron. J., 1983, 14
3 NAGARAJ, SATYAM, 'Multistage monostable multivibrator using
load-coupled regenerative feedback', Electron. Lett., 1981, 17, pp.
159-160

= l - ( l - p)n

(3)

In Fig. 1 the throughput rj of Sastry's scheme and the pro0-5r

EFFICIENT ARQ TECHNIQUE USING SOFT

DEMODULATION
Indexing terms: Codes, Demodulation
In the letter a new technique for increasing the efficiency of
an automatic-repeat-request communication system is
described. This technique uses all the received versions of a
codeword, and also those versions containing errors. Such a
strategy, together with a soft demodulation of each received
symbol, is particularly efficient when applied to ARQ
schemes in which each block erroneously received is
retransmitted many times.

0 3

Automatic-repeat-request (ARQ) techniques are widely used

to improve the reliability of communication systems using
many types of practical channel. 'Stop-and-wait', 'go-back-JV'
and 'selective ARQ' schemes are the best known methods.1'2
Stop-and-wait and go-back-iV schemes present a lower implementation cost with respect to the selective scheme; on the
other hand, their efficiency falls rapidly with the increase in
the channel error probability.
Sastry3 proposed a modification of the classical stop-andwait and go-back-N schemes to increase the throughput by
reducing the wasted time spent in the waiting or in the
retransmission state. Each new codeword c is first transmitted
only once, while it is repeated i times when a repeat request is
received. Recently, a continuous ARQ scheme has been proposed by Moeneclaey and Bruneel,4 in which each block is
always transmitted N times, where N is the number of blocks
which can be transmitted during the round-trip delay.
In this letter it is shown that the performance of the
previous ARQ schemes, in which the same codeword is
retransmitted many times, can be significantly improved by
introducing a soft decision demodulation.5
A signal having amplitude dmA is used to transmit the
binary symbol dm (dm 1). Each information-bearing
sequence of k symbols is encoded into a codeword c through a
code of type (n, k). The positive signal region (0 A) is linearly quantised in nL levels; the quantisation step is d =
2A/(2nL 1); the upper level lies between A (d/2) and +00.
Similarly, nL levels are defined for the negative signal region.
With the /th quantisation positive level, the integer / is associated, and with the /th negative level, the integer /. We
denote by rjt m(t), for 1 < m < n, the received signal in the mth
symbol interval after j transmissions of c. The receiver quantises rjt m(t) and, hence, associates with it a positive or negative
integer Wj m (where nL < wjt m < nL). Then the reciever forms
a vector Zj whose mth component is given by5

0-2

classical scheme
Sastry's scheme
proposed scheme

0 1
10-2

[26i7T]

10'

Fig. 1 Throughput of a stop-and-wait scheme using a code (980, 960)

posed scheme is shown when a stop-and-wait strategy is used,

for the case N = 2, N = 3, 1 = 2 and i = 3. In Fig. 2 similar
results are presented for the go-back-JV strategy. Sastry's
scheme presents a higher performance with respect to classical
techniques only for very high error-rate conditions. On the
other hand, the conclusion of soft demodulation improves the
performance of Sastry's scheme significantly. However, the

0-8

06
'j,m ~

U-D,m

+ W'j.m

1 <m<n

(1)

since z0 m = 0. After each set of transmissions (i transmissions

in Sastry's scheme and N in the scheme of Moeneclaey and
Bruneel), the receiver performs a hard demodulation of Zj and
a binary vector Vj is generated in the following way:

if zL m < 0

0-4

1 < m < n (2)

0-2

If Vj is a codeword, then it is assumed to be the transmitted

codeword; otherwise, a new set of transmissions of the same
codeword is required.
The performance of this ARQ scheme has been evaluated
through computer simulation. A code (980, 960) is used and
ELECTRONICS LETTERS 13th February 1986

Vol. 22

10-2

classical scheme
Sastry's scheme
proposed scheme

Pb

10-1
""

1261/21

Fig. 2 Throughput of a go-back-N scheme using a code (980, 960)

No. 4

205