ABSTRACT

This project presents an improved circuit design of low power 1-bit full adder circuit. The circuit
is designed and implemented based on top-down approach using total number of 10 transistors,
thereby, known as 10-t cell. After simulation of the circuit, A clear view of the circuit
performance, in terms of power, delay, area was studied. The performance of the proposed circuit
was compared with other reported circuits in various literatures and observed approximately
more than 60% reduction in power consumption. The proposed cell gives faster response for the
carry output and can be used at higher temperature with minimal power loss. The drawback of
the circuit is that it
occupies larger area on the chip.

CONTENTS
TITLE
1.

PAGE NO.

INTRODUCTION
1.1 Introduction
1.2 VLSI Design Flow
1.2.1 Typical VLSI Design Flow in Three
Domains (Y-chart representation).
1.3 Design hierarchy
1.4 Overview
1.5 CMOS Logic Design Styles
1.6 Impact of Logic Style
1.7 Logic Style Requirements for Low Power
1.7.1Logic Style Requirements for Ease-of-Use
1.7.2 Static versus Dynamic Logic Styles
1.7.3 Complementary CMOS Logic Style
1.8 LOW POWER VLSI
1.8.1 Importance of Low-Power CMOS Design
1.9 The Low Power Design Flow
1.9.1 Power Analysis/Estimation and Optimization
1.9.2 Propagation Delays
1.9.3 Power Consumption in Digital Circuits
1.9.4 Static power
1.9.5 Dynamic power
1.10 Existing system
1.11 Proposed Circuit
1.12 Tools used
1.12.1 Languages used
1.13 : Organization of Thesis
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2.

IMPLEMENTATION
2.1 Adders

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2.2 Full Adder Circuit

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2.3 Existing XOR Design

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2.3.1 Existing XOR Waveforms

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2.4 DSCH design of existing 3T XOR cell

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2.4.1 Existing XOR 3-T wave form

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2.5 Existing XOR 4-T Design

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2.5.1 Existing XOR 4-T wave form

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2.6 Existing NAND gate

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2.6.1 Existing NAND Waveforms

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2.7 Block Diagram

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2.7.1 FULL ADDER Schematic Designs

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2.8 Full adder schematic-conventional style

(28 transistors)

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2.9 Full adder schematic using 24 transistors

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2.9.1 DSCH design of 24 transistor simulation

Waveform

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2.10 A novel full adder schematic 18 transistors

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2.10.1 DSCH Design Of 18 Transistor

Block Diagram Waveform

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3.

SOFTWARE
3.1 Micro wind

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3.1.1 Layout Design rules of CMOS

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3.2 Design Rules

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3.3 Micro wind 3.5 menus

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3.4 DSCH LIST OF ICONS

4.

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3.5 DSCH MENUS

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3.5.1 File Menu

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3.5.2 Edit Menu

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3.5.3 Insert Menu

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3.5.4 View Menu

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3.5.5 Simulate Menu

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3.5.6 Symbol Palette

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SIMULATION RESULTS
4 .1 Simulation and Results
4.2 Layout and Power Consumption

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Designs for Proposed Systems

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4.2.1 Schematic Designs and Power Analysis

4.3

DSCH design of existing 28 Transistor cell

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4.3.1 Layout of 28 Transistor

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4.3.2 Power Analysis of 28 Transistor

4 .4 DSCH design of existing 24 Transistor cell
4.4.1 Layout of 24 Transistor
4.4.2 Power Analysis of 24 Transistor

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4.5 DSCH design of existing 18 Transistor cell

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4.5.1 Layout of 18 Transistor

4.5.2 Power Analysis of 18 Transistor
4 .6 DSCH design of existing 10 Transistor cell
4.6.1 Layout for proposed 10 T cell

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4.6.3 Power Analysis of proposed 10 T cell

4.7 Discussion

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6.

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CONCLUSION
5.1 CONCLUSION
5.2 FUTURE SCOPE

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REFERENCES

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APPENDIX

7.
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LIST OF FIGURES
TITLE

PAGENO
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1.1

Chart

1
1.2

A More Simplified View of

2.20
4.1
4.2
4.3

VLSI Design Flow

Structural Decomposition Of A Four-Bit
Adder Circuit, Showing the Hierarchy
Down To Gate Level.
Block Diagram Of Representation Of 1 Bit
Full Adder
Schematic of Full Adder
Full Adder Truth Table
Existing XOR Design
Existing XOR Waveforms
DSCH design DSCH design of existing
3T XOR cell
Existing XOR 3-T wave form
Existing XOR 4-T Design
Existing XOR 4-T wave form
Existing NAND gate
NAND Waveforms
Full adder-conventional style
Full adder-functional timing diagram
Full adder-functional timing diagram (28T)
Full adder using 6T-XOR design
24 Transistor Waveform
Full adder 3 T cell design
18 Transistor Waveform
Transistor level implementation of 1-bit
10-T full adder circuit
1-bit 10-T full adder Waveform
Schematic Designs and Power Analysis
Layout of 28 Transistor
Power Analysis of 28 Transistor

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4.4
4.5
4.6
4 .7

dsch design of existing 24 Transistor cell

Layout of 24 Transistor
Power Analysis of 24 Transistor
DSCH design of existing 18 Transistor cell

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1.3

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19

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4.8
4.9

Layout of 18 Transistor
Power Analysis of 18 Transistor

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4 .10

DSCH design of existing 10 Transistor cell

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4.11

Layout for proposed 10 T cell

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4.12

Power Analysis of proposed 10 T cell

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