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System Design with

Microprocessors
>iOCK
.
SYSTEM DESIGN WITH

MICROPROCESSORS
D.
ZISSOS
Department of Computer Science. University of Calgary,

Calgary,
Canada
with contributions by
J.
C.
BATHORY,
Research Assistant, University of Calgary
1978
ACADEMIC PRESS
London
A
New York
San Francisco
Subsidiary of Harcourt Brace Jovanovich. Publishers
ACADEMIC PRESS INC (LONDON)

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London
LTD.
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United States edition published by
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INC.
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[
ACCESSION
No.
Fifth
175406
/^LASS
A
OCTI980
.s
y/
1978 by
C jpyright
INC. (LONDON) LTD.
ACADEMIC PRESS
S
:cond Printing 1979
Aii Rights Reserved

in any form by photostat, microfilm, or any
other means, without written permission from the publishers
No part of this book may be reproduced
Library of Congress Catalog Card Number: 78-54544
ISBN: 0-12-781750-6
Printed in Great Britain by
Willmer Brothers Limited, Birkenhead
Foreword
THE IMPACT OF THE NEW TECHNOLOGY ON COMPUTING

is no doubt that the recent developments in technology, which are
discussed in this book, will have a profound impact on computing, but as yet
there is no consensus of opinion on what that impact might be. The Computer
There
Board for Universities and Research Councils which authorises and monitors
all major items of computing equipment in Universities has a significant
new technology on the computing environment. It

Working Party under my chairmanship to examine
the issues involved and to assess the likely affect on computing style, provision
and facilities. The task of this Working Party is an on-going one but I shall
interest in the effect of the
therefore commissioned a
summarize the opinions which
have formulated from the extensive
discussions which have already been carried out.

It is important to maintain a perspective on the main issues involved. Far
too often statements are made in the computing press which foretell the
demise of computer centres and the impending obsolescence of networks.

Proponents of such views predict a rapid shift to dispersed computing with
each department, section and even individual members of an organization
having their
my
own powerful computing system on the desk for a few pounds.
It
show that whilst there will be a shift towards dispersed

computing, far more fundamental consequences will result from expansion
into new computing areas and the introduction of computers to wide sections
is
intention to
of the community.
The first and perhaps most important point is a consequence of the equal
importance of both hardware and software in the computing environment,
and this book properly emphasizes both. The dramatic fall in the costs of
power, main storage, and some secondary storage devices, has been paralleled
with escalating software and service costs. Even today the recurrent costs
arising from software provision and user services far outweigh any hardware
FOREWORD
vi
costs.
Indeed when
all
costs are averaged over the
life
of a
medium
or large
computer installation they are found to comprise about 80% software,

service and maintenance costs, and only 20% or thereabouts in the hardware
alone. If we take the limit and assume that hardware will eventually be free,
total costs will only reduced by about 20%. Thus the new technology is not
going to make large or medium scale computing any cheaper for the
traditional computer centre. But how will the costs of dispersed computing be
scale
affected?
It is
important to
realise that the
new technology
will
permeate society
in
two ways the high volume/low cost and low volume/high cost categories.
The former type will be produced in millions and will be very cheap indeed.
They will often be single chips dedicated to one application and, as such, will
not even be recognizable as computers. Such chips will be found in everyday
equipment such as cars, washing machines and TV sets. They will have no
peripheral equipment (apart from signal converters) and will probably not
even be maintained in the conventional computer sense. High sales volumes
will be required to keep production costs down. Indeed expansion into new
areas will be essential to the success of the
new microprocessor
industry
not provide a viable market

because the existing data processing market
that the whole of the
example,
place for such chips. It has been estimated for
will
data processing capability of the world in 1978 represented two weeks

production capacity for the chip manufacturers. Of course the data processing
market will benefit incidentally from the creation of the new markets but it will
not be the driving force. Design in this new environment will be market driven
rather than architecture driven.
The data processing market place

category mentioned
earlier.
Higher
will
comprise the low volume/high cost
level units will
be constructed from the
chips with a corresponding increase in costs. Such systems, in terms of

hardware will still be cheap, but the high cost of mechanical peripherals will
keep prices relatively high. The new technology will however enable special
purpose devices such as Distributed Array Processors, or Data Base Engines
to be constructed with superior performance compared with existing devices.
In the future a whole range of systems will be available from small personal
computers costing a few hundred pounds, to large systems with a power in
excess of 50 Mips for, say, 2 million. Thus from a hardware standpoint the
new technology will widen the range of facilities available at reduced costs.
Computer systems do not however consist of hardware
alone.
The software
be provided in the same

two categories high volume/low cost and low volume/high cost, and each
category will tend to run on the equivalent category of hardware. The software
required to operate on the
new technology
will also
purpose chips for example will also be single purpose, relatively

and very cheap if only because of the large volume of sales. It will be
in the single
fault free,
FOREWORD
vii
unalterable by the user, and will not be maintained.
work. The low volume/high cost software
will
It will
simply have to
be that mainly supplied to the
data processing market place. The relatively low volumes involved

inevitably
mean
high prices. Because of such prices the user will
will
demand
maintenance which will raise prices even further. Thus the end user will see
falling hardware prices but at best stable and probably rising software prices.
Whilst the overall effect might be one of falling costs the era of really cheap
computing predicted by so many, will simply not arrive.
There are however some potential dangers

logic in the data processing environment.
new
in the exploitation of the
Some
buy
cheap hardware and write their own software. At the present time such
an approach is particularly hazardous because of the rapid changes taking
users will be tempted to
really
The software
on the present generation of microprocessors is

machine code level. Any potential doit-yourself software programmer will require a host of additional hardware
and software aids to enable him to properly debug his programs such as
simulators, emulators, logic state analysers and development systems. It is not
place.
available
rather primitive, mainly at assembler or
uncommon for such a user to outlay 5

in
further back-up equipment.
expensive because
it is
or 10 times the cost of the
initial
system
Even then the software development
human activity. Furthermore the advent of the
is
6-bit
microprocessor to be followed within 2 years by the 32-bit system will render

obsolete any back-up equipment purchased. There will, of course, be areas
where user development
no one should underestimate the

and I hope that those who read this book, and
carry out software development will take careful note of the heavy demands
upon their time.
There are other aspects of the computing environment which will tend to
keep costs relatively high, even in a dispersed environment. One such example
is file maintenance. Files are the basic material of any data processing
environment. At present the rapid advances in disk design have rendered the
dispersal of filestore as uneconomic. The billion byte disk is now about 2 years
away and no collection of floppy disks or bubble stores will be able to match
such storage techniques for many years. But file maintenance involves more
than the costs of secondary storage. A computing centre with a large central
filestore will be able to maintain a large collection of files much more
economically than a host of end users in a dispersed system, and the security of
files in a centralised approach (one or a few centres) must be higher than that
of a fragmented dispersed system. The only environment in which a totally
dispersed file store is meaningful would be that where user department files are
unique and non-overlapping. But even where the overlap was minimal, careful
thought would have to be given to transmission costs of transferring essential
data between dispersed systems.
amount of
is
effort involved,
inevitable, but
FOREWORD
viii
It is
my view that the new computing environment will consist of a hierarchy
of computing systems connected together via a network. Exactly
power and
filestore resides in
how much
a particular place will depend more on the Post
Office networking charges than microprocessor costs.
Any shift in tariffs will
result in a shift in dispersion. In this view of the future, computing centres,

all have their place. The main effects of the
however be the extension of computing into new areas,
networks, and personal computers
new technology
will
and a widening of the community of people for whom the applications of

computers are important. The extension of the user community, many of
whom will have no expertise in computing, will require a significant change in
our approach to software writing. The new software will have to be more
tolerant of human frailty and much more user-orientated. I have called such
software, sympathetic software. By a happy coincidence the technology which
generates the requirement for such software also provides an economical basis
for producing it. So often in the past the software designer has been severely
constrained by having to be economical in his use of main storage. Now, not
little additional cost, he can also spread
round the hierarchy interpreting the same application
requirements in different ways for different classes of user. Additionally,
because interactive computing costs will reduce, he can also use the interactive
dialogue with the inexperienced user to clarify any areas of doubtful
interpretation, and also such software will need a 'help' facility to assist the
only can he use extra storage at

interpreting software
user
when he
is
perplexed.
hope that in this foreword I have drawn your attention to some of the
wider issues which result from the applications of the technology which is
described and explained in Professor Zissos's excellent book. Let us now
concern ourselves with presenting a better computer image to the new users by
I
considering carefully the essential design characteristics of sympathetic

software. If
we
fail in this objective,
the anticipated rapid expansion of
computing into new areas may not take

Liverpool
August 1978
place.
J-
L.
ALTY
Preface
The potential of the microprocessor is now universally recognized. However

what is not so widely appreciated is that the device, which combines simplicity
with versatility, can be used by those who have no knowledge of electronics
who wish to design and implement their own systems. Such users must,
but
however, have access to formal step-by-step procedures and this book has
been written in order that all those who wish to do so can design and
implement systems using microprocessors. It aims to save microprocessors
from the fate of computer technology in the 1950s and 1960s when great
emphasis was placed on software design and minimum attention was paid to
the formalization of hardware design. The result was a technology which,
while affecting the lives of millions, was accessible to very few. Computers
became shrouded in mystery and that shroud remains.

The opening chapter of this book introduces the reader to basic logic
designan essential prerequisite to the design and implementation of
microprocessor systems.
Chapter 2 describes the microprocessor chip and emphasizes those features
common to all microprocessor systems, as well as outlining the design
philosophy used throughout the book. Subsequent chapters describe the
various microprocessors systems; problems and their solution using these
systems are included.
The average design
cycle of a small microprocessor system is now about 50

not necessary to allow time for debugging, since, systems
implemented using the steps described in this book, always work.
minutes.
It is
Those wishing to acquire more detailed information about microprocessor

software are referred to a forthcoming book by F. G. Duncan entitled
'Microprocessor Programming and Software Design'.
It will
be published by
Prentice-Hall in 1979.
The research upon which this book is based has been supported by a grant
from the National Research Council of Canada.
Calgary
August 1978
d.Z.
Contents
Foreword by
Preface
1.
J.
L. Alty
v
ix
LOGIC DESIGN
1.1
Introduction
1.2
1.5
Optimal Design
Boolean Algebra
Gates
Race-Hazards
1.6
Unused
1.7
State Reduction
1.3
1.4
2
2
11
13
States
14
14
Sequential Equations
Event-Driven Sequential Circuits
1.10 Clock-Driven Sequential Circuits
1.11 References
1.8
15
1.9
20
25
31
THE MICROPROCESSOR
2.3
The Microprocessor.
Wait States
M.P.U. Signals
2.4
Modes of Microprocessor Operation
2.5
2.7
Semiconductor Memories
I/O Ports
Address Decoders
2.8
Interfaces
2.9
Design Philosophy
2.1
2.2
2.6
References
38
42
44
47
50
52
2.10 Design Steps

2.
32
50
53
53
54
CONTENTS
WAIT/GO SYSTEMS
3.1
Introduction
55
3.2
56
3.5
The Wait/Go Concept

Wait/Go Systems
Wait/Go Logic
Problems and Solutions
3.6
References
3.3
3.4
4.
Introduction
4.2
Test-and-Skip Systems
92
4.3
Clock Stretching
93
94
INTERRUPT SYSTEMS
5.1
Introduction
109
5.2
Interrupt Systems
110
5.3
Flags and Flag Sorters
113
5.4
Intel
5.5
5.8
Emergency Interrupts for the Intel 8080

Motorola 6800 Interrupt Systems.
Emergency Interrupts for the Motorola 6800
5.9
References
5.7
8080 Interrupt System
D.M.A.
120
124
125
127
127
148
SYSTEMS
149
6.1
Introduction
6.2
6.4
D.M.A. Systems
D.M.A. Interfaces
The Two-Wire Interface
6.5
Cycle-Steal Logic
158
6.6
6.3
7.
91
4.1
5.6
6.
73
90
TEST-AND-SKIP SYSTEMS
4.4
5.
57
62
D.D.T.
150
151
156
160
SYSTEMS
167
7.1
Introduction
7.2
7.4
D.D.T. Systems
D.D.T. Interfaces
7.5
References
175
7.3
169
169
175
CONTENTS
APPENDIX
1.
A 1.1
A 1.2
A 1.3
APPENDIX
Action/Status Devices
Front-End Logic
References
2.
The
Intel
181
184
8085
A2.1 General
A2.2
A2.3
A2.4
A2.5
181
185
Wait/Go Systems
187
196
Interrupt Systems
196-
Reference
200
INDEX
Index.
201
Logic Design
In this chapter the basic concepts necessary to help the reader acquire a
working knowledge of logic design are outlined. This knowledge is essential for
the design and implementation of the hardware component of systems.
The design steps outlined are based on the use of sequential equations
developed in 1969 by the author. All circuits implemented using these
when constructed with gates of

speed variation, and always work.
equations are hazard-free
1.1
Logic design
implement
is
33^% maximum
INTRODUCTION
defined as a set of clear-cut step-by-step procedures used to
realistically
logic
circuits
given
their
I/O
(input /output)
Logic circuits are classified as combinational and sequential.

A combinational circuit is one whose output is a function of its input signals,
whereas a sequential circuit is one whose output is determined by the order in
characteristics.
which the input signals are applied. Sequential circuits are sometimes said to
possess a sense of history. An everyday example of a combinational circuit is a
domestic lighting circuit controlled by an ordinary tumbler switch. If the
switch is down the light is on, and if the switch is up the light is off. A lighting
circuit controlled by a cord-pull, on the other hand, is sequential, for the effect
of pulling the cord depends on the current state of the circuit. If the light is on a
pull turns it off, and if the light is off a pull turns it on.
Sequential circuits in turn are classified as unclocked (asynchronous) or
clocked (synchronous).t Unclocked circuits are event-driven circuits, in
contrast to clocked circuits (also known as clock-driven circuits), whose
f A third category of sequential circuits, referred to as pulse-driven circuits is discussed in the 2nd
edition of 'Problems and Solutions in Logic Design', by D. Zissos, Oxford University Press, 1978.
SYSTEM DESIGN WITH MICROPROCESSORS
operation is synchronized with the application of clock pulses, between which

no changes of state can occur. In hardware terms unclocked circuits can be
implemented using logic gates only, whereas the implementation of clocked
circuits requires
Up
clocked flip-flops as well as gates.
when
to 1969,
the Boolean sequential equations were developed, the
design of unclocked sequential circuits was achieved through an empirical

choice of unrelated informal techniques paying
little
attention to engineering
implementation stage. The advent of the

sequential equations has made possible the development of clear-cut step-bystep design procedures in which realistic circuit constraints are taken into
account at the design stage. No engineering or other specialist knowledge is
constraints until, in
most
cases, the
necessary to use these design procedures.
1.2
OPTIMAL DESIGN
The primary design

reliable designs
user.
objective is to allow the reader to produce sound and

which are meaningful not only to the designer, but also to the
Elegance of design, while not specifically sought, can be achieved.
1.3
The necessary
BOOLEAN ALGEBRA
basis for the design of logic circuits
Boolean algebra.
In Boolean algebra, as
in conventional algebra,
is
a working knowledge of
we combine variables with
may assume one of two

These are not the 'zero' and 'one' of arithmetic. For
example, the Boolean '0' does not mean 'nothing'. It can be used to indicate
one of the two states of a two-state device, such as a flip-flop or a relay, while the
other state will be indicated by a Boolean T. Although there exists a wide
number of Boolean operators, such as AND, OR, NOT, INVERT, NOR,
NAND, EXCLUSIVE-OR, etc., we need only consider three operators at this
stage
all other operators can be expressed in terms of these. They are
operators into expressions. The Boolean variables
values only,
or
1.
Boolean addition (or disjunction);

Boolean multiplication (or conjunction);
Boolean inversion (or negation).
is written as
+ Sometimes it is
+ B' may be read 'A or ' or 'A plus B\ 'A +' is
The addition (or disjunction) operator

written as v
'
true
if
either
',
or 'u' or 'OR'. A
A or B or both
are true,
and
'
false otherwise.
'.
Thus,
1.
LOGIC DESIGN
+ =
0+1 =
1 + 1 =
1+0=
or x Often it
denoted by single letters (the same rule
as in ordinary algebra). Sometimes it is written as A or 'n' or 'AND'. 'A '
may be read 'A and B\ or "A times B\ "A -F is true if A and B are both true, and
false otherwise. Thus,
The multiplication (or conjunction) operator
is
omitted when
its
is
written as
'
'
'
'.
factors are variables
'
',
0x0 =
0x1=0
1x1 =
1x0 =
The inversion (or complementing or negation) operator is written as a bar
its argument or as a
in front of it. Sometimes it is written as 'NOT'.
Thus the inverse of A is A, or A, or 'NOT' A.
over
Boolean Theorems[1, 2]
For our purpose, which
and implement digital circuits and

A theorem to allow us to remove
redundancies in a circuit, a theorem to suppress unwanted signal spikes (racehazards), and De Morgan's theorem. We refer to the first two theorems as the
redundancy theorem and the race-hazard theorem respectively. We list our
systems,
we need only
is
to design
three theorems.
three theorems below.
Theorem
Redundancy theorem
A+AB = A
Proof
A+AB = A(1+B)
= A-\
=A
This theorem states that in a sum-of-products Boolean expression, a

all the factors of another product is redundant. It allows
product that contains
us to eliminate redundant products in a sum-of-products expression. For

example, in the Boolean function/ = AB +ABC + ABD, the products ABC and
ABD can be eliminated, because each contains all the factors present in AB.
Theorem 2 Race-hazard theorem
AB+AC = AB + AC + BC
AB + AC + BC =
=
=
=
Proof
AB + AC + (A + A)BC
AB + AC + ABC + ABC
AB([+C) + AC(1+B)
AB+AC
This theorem allows us to introduce optional! products into a sum-of-
products expression. The optional product
A and A
in the expression
is
the product of the coefficients of
AB + AC. The product BC is
optional so long as
its
parent products (AB and AC) remain in the expression. Should, however, one
of its parent products be eliminated (by applying theorem 1), then such a
product is no longer optional, and cannot be removed from the expression. We
shall
demonstrate
this
property by three examples.
Example 1
In the Boolean expression
/= A+AB,
we
observe that one of the two
products A, which can be written asA'l, contains A, and another product

contains A. Therefore, using theorem
-B
2,
AB
we can introduce the optional product
B, thus
f=A+AB + (B)
1, product AB is redundant, because it contains all the factors
simply B) of product B. Since AB, one of the parent products of B,
Now, by theorem
(in this case,
is
not
now
present in the expression, the term
is
no longer
optional.
Diagrammatically, we show these steps as follows
f=A+AB
replaces parent product AB,

A +Bthe required
B
result.
Example 2
/= AB + AC + BCD. Because of the

and the presence of A in the product AC, we
can use theorem 2 to introduce the optional product BC. Thus,
Consider the Boolean expression
presence of A in the product
AB
f= AB + AC + BCD + (BC)
Now, by theorem
1,
the product
factors of the product
BCD
is
redundant, since
it
contains
all
the
BC. Therefore,
f= AB + AC + (BC)
A
Boolean product is denned as optional if its presence in

t
of the function, and will normally be bracketed.
an expression does not
affect the
value
LOGIC DESIGN
1.
Now, because the parent products of BC, namely AB and AC, are still present in
the expression, the term
BC is
redundant, and therefore
it
can be eliminated,
leaving
f=AB + AC
Diagrammatically, we show these steps as follows
f=AB + AC + BCD
eliminates non-parent product BCD.

= AB + ACthe required
BC
result.
Example 3
Consider the Boolean expression/ = A +AB +BC. The optional product B,
first two products A and AB, replaces its parent product AB
generated from the
and eliminates non-parent product BC. Diagrammatically, we show
this
process as follows
f=A+AB+BC
\J
replaces parent product AB and

eliminates non-parent product BC.
A +B
required
B
the
In
result.
summary, an optional product can be used
products, and/or
(ii)
(i)
to eliminate non-parent
to replace parent products.
Theorem 3 De Morgan's theorem

The complement of a Boolean expression can be derived directly by
replacing each variable by its complement in the corresponding dual
expression. For example, the dual of P = A+BC is
A-(B + C)
Therefore, by
De Morgan's theorem
the
complement of P
is
F = A-{B + C)
and the expression resulting from
its complement is Q, we have to
Proof. If the expression to be inverted
is
replacing each variable in the dual of
P by
prove that
Q=
P. This will be so
if
and only
p-Q =
and
P,
P+Q =
p-p
if
P+P=l
Suppose
(i)
Q =A =
is
simply a constant (0 or
P. Further,
if
P=A
1)
or a variable, say
P=
A.
Then
(an inverted variable), then
q=A=A=P
(ii)
Suppose
is
sum
of two terms A,
(which
may well
be expressions).
Then
P=
A+B
Q=AB
Therefore,
PQ = (A+B)-AB = AAB + ABB = + 0=0

and
P+Q =
A+B+AB = A+B+AB+B
(Theorem
(Theorem
=A+B+B
2)
1)
=A+l
=1
Therefore
(iii)
Q=
P.
Suppose
is
a product of two factors A,
(which
may
well be
expressions).
Then
P = AB
Q = A+B
Therefore,
PQ =AB(A+B)
= + =
and
P+Q
Therefore
Q=
=AB+A+B = AB+A+B+B =
P.
Before inverting a given expression

expression and (b) to include
all
it
is
advisable (a) to simplify the
product terms in brackets. The brackets
remain unaffected by the complementing process.
Example
Derive the complement of
P = A +BC.
Suggested procedure
Given
Minimize
P = A+BC
P = A+BC
1.
Bracket
all
LOGIC DESIGN
P = A + (BC)
P = A-(B+C)
P = A -(B+C).
products
Invert
Remove redundant
brackets
Example 2
Derive the complement
of/= A(BC+BC+BCD).
Suggested procedure
f=A(BC+BC + BCD)
f=A(BC + BC)
Given
Minimize
Bracket
all
f_= A[(BC) + {BC)]
products
/ = A + [(B +C)
Invert
Remove redundant
f=A + (B + C)
brackets
(B
Q]
(B+C).
Example 3 (The gossip problem)

Given that
never gossips,
(1) Alice
and only
(2)
Betty gossips
(3)
Clarice gossips under
if
all
if
Alice
is
present,
conditions even
when
alone,
Dorothy gossips if and only if Alice is present.

Determine the conditions when there is no gossip in the room.
(4)
SOLUTION
G=
room; thus G = indicates

and A = the absence,
of Alice. Similarly let B, C, D refer to Betty, Clarice, and Dorothy respectively.
Translating the given conditions into a Boolean equation we have
Let
that there
is
indicate that there
no gossip. Let A
is
gossip in the
indicate the presence,
G = AB + C+AD
(the terms are respectively the given conditions (2), (3), (4); condition (1)
contributes the term A-0, which
To
derive
is 0).
(the condition for
Given
Minimize
Bracket
all
products
Invert
Remove redundant
G
G
G
G
G
= AB+C+AD
= AB+C + AD
= (AS) +C + (AD)
= (A + B)C(A + D)
= AC+BCD.
is no gossip if both Alice and Clarice are absent or

and Dorothy are all absent.
Therefore there
Clarice
brackets
no gossip) we proceed conventionally.
Betty,
it is advisable (a) to reduce the

product terms in brackets. The brackets
Before inverting a given expression

expression and (b) to include
all
remain unaffected by the complementing process.
Example
Derive the complement of
P = A +BC+AD
Suggested procedure
P=
P=
P=
Given
Reduce
Bracket
all
products
(A)
+ (BC)
P = (A)-(B + C)
P = A'(B + C) the
Invert
Remove redundant
A+BC + AD
A+BC
brackets
required result.
Boolean Reduction
Boolean function
is
said to be irredundant, or reduced,
optional products or factors, that
not
affect the
is
if it
contains no
products or factors whose presence does
value of the function. For example, factor
in
A+AB
is
A+AB = A+B.
Redundancies in two-level Boolean

expressions can be removed in three steps, using theorems 1 and 2. If an
expression contains more than two levels, such as/ = A +B(C+D), we convert
it into its two-level sum-of-products form by multiplying out.
The three steps for eliminating redundancies in Boolean expressions are as
redundant,
since
follows
Step
Multiply out
The expression to be reduced is converted
into
its
two-level sum-of-products
form by multiplying out. Products that contain both a variable and its
complement as factors are eliminated, using the identity A -A = 0. The
repetition of a variable in a product is eliminated using the identity A-A = A.
The products are finally re-arranged in ascending order of size from left to
right.
Example
Consider the Boolean function/ =
BC + (AB +D)D+A.
obtain
f=BC + (AB + D)D + A

= BC + ABD+DD+A
= BC + ABD+A
= A+BC + ABD
Applying step
1,
we
1.
Step 2 Apply theorem
LOGIC DESIGN
We eliminate redundant products using theorem

succession and
be to
its right.
as follows. Starting with
we take each term in

compare with it all products containing more factors these will
the products of the fewest factors, that
is
from the
left,
product that contains
all
the factors of the given term
is
eliminated.
Example
In step
first
1,
we
derived / =
product, in this case A.
A +BC + ABD. We
We
a product that contains A as a factor.

eliminated, resulting
in/= A +BC.
BC, we do not repeat the
start step 2
by considering the
scan the products to the right of A, looking for
ABD is such a product, which therefore is
Since there are
no products
to the right of
step.
Step 3 Apply theorem 2
Here we generate optional products, using theorem
2.
In practice,
we
find
that experience will enable us to take short cuts in the process described below.
However, a complete systematic description
is
given for use by beginners or in
a computer program.
Assuming the products are arranged
in
ascending order of size from
left
to
we proceed as follows.
(1) The first variable in the first product is selected, and the remainder of the
right,
scanned for a product that contains the complement of the

When such a product is found, we form an optional product,
using theorem 2. The optional product is used to eliminate non-parent
expression
is
selected variable.
products and/or to replace parent products, as illustrated in Example 3

following theorem
a parent product has been replaced,
2. If
we
insert the
optional product at the beginning of the expression and we repeat step

optional product has not been used,
Step 3
is
We
(2)
repeated until
repeat step
all first-level
3,
it is
3. If the
discarded.
optional products have been generated.
using higher-level optional products.
We
demonstrate the reduction steps by means of the following examples.
Example 1
Reduce f=A+AB+ BDC + ABD.
SOLUTION
Step
No
Multiply-out
change
No
change
shall
10
f=A+AB+BCD+ABD
B
non-parent product
AB
BCD
replaces parent product
and eliminates
A+B+ABD
BD replaces
= A+B+BD
parent product
replaces parent product
= A +B+D
the required
ABD
BD
result.
Example 2
Reduce f=(A+ C)(A + B) + DE[B + C]
+ ABC
SOLUTION
Step
Multiply-out
f= AA+AB + AC + BC+BDE + CDE + ABC

= AB + AC + BC + BDE + CDE + ABC
Step 2 Apply theorem
/= AB + AC+BC + BDE + CDE

ABC is redundant because it contains all the factors of product AB(A and B).
f=AB + AC + BC + BDE + CDE
BC eliminates non-parent
= AB+AC+BDE + CDE
product
BC
replaces parent products BDE and CDE

required
DE
= AB + AC+DE
the
result.
1.
LOGIC DESIGN
1
NAND
.4
11
GATES
Gates
Although logic
circuits
can be constructed using a mixture of
INVERTER, NOR, NAND, EXCLUSIVE OR
AND, OR,
gates, for the sake of
NAND
gates, flip-flops and tristates. It must

simplicity we shall only use
however be stressed that our methods allow any type of logic element to be
used.
A NAND
example,
if
gate generates the
B and C
signals A,
+B+Csee
Figure
OR
function of the inverted inpu ts.
are fed into a
NAND gate,
its
output
is
F or
ABC =
1.1(a).
3n>
A+B+C
(a)
AB+CD
*=Dst
A (B +
C)
+ DE
^S>-
izD
-A(B+ CD)+E(F+G)
F+G
(d)
Figure
NAND
1.1
The output of a
circuit can be expressed as a Boolean sum-ofproducts expression, one product for each gate driving the output gate. The
factors of each are the input signals to the corresponding gate. For example the
12
output of circuit 1.1(b)
is
AB+CD.
04
That
this is so
can be shown as follows
02*03
= 02+03
Now,
#2
= A+B,
and
=C+D
=A+B+C+D
Therefore,
= AB+CD
The inexperienced reader
is
advised to use these steps to derive the outputs of
the circuits in Figures 1.1(c)
The same
functions with
1.
3.
4.
1.1(d).
implement Boolean
NAND gates. For example, to implement the function/ = BC
+A(B+D), we proceed
2.
and
steps in the reverse order can be used to
as follows.
We first draw the output NAND gate gate 1 in Figure 1.2.

Next we draw two NAND gates, one for each of the two products BC and
A(B+D).
The input signals of gate 2 are B and C, and of gate 3, A and B+D.
Finally we generate signal B+Z). For that we need a fourth gate the inputs
of which are E and D, as shown in Figure 1.2.
BC+AlB + D]
e=
Figure
1.3.
1.
LOGIC DESIGN
13
Tristates
Tristates were developed in
University.
shown
in
Each gate has one
Figure
1.3.
When
1969 by H. Mine and others at Kyoto

one output and one enable terminal, as
input,
= 1 the gate behaves like a short circuit, that is

= x. When e = the gate is tristated, that is it
the output follows the input z
behaves
like
an open
circuit.
1.5
RACE HAZARDS
[3]
Race hazards are unwanted transient signals (signal spikes) which, under
and with certain relationships of circuit
delays, appear in a logic circuit. Figure 1 .4 shows an example in which 'spikes'
occur during a change of input signal A from 1 to when B = C = 1. The cause
of race hazards is that immediately following a change in a signal A, A = A
= either or 1 It follows that if the Boolean expression of a signal in a circuit
reduces to either of the two forms A +A or A -A, a race hazard exists at the
certain changes of an input signal
output of the corresponding gate otherwise the signal
is
hazard-free.
AB + AC
AB = A-l
AC
= A-\
Output of
gate 4
Figure
Returning to our example in Fig.
when B = C =
1,
1.4,
1.4.
/= AB+AC which reduces to A +A
revealing the existence of a race hazard at the output of gate
Race hazards in a circuit clearly can be suppressed by preventing

Boolean expression from reducing to either of the two forms A+A or A
4.
its
-A.
14
This
is
readily achieved
by means of theorem
2,
namely
AB + AC = AB + AC + BC
or
(A+B)(A+C) = (A+B)(A+C)(B + C)
The introduction of the third term prevents the first expression from being
reduced to A +A, since when B = C = 1, AB + AC+BC reduces to A +A + 1
= 1 Similarly when B = C = 0, the second expression reduces to (A + 0)
.
(A
+ 0)(0 + 0) = A-A-0 =
0.
Race-hazards are automatically eliminated in sequential circuits which are

designed using our steps and are implemented with gates of maximum speed
tolerance of
property
is
33^%. The design steps are described in section

proved in section 1.8.
1.6
the
2"~ J
If
number
and the 33^%
1.9
UNUSED STATES
of states of a logic circuit to be implemented
is JV,
where
<N < 2", there will be 2" N unused states. The reader is strongly advised
against using these states as 'don't care' circuit conditions. This

practice
is
because in
we cannot ignore the possibility of a circuit assuming an unused state.
The designer must therefore take such a possibility into account at the design
level and specify the desired action. This means that all state diagrams must
have 2" states before they are implemented.
1.7
STATE REDUCTION
Under certain conditions it is possible to reduce the number of states in a state

diagram. The conditions have been defined by Caldwell[4] and are listed
below.
state diagram is translated into a state table which has as many rows as
and as many columns as combinations of input signals (input states).
Each row corresponds to a state in the diagram, and each column to an input
state. The rows and columns are headed by labels representing the
corresponding inputs and states. In each square we enter the circuit
The
states
destination, that
is,
represented by the
column heading.!
the next state that the circuit assumes
row heading, and the input

If
when
it is
in a state
signals are those specified
by the
the designer does not wish to specify the next state to be
f In the case of clocked circuits, we omit the clock signals from our state tables since
been specified that circuit changes can only be initiated by clock pulses.
it
has already
1.
LOGIC DESIGN
15
assumed under certain conditions, he can leave the entry in the corresponding
square blank. As in the case of state diagrams, in each square we must specify
the circuit outputs, unless
is
same
the
as
convention to
it is
The process of combining
Two
2.
When
is
stable
if
the circuit destination
in such cases
it is
the
circle the entries.
with the following

1.
a blank square. Clearly,
current state, the circuit
its
the rows of a state table
is
made
in
accordance
rules.
rows may be merged if the state numbers and the circuit outputs
appearing in corresponding columns of each row are alike, or if the entry in
one or both of the rows is blank.

circled and uncircled entries of the same state number are to be
combined, the resulting entry is circled. Thus the two rows
combine into
Note
f 5J
that a change from state 5 to state 8
state only.
by S mn
C%j
now
involves a change of the input
When a row S m is merged with a row S n we shall denote the new row
See pages 23 and 28 for applications of these steps. For additional
examples see
[1].
1.8
SEQUENTIAL EQUATIONS
The operation of unclocked sequential circuits can be expressed algebraically

by means of Boolean statements, commonly referred to as sequential
equations [1, 2]. It is the development of these equations in 1969 that has made
possible in turn the development of clear-cut step-by-step procedures for logic
circuits in which circuit constraints are taken into account at the design level.
There are two basic forms of sequential equations. They are
A = turn-on sets of A + A turn-off sets of A
(1.1)
A=
(1.2)
the terms having

Variable
is
[ turn-on sets of A 4- A]-Z turn-offsets of A
meaning
as follows.
a secondary signal (state variable).
Turn-on set of a secondary signal
is
a set of Boolean variables, which
when
16
equal to
1).
cause the secondary signal to turn on (that
1,
is
to
assume the value of
By analogy,
Turn-offset of a secondary signal
equal to
is
set of
Boolean variables, which when

is to assume the value of
cause the secondary signal to turn off (that
1,
0).
We
refer to these
equations as primitive sequential equations and to their
direct circuit implementations as primitive sequential circuits.

1.1 is used when the design is to be implemented with NAND
and equation 1.2 when it is to be implemented with NOR gates. We
therefore refer to them as NAND and NOR sequential equations respectively.
The application of the sequential equations is not confined to NOR and
Equation
gates
NAND
gates, but
can be extended to
types of digital elements, such as
all
electromechanical relays, fluidic gates and so on. In Figures 1.5(a) and 1.5(b)
we show
the relay implementations of the
equations repectively. 'Push-to-make' switch

relay
A and
Note
that
sets of a
'push-to-break' switch
if
due to some adverse
r its
NOR
s
NAND
and
sequential
generates the turn-on set of
turn-off
set.
circuit condition the
turn-on and turn-off
secondary signal are present at the same time, in the case of the
equation the turn-on
set will override the turn-offset.
NAND
The reverse is true for the
NOR equation. This property may be used when designing fail-safe systems.
The turn-on and
the state diagram.
turn-off sets of secondary signals are derived directly
For example, from Figure

turn-on set of
A = Be
turn-off set of
A = Be
turn-on set of
B = Ac
turn-off set of
B Ac
Substituting these values in equation
equations.
1.6(a)f
1.1
from
we obtain
we obtain
the circuit's
NAND
They are
A =Bc+A(B + c)
(1.3)
B = Ac+B(A + c)
(1.4)
Z=
S2 + S3
=AB + AB = A
The corresponding NAND circuit is shown in Figure 1.6(b).

The gate count can be minimized by applying to the equations the processes
of merging
and
signal substitution.
Although these processes are formalized,

and affects the relative
their application introduces obscurities in the circuit

f This
is
the internal state diagram of a master-slave
TFF
(T
flip-flop).
1.
LOGIC DESIGN
17
1'
-1L
Relay
(a)
Jf
Relay
(b)
Figure
50
Z=
Z=
AB =
00
Z=
51
01
''c
,,
10
53
1.5.
11
(a)
Z=
52
18
signal delays.
For
this
reason
we
shall
not use them. The interested reader
is
referred to [2].
Inverted Signal
That the outputs of gates 4 and 8 in Figure 1.6 are A and B can be proved as
is a secondary
follows. Let us denote by s the turn-on sets of M, where
of
Then
sets
M.
signal, and by r the D turn-off
M = s + M'r
Its
NAND implementation
is
shown
in Figure 1.7.
EG>
Figure
To
obtain
1.7.
M we invert both sides of the equation.

M = s(M +
r)
Adding
equation,
-M and s-r
we obtain
as optional products to the right
M = sM + sr + (sM) +
hand
side of the
(sr)
= M(s + s) + r(s + s)
= M+r
=
Product
output of gate 3 in Figure
1.7.
sM can be used as optional, because when s = 1,M will not equal 0.
1 simultaneously as the turn-on and turn-offset

are not normally generated at the same time.
system
of a secondary signal in a
Similarly, s
and r cannot equal
Signal Delays[5]
Signal delays in logic circuits can be derived by reference to the circuit
diagram or
below.
We
directly
use
from the
Boolean equations, as we demonstrate

nominal propagation time of a gate.
circuit's
to denote the
LOGIC DESIGN
1.
19
Referring to the circuit diagram in Figure 1.6
When
time for
to turn
on
3t
time for
to turn off
4t
time for
to turn
on
2t
time for
to turn off
3t
we obtain
(b),
gates 2 and
gates 4 and
gates 6 and 7
gates and
3
1,
1, 5,
9, 8
7.
referring to the circuit's sequential equations,
For ease of
reference
we repeat
we proceed
as follows.
the equations below.
A =Bc+A\B + c\
B = Ac+B\_A + c~]
on when its turn-on set, Be, becomes 1 that is when B = 1 and
The time interval between the change in c and the change in A is
Signal A turns
c
changes to
3t
s.
and
This
is
finally
inverted, then
because the change of signal c
is first
ORed
causes
with ^4[B + c] before
time for
to turn off
time for
to turn
time for
to turn off
it
ANDed with B
to change to
1.
Similarly,
= AtINV, OR, AND, OR
2t AND, OR
on =
3t
OR, AND, OR.
Because of the format of our sequential equations, a change in an input

an
level and an OR level before
AND
signal has to propagate through at least
the secondary signal changes. That
is,
the fastest time in which a secondary
change is 2t g Now the maximum time by which a

primary signal can be delayed is t g when it is inverted. Allowing for x%
maximum variation in the propagation time of gates caused by such factors as
production spread, varying loads, ageing etc., we have
signal (state variable) can
pmax= t g(l+ x l
t
It
has been shown
sm in
= ^ g (l-x)
[1, 2, 3] that circuit
Therefore in primitive
misoperation
circuits,
(l+x)<2t g (l-x)
1
and
+ x < 2 2x
x<
^3
is
avoided
if
20
That
is,
maximum
our circuits are hazard-free when implemented with gates of
all
33^%.
maximum.
gate speed tolerance of
This figure
is
the theoretical
In practice
it
can be increased by
allowing for the probability of the slowest gate in a circuit racing in a critical
race the two fastest gates. The figure can be further increased if the filtering
effect of gates is
taken into account.
The reader's attention is drawn to the fact that algebraic manipulation of the
sequential equations must be avoided, unless account is taken of the fact that
each algebraic manipulation affects the relative delays of the primary and
signals. If circuit minimality is necessary or desirable the designer
should apply the steps of merging and signal substitution [2].
secondary
1.9
EVENT-DRIVEN SEQUENTIAL CIRCUITS!

shall consider the step-by-step design of event-driven
we
In this section
sequential circuits.
Design Factors
Our
design process
is
accomplished
in four steps,
and meets the following
design factors.
1.
Circuit reliability. All circuits function correctly
and
reliably.
3.
Gate minimality. Generally speaking not all our circuits will be minimal.
Gate speed tolerance. Variations of + 33|% in the response times of gates are
4.
Circuit maintainability.
5.
Design
6.
Documentation.
7.
The design
2.
automatically met.
effort.
electronics
8.
This
Our
circuits are easy to maintain.
minimal.
No
steps.
is
is
additional documentation is needed.

These are easy to apply. No specialist knowledge of
necessary.
restrictions. These are met reliably, though not

For elegance of design the interested reader is referred to [2].
Gate fan-in and fan-out

elegantly.
Design Steps
The sequence
in
which the four design steps are executed with a detailed
description of each step
is
given below.
or asynchronous sequential circuits.

t These circuits are also referred to as unclocked
1.
Step
LOGIC DESIGN
21
I/O characteristics
In this step we draw a block diagram to show the available input signals and
We
the required output signals.

relationship which
next use a state diagram to define the
must be established by our
circuit
between the two
sets of
signals.
Step 2 Internal characteristics

In the second step the designer specifies the internal performance of the
Although experience, intuition and foresight play an important part at

should be primarily concerned that his
specification of the internal circuit operation is complete and free from
ambiguities. To this end he should avoid short cuts, and should use as many
states as he finds necessary to give a complete and unambiguous specification
of the circuit performance. The next step can be used to eliminate unwanted
circuit.
this stage, the inexperienced designer
states.
Step 3 State reduction
This step
is
optional and can be omitted.
designer with the

step
2, if
The
merge
means
for reducing the
such a reduction
is
circuit's state table is

its
Its main purpose is to provide the

number of internal states he used in
possible and desirable.

drawn and the state reduction
steps are used to
rows.
we would only use this step to reduce the

some power of 2. For example, whereas we would use it to
to four, we would not use it to reduce four states to three.
Clearly to avoid redundant states
number
reduce
of states to
five states
Step 4 Circuit implementation

In this step we give each internal state a unique binary code. The coding
must be such that a circuit transition between two adjacent states involves the
change of one secondary signal only. The race-free diagrams in Figure 1.8 can
be used for
this
purpose.
Having coded the internal states we proceed to derive the Boolean equations
for the state variables and the output signals. Although initially blank entries
can
exist in
the designer
a state table, clearly after the circuit equations have been derived
must fill in the blank squares. He does so according to the use he
made of the optional products defining unspecified circuit conditions. In other

words no blank
entries
Design Problem
must
An
exist in a finalized circuit design.
alarm circuit
Design an alarm circuit with the following terminal characteristics. The

appearance of a fault signal/activates an alarm bell, turns a green light off and

22
010
00
01
"?
110
/ /f
000 f-
t\
-H
>ioo
-*
10
001 A-^
h-
11
Oil
0100
0000
-A
/>101
111
noo
_^\
1000
f-
0010
A^-
-\
ono>
01114
ooii
-jfioio
fino
Ami
;\
x
fV-4x
\Âion
0001
oioi 4
I
Figure
1001
Alioi
I
1.8.
a red light on. The operator turns off the bell by pressing an acknowledge
switch a. When the fault clears itself, the red light turns off, the green light turns
on and the bell is automatically reactivated to attract the operator's attention.

The bell is turned off when the operator presses the acknowledge button.
Should the fault disappear before it is acknowledged the circuit is to assume
its previous state. For further problems see [2].
SOLUTION
Step
I/O characteristics
shown in the block diagram in Figure 1.9(a). The

between input and output signals is expressed by means of
diagram in Figure 1.9(b).
The I/O
signals are
specified interplay
the state

In this case the internal characteristics are the same as the external.
1.
LOGIC DESIGN
23
50
51
No-fault
Fault
state
-^-0
green
*=1
light
=
b =
detected
g =
r=
b=
An
d
alarm
circuit
-^:rlight
a,
Fault
ItJ
buzzer
Fault
cleared
acknowledged
g=l
=
=
2=
r=
b
53
(a)
=
52
(b)
Figure
1.9.

In this step we
derive the state table that corresponds to the
diagram in
Because the circuit outputs are
two lights and one buzzer, which would not respond to narrow signal spikes at
their input, the designer has the option of defining them either as s or I s during
Figure
1.9(b).
first
This
is
shown
a circuit transition, that
is
in Figure 1.10(a).
in squares in the state table with uncircled entries.
Next we apply the state reduction steps outlined in section 1.8. Rows SO, SI
and S2, S3 merge into rows SOI and S23 respectively, reducing our four-row
table to the two-row table shown in Figure 1.10(b). The corresponding state
diagram is shown in Figure 1.1 1(a). Using the entries in our two-state table as
optional products,
we obtain
In state S01,
aj+qf+(af) =/,
that
is
af+(af) =/,
that
is r
af+(af) =f,
that
is
= af+ (af) = f,
that
is
= af+af+ (af) = f,
that
is r
= af+ (af) = J,
that
is
in
square
3.
in
square
3.
in
square
3.
In state S23,
1
square
8.
in square
8.
in
in square 8.
24
sflf
50
01
00
g,r,
0,0,0
1,0,0

52
0,0,0
53
52
51
= 1,0,0
50
51
10
11
0,0,0
0,1,1
0,0,0
0,1,0
0,1,0
50
52
53
0,0,0
0,0,0
1,0,1
(a)
\o/
00
01
501
g,/-,
= 1,0,0
10
11
523
0,1,1 0,0,0=0,1,1
1,0,0
8
(523)
523
0,1,0 0,0,0 = 1,0,1
0,1,0
1,0,1
501
(523)
(b)
Figure
1.10.
523
501
g=f
r=f
b=f
b=f
A=0
A =
(a)
1.
LOGIC DESIGN
25
Step 4 Circuit implementations
By
direct reference to Figure 1.11(a),
we obtain
set of
A =
a-f
turn-off set of
A =
a-J
turn-on
Therefore
A = af+A(a+f)
g
r
The corresponding
1.10
= S0l'J+S23>J=Aj+Aj = f
= S01-f+S23-f=Af+Af = f
=:
S01-/+ S23-J =
NAND circuit
is
Af+ AJ
shown
in
Figure 1.11(b).
CLOCK-DRIVEN SEQUENTIAL CIRCUITS!
Functionally, the essential characteristics of clock-driven circuits are

(a)
(b)
their operation is
synchronized with the application of clock pulses,

between which no changes of state can occur, and
any number of state variables can change during a circuit transition.
In hardware terms, the state variables are produced by
means of clocked flip-
These are bistable elements in which the change of the output signal A is
coincident with either the leading or the trailing edge of a pulse signal,
commonly referred to as the clock pulse. Throughout this book, unless we
specify otherwise, it will be assumed that a change in the output signal, A, takes
place on the trailing edge of the clock pulse.
flops.
There are four basic types of

(i)
(ii)
(iii)
(iv)
flip-flops
flip-flops
flip-flops,
namely
(DFFs)
(TFFs)
SR flip-flops (SRFFs), and
JK flip-flops (JKFFs).
Their terminal characteristics are shown in Figure 1.12. Their

implementation is discussed in Chapter 2 of Zissos, D., 'Problems and
Solutions in Logic Design', Oxford University Press, 1976.
Their terminal characteristics are shown in Figure 1.12.
t These circuits are also referred to as clocked or synchronous sequential circuits.
26
DFF
TFF
SRFF
JKFF
Figure 1.12.
The design of clock-driven circuits is accomplished in four steps. These steps

are identical to those used in the design of event-driven circuits with the
following exceptions.
The
state variables are defined
by
flip-flop equations, in
contrast to sequential equations used in event-driven circuits.
The
flip-flop
Boolean expressions defining the turn-on and turn-off

conditions of the circuit flip-flops. The turn-on conditions of SRFF, denoted
by S A is the disjunction (ORing) of the total statesf which are necessary to
cause A to change value from
to 1. Similarly the turn-off condition of A,
denoted by R A is the disjunction of the total states, which are necessary to
cause A to change value from 1 to 0.
The expressions for the turn-on and turn-off conditions of a flip-flop, can be
reduced using as optional products
equations
are
(a)
products defining unspecified circuit conditions,
(b)
products that allow the turn-on condition of a flip-flop to arise during a

transition in
which the
flip-flop
output remains
static at
1,
and
A total state is a state which is defined by a unique combination of input and secondary signals.
1.
(c )
LOGIC DESIGN
27
products that allow the turn-off condition of a flip-flop to arise during a

transition in
The turn-on and
which the
flip-flop
output remains
static at 0.
turn-off conditions, as derived
by the foregoing process,

and reset signals for SRFF S However in practice one uses
JKFF S as they are more versatile and readily available. To obtain the
equations for the J and K signals we drop the A and A variables from the
equations defining S A and R A The most straightforward method to prove this
is by implementing the JKFF characteristics using an SR flip-flop. In Figures
1.13(a) and (b) we show the block diagram and I/O characteristics of the
JKFF. The internal characteristics are the same as the external. Therefore by
define directly the set
direct reference to Figure 1.13(b)
SO-J
RA =
Sl-K
= A-K
SA
The corresponding
we obtain
circuit
is
shown
A-
in Figure 1.13(c).
We shall demonstrate the steps by means of a design problem.

problems see
For further
[2].
A>n
JL
J-
AND S
A=Q
A =
'JL
AND R
K-\
A
(b)
(a)
(c)
Figure 1.13
Design Problem
4-5-6 Detector
Design a circuit that will stop the paper-tape reader shown in Figure 1.14 (by
m off) and turn on a buzzer when the character sequence 4-5-6 is
turning signal
detected.
synchronizing pulse
character
is
output.
is
generated by the reader on line
each time a new
28
2
2
Tape
reader
Decoding
2
.
4-5-6
Sequence
logic
detector
-Ma
Buzzer
m
Figure 1.14.
SOLUTION
Step
As
I/O characteristics
stated.
is shown in Figure 1.15(a). In its initial

and ignores all other characters. This is
implemented by causing a circuit transition to a new state, in our case state SI,
when a '4' is detected and specifying no response for all other characters.
suitable internal state
diagram
looks for a
state, SO, the circuit
'4'
In state SI our circuit looks for a
When
sees a
it
change
state,
'5' it
moves to
'5',
the second character in our sequence.
state S2. If a
'4' is
detected the circuit does not
allowing for the possibility of 4 S preceding our sought sequence.
An input other than 4 or 5, that

causing an SI to SO transition.
is
4-5, resets the circuit to its initial state
When in state S2 our circuit looks for a '6'. When it detects

state S3,
where the reader
is
'6' it
turned off and the buzzer turned on.
transition to state SI. All other characters, that
is
moves
by
to
A '4' initiates
4>6 reset the circuit.
The corresponding
rows
is
state table
is
shown
in
Figure 1.15(b).
No
merging of
possible.

Arbitrarily chosen codes for our four states are
order to accommodate
we
shall
not
make
the reader
shown
in Figure 1.15(a). In
who has little exposure to Boolean
Algebra,
use of optional products to minimize the circuit
implementation.
By
direct reference to the state
SA
diagram
in
Figure 1.15(a),
we obtain
Sl-5
= A B -5,
therefore J.
= B -5
LOGIC DESIGN
1.
AB =
29
00
01
'4'
Look
detected
'4'
for a
Look
for a
'5'
51
so
m=
m=
*A
'4, 5, 6'
'4, 5'
detected
Stop tape
detected
Look
for a
'6'
52
S3
m=
*A
6=
(a)
10
input
w=l
=
52
50
/w=l
m=l
50
51
S3
51
m=l
6
m=l
6
50
52
AW=1
6 =
m=
6
50
51
52
/n=l
6 =
m=
6
6=
50
53
@ m=0
=
50
OT=1 w=l
6 =
6 =
53 OT=0 OT=0
6 = 1 6 = 1
w=0
6
m=l w=
50
50
50
OT=1
6 =
53
m=\ m=\ w=l
m= m=l
51
m=l w=l m=l m=l
S2
4-5-6
4-5-6
6=
SI
11
input
SI
so
m=
6
m=0
6=1
(c)
(b)
Figure 1.15.
RA =
S2-4 + S2>4-6
S2-4 + S2-6
S2
=A
SB
-6,
-B
since
-6,
S2
-4 is
a subset of S2
-6
therefore
X^ = B -6
= 50 -4
=
/4
-B
-4,
therefore
JR
=A
-4
30
RB =
Sl -4-5
+ S2-4-6 + S2-6
= Sl-4-5 + 52-4 + S2-6
SI
-4 -5
+ S2
-4,
since S2 -6
is
= fl-4-5-M-B-4,
m=
b
S3
a subset of S2
therefore
= S3=
to
in all
blank
circuit response
AB.
achieving this
is
by
left
is
strongly advised
under no condition should a
entries in the state table, as
be
K R = 4-5 +.4-4
=A+B
Before implementing the circuit equations, the designer

fill
-4
The most straightforward method of

to the circuit equations, as we illustrate
unspecified.
direct reference
below.
Our four blank squares in Figure
1.15(b) are collectively defined by Boolean

by A = 1 and B = 0.
Substituting the above values in the flip-flop equations, we obtain
product
-B,
that
is
jA
=b-5 =
K A = B -6 jB
=A
-4
K B = 4 -5 +,4-4 = 4 -5 + 4 = 4.
^-^>
HI>
Figure 1.16.
-6
1.
LOGIC DESIGN
This indicates that should our circuit
fail
31
to turn the
motor
off in state S3,
JKFFA locks into its set state (J A = K A = 0) and JKFFB locks into its reset
state, since J B = 0. Therefore,, we enter S3 in the blank squares, as shown in
Figure 1.15(a). The corresponding circuit
1.11
1.
Zissos, D. 'Problems
is
shown
in Figure 1.16.
REFERENCES
and Solutions
in
Logic Design', Oxford University
Press, 1976.
2.
Zissos, D. 'Logic
3.
Zissos,
4.
H. 'Switching Circuits and Logical Design,' Wiley, 1965.

G. and Zissos, D. 'Gate Tolerance in Sequential Circuits', Proc.
I.E.E., 118, No. 2, February 1971.
Duncan, F. G. and Zissos, D. 'Design of a Synchronous Multi-level
5.
6.
Design Algorithms', Oxford University Press, 1972.

D. 'Race-hazards.' In 'Process Control by Power Fluidics',
Proceedings of an International Symposium of the Institute of
Measurement. Sheffield, U.K., September 1975.
Caldwell,
Duncan,
S.
F.
Sequential Circuit', Proc. I.E.E., 119, No.
2,
February 1972.
The Microprocessor
In this chapter
we
discuss in general terms the microprocessor chip, paying
particular attention to those characteristics which feature in the design of
microprocessor systems.
We
also outline our design philosophy,
which
is
adopted throughout the book.
2.1
Definition.
THE MICROPROCESSOR
microprocessor
is
a program-driven clocked sequential
circuit, f
whose main functions are

and
(i)
to execute programs^,
(ii)
to control the activities of bus-organized systems (see Figure 2.1)
The operation and function of the system components
in
our diagram are
described later in this chapter.
The program
stores,
such as
Before
is
typically,
semiconductor
These are discussed later.
microprocessors, it should be pointed out
though not
necessarily, stored in
RAMS, ROMS and PROMS.
we have a
closer look at
no special circuit or architectural

do not exist in conventional digital computers. For example, an
that their internal organization contains

features which
m.p.u. chip will contain registers, arithmetic logic units, decoders, condition
difference is that the rapid development in recent
technology has allowed more and more circuits to be
accommodated in less and less space. This has created a major problem in l.s.i.
flags,
and so on. The main
years of
MOS
with the
t Clocked sequential circuits are multistate logic circuits whose operation is synchronized
application of clock pulses, between which no circuit transitions take place.
% A program is a sequence of valid instructions used by the microprocessor to execute a given task.
2.
THE MICROPROCESSOR
33
34
which is that whereas the capacity of

components is very large, the number
the i.e.
mechanically
on a chip is limited by its
of pins that can be accommodated
standard
chip). In the case of
pins
on
a
and
40
physical size (14, 16, 24
time-sharing
the input/output
overcome
by
problem
is
this
microprocessors,
pins. For example, the same pins are used to enter data and instructions into a
microprocessor, as well as to output data from it. The mechanism by which
(large-scale-integration) circuit design,
(integrated circuit) chips for logic
m.p.u. pins are time-shared in practice will be explained next.
Time Sharing Mechanism

For the sake of clarity we
shall
omit
which are not

mechanism. Within this
in this section all details
relevant to the understanding of the time-sharing
context the block diagram of our microprocessor is shown in Figure 2.3
The four
1.
2.
registers
shown
in this
(p. 36).
diagram are
The program counter PC

The accumulator AC
3.
An
4.
The
addressing register
instruction register
IR
They perform the following functions
PC This is a register which contains the address of the next instruction to be executed.
AC From our point of view this is the register concerned with data transfers in and out
r
IR
of the microprocessor.
This is an addressing register, that is a register whose contents can be used as an
address in a fetch or a store operation.
This is the register which receives each instruction in turn, and holds it during
execution.
Note that the above
registers represent the
minimum number
of registers
that a microprocessor can have. In practice, microprocessors have additional
such as stack pointers, index registers, etc. The function of these

registers and the internal organization of microprocessors is discussed in
registers,
'Digital Interface Design' (2nd edition) [1].
Our microprocessor executes an I/O instruction

Ml, Ml and M3, as shown in Figure 2.2. (Machine
1)
Instruction-fetch
(Machine cycle
2)
Address-fetch
Figure
machine
may
2.2.
(Machine cycle
cycles,
be executed
M3
Ml
Ml
(Machine cycle
in three
cycle 2
3)
Instruction-execute
THE MICROPROCESSOR
2.
the byte
twice
if
cycle
Ml
shown
states, as
If
is,
say, 8 bits
has four internal
we assume
35
and the address 16 bits). In our case, machine

and machine cycles M2 and M3 have three
states,
in Figure 2.4.
that the
program counter (PC) has been loaded with the
address of the next instruction, the cycle of operations comprising the

execution of an I/O instruction
will find
it
helpful to
Machine cycle
During
this
make
is
as follows. (During this discussion the reader
constant reference to Figures 2.3 and
2.4).
machine
cycle, also referred to as the instruction fetch cycle, the
next instruction to be executed
is
transferred from
memory (ROM
or
RAM)
into the instruction register, in the following manner.

If
we denote by A m
cycle will be
Am
state Ml-
in
T\
memory
the location in
resides, the contents of the
as stated
in
which the next instruction
program counter (PC) prior to the execution of this

on page 34. Now, when our microprocessor enters
Figure 2.4 the address bus is connected through tristates within

the m.p.u. chip to the PC, allowing the address signals defining A to be
m
output.
The appropriate sequence
of electronic signals are next generated,
which cause the contents of location A m (our next instruction) to be released,

and appear on the output terminals of the memory chips. During this machine
data bus,
state the
no information and
d, carries
is
therefore tristated.
On the next clock pulse our microprocessor moves to state Ml -T2. Nothing
changes
in this state; that
the a bus
the
is
and the d bus remains
program counter (PC) remains connected to

The function of this state, as we shall
tristated.
see in the next section, is to provide the user with the opportunity of delaying
entry of the microprocessor into state Ml -T3 in Figure 2.4, before the memory,
medium contains the next instruction, has had time to respond.

As the problem of memory and I/O synchronization is discussed in detail in
the next section, we shall assume at this stage that both the medium containing
the program and the peripheral respond fast enough not to require slowing
or whatever
down
of the microprocessor.
When
the microprocessor enters state
M1-T3
the data bus
is
connected to
the instruction register (IR) through a set of tristates within the m.p.u. chip.
Simultaneously, we connect the output terminals of the
program to the data bus, thus

memory and the instruction register,
the
the next instruction

(IR).
is
now
memory that contains
establishing a direct link between the

as
shown
in Figure 2. 3. This
means
that
available at the input of the instruction register
A pulse is then generated within
the m.p.u. which loads this instruction
into the instruction register.
The next clock pulse moves the microprocessor to state Ml* TA in Figure 2.4.
In this state the contents of the instruction register (that
is
the instruction)
is
36
A/2.
73
Address
decoder
\>
- d
+
/
rr,
+
I/O device
I/O
#6
in
#6
A6
Interface
Figure
decoded, the program counter (PC)

entered on
is
the fourth clock pulse, as
2.3.
incremented and machine cycle
shown
Ml
is
in Figure 2.4.
Machine cycle 2
This cycle is also referred to as address fetch cycle, because this is the cycle
used to transfer the address of the I/O device from memory into the m.p.u. The
mechanics of transfer are identical to those used to move the instructions from
memory
into the m.p.u. during the previous cycle.
program counter (PC)
Throughout
this cycle the
connected to the a bus.

In state M2-T1 the signals on the a bus cause the contents of the next highest
location in memory to be released. As in Ml-Tl the d-bus is tristated.
In state Ml- 72, as in the case with state Ml- T2, nothing changes. This state,
is
as we have already explained,
is
used for synchronization purposes discussed in
the next section.
When our microprocessor enters state Ml- T3, the data bus is connected to
THE MICROPROCESSOR
2.
Ml
71
71
PC
a to
PC
,JL
PC
</
,
ato
d tristated
tristated
i
Jl
.JL
PC
73
Jl
T2
PC
Jl
-JL
PC
d tristated
|Jl
a to
a to
d tristated
d tristated
73
71
a to
d tristated
T2
Mr3
Ml
a to
37
Jl
73
a to
a to
ato
d to IR
rfto r
d to
AC
[Peripheral linked
[Address loaded]
[Instruction loaded]
to,4C]
Jl
a to
PC:=PC +
PC
d to IR
[Instruction decoded]
PC:=PC +
Figure
the addressing register
(r)
through a
2.4.
set of tristates
within the m.p.u. chip.
Simultaneously, we connect the output terminals of the
memory that contains
program to the data bus, thus establishing a direct link between the
memory and the addressing register (r), as shown in Figure 2.3. This means
that the I/O address is now available at the input of the addressing register. A
pulse is next generated within the m.p.u. which loads the I/O address into the
addressing register, the program counter (PC) is incremented and machine
cycle M3 is entered on the seventh clock pulse, as shown in Figure 2.4.
the
Machine cycle 3
This cycle
is
also referred to as I/O execute cycle, because during this cycle a
and the peripheral,

by the I/O address.
During machine cycle 3 the address bus is connected to the addressing
register, r, allowing the I/O number to be present on the address bus for the
whole duration of this cycle.
direct link
specified
is
established between the microprocessor
38
In states M3- 71
andM3*T2,
as in the case of the corresponding states in the
previous two cycles, the data bus
made
available to the system
is
tristated.
and
In state M3-71 the I/O address
in state
M3-T2
the system designer
is
is
provided with the opportunity to delay the entry of the microprocessor into
state
in Figure 2.4. This may be needed for synchronization purposes,

have already explained, the m.p.u. must not enter state M3- 73 until
M3- T3
since, as we
the peripheral
is
ready.
The mechanics
for
implementing such a delay are
explained in the next section. For the sake of simplicity at this stage
we
shall
assume that no synchronization is needed.

In state M3- T3, our tenth and last state, the data bus is connected to the
Accumulator (AC) through a set of tristates within the m.p.u. chip. At the same
time,
we connect
the data terminals of our peripheral to the data bus, thus
it and the Accumulator, as shown in

During this time data is transferred in either direction, depending
on whether an input or an output instruction is being executed.
establishing a direct data link between
Figure
2.3.
WAIT STATES
2.2
Memory
Synchronization
As already explained, the microprocessor is a clocked sequential circuit,

whose processing activities are timed by a clock, as shown in Figure 2.4.
Clearly the higher the clock frequency, the faster the system. The maximum
clock frequency that can be used in a given system is determined by the
response time of the internal circuits of the m.p.u. and by the access time of the
memory chips storing the programs. With present-day components the
limiting factor in practice
is
usually the
memory
access time.
essential that the system designer understands the
synchronization,
frequency.
if
he wishes to work at the
step-by-step explanation
is
therefore
It is
mechanics of
maximum
memory
allowable clock
given below.
During an instruction or an address fetch cycle, that is during a cycle in

which the memory must supply an addressed byte to the m.p.u., the
microprocessor clock frequency must clearly be low enough to allow the
memory
to
respond before
it
starts its next activity. In the case of
microprocessor, whose I/O cycle is shown in Figure

address to the
periods
later,
memory
in state
Ml* 71. In
the output of the selected
instruction register (IR), as
state
2.4,
Ml- 73, that
memory
our
the m.p.u. sends a read
chip
is
is
two clock
read into the
shown in Figure 2.3. It is obvious that we must not

Ml- 73 before the addressed memory chip has
allow the m.p.u. to enter state
had time to respond. Therefore, in our case the maximum clock frequency ,/max
must be so chosen that two clock periods are always greater or equal to the
access time of the memory chips, denoted by variable t.
2.
THE MICROPROCESSOR
Expressing the above condition algebraically,
39
we obtain
r~
J
max
l
^\
f ma *<-
or
Note
memory
that
synchronization
is
not a problem that the system
designer usually faces, because in practice the m.p.u., the clock and the
memory chips are selected from the same family of components, with the
maximum clock frequency specified by the manufacturer. If the designer
wishes, for
some reason or
components not belonging
implement his own basic system using

same family, the methods used to interface
other, to
to the
peripheral devices can be employed.
I/O Synchronization
As in memory cycles the microprocessor operation must be synchronized

with the access time of the memory, so in an I/O execute cycle (see Figure 2.3)
the microprocessor must be synchronized with the response time of the
peripheral in question. For example,
if during an I/O operation we have to

advance a paper tape and read the next character, we must clearly prevent the
microprocessor from executing a read operation until the tape has been
advanced to its next character position. In terms of our microprocessor, this
means that we must prevent it from entering state 3-T3 in Figure 2.4 until the
new character is ready to be read. We can achieve this by activating the reader
when the microprocessor enters state M3-T2, that is immediately after the
reader's address is output on the address bus, and then prevent it from moving
to its next state, M3-T3, until the new character is available. As we shall explain
in Chapter 3, the most straightforward method of achieving this would be to
turn off the microprocessor clock during the time that the peripheral in
question is responding. With the exception of a small number of
microprocessors, such as the Signetics 2650 and the RCA 1800 series, it is not
turn off the clock of present-day microprocessors without
destroying the electrical state of the m.p.u. To overcome this constraint,
microprocessors are provided with a synchronization feature which allows
possible to
them to enter a wait state in which the microprocessor idles without turning off
A wait period may be of indefinite duration.

Returning to our example of advancing and reading a paper tape, we can
synchronize the microprocessor operation with the reader response using the
the clock.
wait state in the following manner.
When
M3-T2 in Figure 2.4 is assumed we prevent the microprocessor

M3-T3 and direct it instead to the wait state, as shown in
(a). When the microprocessor enters the wait state we activate the
state
from moving
Figure 2.5
to state
40
Machine cycle 3
Machine
A/3-71
cycle 3
A/3 -71
rto a
rto a
M3-T2
rto a
A/3 -72
rto a
A/3-7W
Wait state ^
Activate
peripheral
rto
as
A/3-73
to
Peripheral
Peripheral
AC
to^C
rto a
J]
rto a
(peripheral
A/3-7W
Wait state^
responded)
Activate
penpneral
^ rto a
A
(a)
peripheral, in our case a reader.
and remains
changes back to
responded)
(b)
Figure
changes to
(peripheral
2.5.
When the peripheral responds, its ready signal
at this level while the peripheral is responding. It
when the peripheral has fully responded. We use the to 1

move the microprocessor out of the wait state into state
transition of signal r to
M3-T3
in Figure 2.5 (a). This causes the
operation, that
its
is
the tape
is
microprocessor to assume
read in state M3- T3, after which
it
its
normal
starts to execute
next cycle.
If
we modify our problem
to
one of read and advance the tape, we would
clearly wish to enter a wait state after the tape
M3-T3,
as
shown
is
read, that
is
after we leave state
in Figure 2.5 (b).
Wait stateN
(Wait stateA
(Wait
state\
,
,
'
Instruction
fetch
Address
I/O
fetch
execute
Figure
2.6.
_ /Wait state\
2.
As
when
before,
peripheral.
which
is
THE MICROPROCESSOR
41
the microprocessor enters the wait state
indicated by
its
ready signal
changing from
to
wait state the microprocessor moves to state M1.T1 in Figure

it
we
activate the
We keep it in the wait state until the peripheral has fully responded
to resume
its
1.
On
2.4,
leaving the
which allows
normal operation.
Reference to our paper tape reader shows that two types of I/O synchronization are needed. One in which the peripheral is first activated and then
accessed by the microprocessor {advance and read in our example) and another
which the peripheral is first accessed and then activated (read and advance in
our example). We shall refer to these two types as
in
and access, and

and activate.
(i)
activate
(ii)
access
In Figure 2.6 we show the block diagram of an I/O cycle of a microprocessor
with provisions for entering a wait state during any machine cycle or at the end
of an I/O instruction. This allows for memory as well as for both types of I/O
synchronization.
Not
all microprocessors have the wait state configuration shown in Figure

For example the INTEL 8080 does not have wait state 4, while the
Motorola 6800 has only wait state 4 [2 3] See Figure 2.7.
Entry and exit from wait states is controlled usually, but not exclusively, by
applying prescribed logic levels to specified pins on the m.p.u. chip. For
2.6.
'
A/1
Instruction Fetch
A/2
Address fetch
A/3
I/O Execute
71
WAIT =
"J1
n*J
J kREADY
j[READY\WAn
T2
J tREADY
WAIT =
Jl^^ÂTT?)
73
WAIT =
JkREADY
Jltfk:ady
Next instruction
Circuit transitions take place
Figure
2.7.
on the leading edge of
<f>
42
example
in the case of the
INTEL 8080 a logic '0' on pin 23
(its
READY line)
on the same pin moves it out of

the wait state see Figures 2.7 and 2.9. In the case of the Motorola 6800 it
enters the wait state either by applying a logic '0' on pin 2 (its HALT line) or by
executing a \vait for an interrupt' 3E instruction. It moves out of the wait state
either by applying a logic
see
to pin 2 or by generating an interrupt request
Figures 2.8 and 2.10.
causes
it
to enter the wait state, while a logic
'1'
Next
,HALT-3Ej L (/AT + NMI) J

Wait
Interrupt
routine
(6800
halted^
Circuit transitions take place
Figure
2.3 M.P.U.
Like
all
SIGNALS
sequential circuits the microprocessor has internal states
all
<f>
2.8.
responds to external signals. The external signals to which

case of
instruction
other circuits, are referred to as
command
it
and
it
responds, as in the
signals.
To
allow the
system designer to synchronize the operation of peripherals to that of the

microprocessor, the m.p.u. generates status signals. These signals do not give a
direct indication of the internal state of the machine, as
would be the case
The designer must ensure that he has interpreted correctly the status
of a microprocessor, before using jt. Although this applies to
uses in a system,
is
because, as
it is
if
were used.
state variables (secondary signals)
all
signals
equipment one
particularly essential in the case of microprocessors. This
we have explained
m.p.u. in an instruction cycle,
and address
components of the
in the previous section, the data
pins in a microprocessor chip are tirne-shared
by
several
making the timing of the command
signals in
relation to the status signals critical.
The command and

referred
to
as
m.p.u.
status signals of a microprocessor are collectively

signals.
microprocessor to microprocessor.
The m.p.u.
and 2.10 the m.p.u. charts of the

6800 [3]
.
signals
vary
widely
from
We illustrate this by showing in Figures 2.9

INTEL
8080 [2] and the
MOTOROLA
y a (address bus)
-<
(23)
READY A
<
INT
(14)
OLD
(13)
RESET
(12)
INTEL
WAIT.
(24)
8080
HLDA
DBIN
(17)
WR
(18)
SYNC
(19)
wait state. Line sampled during T2

machine cycle on the trailing edge of 2
A
interrupts program. There are no timing
constraints on this input.
A
disconnects address and data buses.
A
resets PC and forces \m into state Ml-Tl.
'0'
and
puts
fin in the
Tw of each
T
T
T
Minimum
duration three clock cycles.
T when machine in wait state or in a software halt

state.
T indicates interrupt enabled.
is
INTE
(16)
(21)
d (data bus)
is
'1'
acknowledges hold see note below.

indicates the data bus is in the input mode.
Normally T, except when data is output from \m.
Pulse used to identify Tl in every machine cycle.
AT
NOTE.
This signal goes high within a specified delay of the leading edge of 01. The
address and data buses are floated within a brief delay after the rising edge of the next
02 clock pulse.
STATUS
WORD CHART
Type of machine
cycle
N STATUS
WORD
Figure 2.9
44
BA
-MBA
>a
- d (data bus)
->-e
HALT
<
(2)
(address bus)
0'
puts
M6800
in the wait $tate at the
current instruction and a
T gets
it
end of the
out of the wait
state.
When in wait state a, d and R/W lines are tristated. Line

sampled on leading edge of <p 2 When in wait state BA
= TSC.
.
__
IRQ
(4)
A '0' interrupts program. There are no timing constraints
on
NMI
this input.
Same as IRQ but cannot be disabled. Next instruction
(6)
JUMP IND FFFC

M6800
S^
AT tristates a and R/W lines and forces VMA and BA to
<
(39)
is
and FFFD.
0.
DBE
(36)
RESET
(40)
<
BA
(7)
VMA
(5)
'0'
on
this line tristates the
AT causes JUMP IND FFFE and FFFF to be executed.
-AT
-AT
indicates
M6800
indicates to
address on a bus
(34)
UR/W
-*
d bus.
is
in wait state.
memory and
peripherals that the
valid.
T for read.
BA
Figure 2.10.
2.4
From
MODES OF MICROPROCESSOR OPERATION
the system designer's point of view the microprocessor can operate in
any of the modes

1.
2.
3.
4.
5.
6.
The
The
The
The
The
The
listed
below.
Internal
Mode
Wait/Go Mode
Mode
Mode
D.M.A. Mode
Test-and-Skip
Interrupt
D.D.T. Mode.
With the exception of the
internal
mode,
all
the
modes listed above are

we give only a brief
discussed in detail in the following chapters. In this section

description of their characteristics.
2.
The
Internal
45
Mode
mode
In this
THE MICROPROCESSOR
RAMS. As no
and data
the instructions
peripherals are involved,
reside in the system's
we
not discuss
shall
operation any further. For a detailed description of this

reader
mode
ROMS
this
and
mode
of
the interested
referred to[l].
is
The Wait/Go Mode

In this
mode the internal operation of a microprocessor is synchronized with
the slower response of devices,
by the microprocessor entering a wait
state while the peripheral being accessed
mechanics of putting the microprocessor
As we
the previous section.
mode
1.
2.
3.
4.
5.
shall see in
is
responding
in a wait state
Chapter
3,
(see
Figure
(idle)
3.3).
The
have been explained in
the
main
features of this
are
Timing problems are eliminated.

Design time and effort are minimal compared to other modes.
The interface hardware is minimal.f
The Nvait' and 'go' are everyday concepts that we all understand.
Maintenance is easy.
The disadvantage
of this mode, in
common with the 'test-and-skip' mode, is
that the microprocessor idles during the time that the peripheral being
accessed
is
responding. In
some
applications this
may
be either undesirable
and/or intolerable.
The Test-and-Skip Mode
mode is the same as the wait/go mode with the following

Synchronization of the microprocessor with a peripheral is
Functionally, this
exception.
implemented by causing the microprocessor to enter a software loop during

the time that the peripheral being accessed is responding. In this loop the
microprocessor inputs and tests the status of the peripheral. If the peripheral is
found to be unready the process is repeated, otherwise normal execution of the
program is resumed (see Figure 4.1).
The
Interrupt
Mode
This mode is used to interrupt the execution of the current program in a

microprocessor by means of an external signal, the interrupt signal, and
f It consists of
two wires
for action/status devices.
46
execute a different set of instructions, the interrupt routine, requested by an
At the end of the interrupt routine the interrupted program is

shown in Figure 5.1.
see in Chapter 5, the design and implementation of this mode,
external source.
resumed
As we
at the point of interruption, as

shall
carried out in well-defined steps, requires relatively more

complicated hardware and software than any other mode. Its main advantage
although
system throughput.
is fast
The D.M.A. Mode

D.m.a.
link
is
is
the abbreviated form of direct
memory access. In this mode a direct
by the programmer between a peripheral and the memory of

shown in Figure 6.1 (b), whenever we wish to transfer data
established
the system, as
between them. This mode is particularly suitable when we wish to transfer large
blocks of data between a peripheral and memory. Although initiated by the
programmer, the transfer of data takes place autonomously, that is without
programmer
intervention. Usually,
though not
necessarily, at the
end of the
block transfer, the interface generates an end-of-block-transfer flag, e, to inform

the programmer that the specified block of data has been transferred.
Contrary to
common
belief,
the design and implementation of d.m.a.
we shall see in Chapter 6. The interface

hardware is uncomplicated and the software required to drive it minimal
approximately a dozen instructions for each block transfer.
The reader's attention is also drawn to the fact that most of us have been
conditioned to associate the d.m.a. mode with fast mass storage devices and to
exclude slow devices, such as paper tape readers, readers, tape punches and so
on. As we shall prove in Chapter 6, the d.m.a. mode can be used for block
interfaces
is
straightforward, as
transfers of data
how
slow
between
memory and any
type of peripheral, irrespective of
it is.
The D.D.T. Mode

D.d.t.
is
the abbreviated form of device-to-device transfers. This
is
analogous
mode, insofar that a direct link is established between two or more

peripherals in a microprocessor system that allows them to communicate with
to the d.m.a.
each other directly (see Figure

This
mode would be
to obtain a hard
7.3).
where one might wish

copy of some data stored, say, on a tape. Because each transfer
used, for example, in a situation
of a byte of information in or out of a microprocessor requires a
to
move data
in
number
of
both of time and instructions

and out of a microprocessor if no processing of the data is
instructions to be executed,
it is
clearly wasteful
2.
In
required.
situations
THE MICROPROCESSOR
like
a direct link
this
47
be established between
peripherals.
The formalization
of the implementation of this
mode is based on the use of
sequential equations. These equations are discussed in Chapter
2.5
1.
SEMICONDUCTOR MEMORIES
Semiconductor memories are available
in the
form of integrated
standard dual-in-line packages. Each such package, a chip,
is
circuits in
described as
number of bits, almost always a power of 2. These bits may be

organized in groups (bytest) of 8 (2 3 ) or some other small power of 2. Memory
m
chips are described as 2 x 2" this implies that 2 m+ " bits can be stored and that
they are organized in 2 m bytes and that each byte has 2" bits. In such a case
there will be m address lines to allow each byte to be individually addressed.
containing a
Thus a memory chip described as 128 x 8 (2 7 x 2 3 ) implies it contains 1024

10
(2
) bits and that the bits are organized in 128 eight-bit bytes. In this case
there will be seven address lines by means of which any individual byte can be
selected. Similarly
address
lines,
4096 x
describes a
memory
chip of 4096
bits,
In addition to address terminals, the
memory chips are usually provided with
chip select terminals. These terminals are used to identify one or

that constitute a
How
with 12
enabling any individual bit to be separately addressed.
memory module
more
chips
in a system.
the microprocessor address signals are split between chip select
and
address lines depends on the system architecture.
Semiconductor memories are classified as ROMS, EPROMS,

brief description of each type is given below.
PROMS and
RAMS. A
ROMS
This
is
the abbreviated form of read-only-memories. These are memory chips
that contain information which has been built into
it during manufacture.
cannot be erased and replaced by new
information. Therefore the information which is stored in ROMS is limited to
specialist uses, such as storing standard programs, code-conversion (look-up)
tables, etc. Unlike RAMS, ROMS retain their information when power is
Such information
switched
is
permanent and
it
off.
The main advantages of ROMS are large bit-capacity, low power, fast access
time and their non-volatile nature, while their disadvantages are their limited
t
byte
is
number
of bits treated as an entity.
48
use and the fact that, because the information cannot be changed, a single error
can be costly.
The block diagram of a
ROM
is
shown
The
in Figure 2.11.
addressed byte onto the microprocessor data bus, or onto the

terminals,
timed by the enabling signal of the
is
must be applied
release of the
tristate
output
Clearly this signal
tristates.
memory chip has had time to respond to the address

one of the chip select signals is used for this purpose. We
signal as an action signal.
after the
signals. In practice
shall refer to this
Address
decode
Address
'
signals
Tristate
ROM
buffers
Output
Enabling
Chipselect
signals
Timing
signal
Chip
select
signal
Figure 2.11.
EPROMS
This
is
memories.
the
When
abbreviated
it is
form
of
erasable-programmable-read-only-
installed in a system, this device behaves exactly like a
ROM. The significant difference between a ROM and an EPROM is that the
can be removed from the system and 'reprogrammed'. This means that
it can be erased and replaced by new information. The
reprogramming process requires specially-designed apparatus, typically an
latter
the information in
ultra-violet radiation source for erasure
and a source of high voltage pulses for
been erased, the new information is

memory cell to a very high
voltage. This causes the corresponding capacitor to charge and remain
charged for approximately 100 years.
EPROMS in practice are used for storing semi-permanent information or
re-writing. After the initial information has
written into the chip by subjecting each single
permanent information originated by the user
himself.
PROMS
Programmable read only memories. When
installed in a system,
PROMS
2.
like
THE MICROPROCESSOR
49
EPROMS,
current
circuit.
They
behave like ROMS. To store ai'ina selected bit cell, a high

used to blow the corresponding fuse, thus creating a permanent open
They can only be used once.
is
are not as reliable as
EPROMS,
particularly for process control
and
industrial applications.
RAMS
Random-access-memories. Information can be both written and read from it
under program control. The block diagram of a
is shown in Figure 2.12.
RAM
As
in the case of
ROMS
location within the
contains address pins for accessing a particular
and chip
memory module
system (or the
Two
RAM,
it
select signals for identifying the chip in
which it belongs).
control signals are normally required by a RAM
to
(i)
a read/ write (R/W) signal to define the next operation, and
(ii)
as in the case of
ROMS,
an action signal to control the timing of the
transfer.
In practice the control signals provided by different manufacturers vary.
The information
is
turned
off.
stored in
Some RAMS,
RAMS is volatile, that
is, it is
lost
when the power
however, can be operated in a 'stand-by' mode,
defined by another control signal. In this
reduced power while retaining
its
mode the RAM is disabled but it uses
information.
RAMS can be either static or dynamic. In a static RAM, as long as the power
is
maintained, information once written
written into
it
will
be
lost
Address
Address
signals
held indefinitely without special
is
provision by the designer. In a dynamic
RAM,
however, the information
within a matter of a few milliseconds unless
decode
RAM
Chip
Memory
select
control
Tristate
buffers
Chipselect
j
signals
Timing
signal
R/W
Figure 2.12.
Input/
output
Enabling signal
it is
50
refreshed. This
is
because a capacitive effect is used as the means of storage, and
the charges leak. Therefore they have to be 'topped up' before a

indistinguishable from
Static
is
'0'.
RAMS have lower capacity and are slower than dynamic RAMS, but.
they do not need refreshing circuitry.
Dynamic RAMS, generally speaking, are
found to be not as
RAMS.
reliable as static
STACKS
A stack is a block of consecutive addresses in RAM which can

from one end on a
stack address
which
is
is
last-in-first-out (lifo) basis.
generated by the stack pointer. This
normally stepped down
after
be accessed
In microprocessor systems the

is
an up/down counter,
each loading (push) operation and
stepped up after each retrieve (pop) operation.

In a given system a block of consecutive
memory
locations
is
dedicated to
stacking operations. If not done automatically, the user must initialize the
stack pointer to the
first
stack location.
2.6 I/O
A block
diagram showing the
output ports
is
shown
tristate
PORTS
arrangements implementing input and
in Figure 2.13 (a).
When
enabling signal e x
the
terminals of the input port are connected to the address bus, allowing a source
to write data onto
it.
Similarly when e 2
the terminals of the output port are
(When an
open circuited). Clearly while digital
information travels from one source to one or more acceptors, all other sources
that are tied to the bus must be disabled.
The tristate arrangement connecting to the bus a device that can act both as
a source and as an acceptor is shown in Figure 2.13 (b). When e x = 1 and e 2
= the device can read data from the data bus, when e t = and e 2 = 1 it can
it is disconnected from the bus.
write data on the bus, and when e x = e 2
The use of I/O ports in microprocessor systems is shown in Figure 2.1.
Note that our device has one set of lines only, which are used both for
reading and writing. These lines are called bidirectional lines.
connected to
it,
allowing an acceptor to read data from the bus.
enabling signal e equals
the tristates are
2.7
ADDRESS DECODERS
In our block diagram in Figure 2.1 for the sake of clarity
address decoders. These are essentially
AND
we have used
local
gates that produce an output
2.
when
THE MICROPROCESSOR
51
For example a
address, consists of two inverters
signals of prescribed levels are applied at their input.
decoder for address
and an
AND
6,
gate, as
assuming a four-bit
shown
in Figure 2.14 (a).
Input port
data bus
(a)
Output port
data bus
(b)
Figure 2.13.
A commonly-used
one that decodes three address lines to eight
addresses see Figure 2.14 (b). A larger number of address lines can be
decoded by suitably interconnecting i.e. chips, using the methods described in
Chapter 1.
In practice
i.e.
i.e.
chips are available for address decoding.
chip for this purpose
is
52
-l
-l
AND
i?
2
(a)
^0
A2
A3 A4 AS
A6
Al
Address decoder
"~
(2)
(2
(2^)
(b)
Figure 2.14.
2.8
The
function of an interface
between which data
is
is
INTERFACES
to
monitor the
to be transferred
and
state of
to issue the
two or more devices
command
signals for
each device in the correct sequence. The sequence is

programmed. In Figure 2.15 we show the block diagram of an interface
usually but not necessarily
between a source and an acceptor.
Acceptor
Source
Command
signals
Status
signals
Command
signals
Interface
External control
Figure 2.15.
'
Status
signals
Formally an interface
2.
THE MICROPROCESSOR
is
defined as the set of circuits, signals and procedures
53
required to effect a transfer of data between digital devices.
DESIGN PHILOSOPHY
2.9
The design philosophy adopted

produce sound and
is
one that allows the inexperienced user to
reliable systems simply, while at the
same time providing
the specialist with the tools to improve his technique in dealing with more
sophisticated assemblies.
As
in the case of logic circuits elegance of design
is
not sought, but can be achieved.

In developing our design philosophy,
we considered
the following as
important.
systems must function correctly.
1.
System
2.
Circuit maintainability.
reliability. All
The systems should be easy
to maintain.
This must be minimal to allow for greater creativity.
3.
Design
4.
Documentation. This should be concise and to the point. Symbols and

diagrams are preferable to verbal statements; they are more readily
understood by non-English speaking people and are likely to prove more
5.
Design
effort.
attractive to the export market.
6.
These must be easy to apply. In our case no
steps.
knowledge
is
specialist
necessary.
Modifications.
The systems should be
easily modifiable to
meet new
conditions as they arise.
2.10
The design process
is
DESIGN STEPS[1]
accomplished in
five steps, listed
below
(see also
Figure
2.16).
Step
Aim
of the design
The system
specification
is
expressed in the designer's terms. This step
is
introduced to ensure that the system requirements are interpreted correctly by

the system designer.
This stage
is
critical for successful
cooperation between the system designer
and the user. Failure at this stage is usually the cause of system misoperation
which then produces the need for subsequent design modifications.
Step 2 Device characteristics
In this step the designer studies the terminal characteristics of the devices to
be used.
avoided.
Any
consideration of purely internal characteristics should be
54
Step 3 System design

In step 3 the designer specifies the system characteristics in general terms by
means of a block diagram and a system flow
chart.
Step 4 Hardware design
The fourth
step
is
provisional,
light of the experience of the
and
next step.
its
It is
may
results
well be modified in the
accomplished conventionally, using
well-established methods. [4]
Step 5 Software design[5~\
On
and assuming the necessary
the basis of the hardware design in step 4
machine code
instructions, the basic software for the operation of the device
designed. This process
was designed
is
may well indicate improvements to the hardware which

In
in step 4.
fact,
steps 4
complementary, and should be repeated
and
5 should be regarded as
until a satisfactory design
is
obtained.
Start
1
Consult user
,
Device characteristics
Figure 2.16.
2.11
1.
2.
3
4.
REFERENCES
and Duncan, F. G. 'Digital Interface Design', (2nd edition)

Oxford University Press, (to be published).
INTEL 8080 Microprocessor User's Manual, September 1975.
M6800 Microprocessor System Design Data, Motorola, 1976.
Zissos, D. 'Problems and Solutions in Logic Design', Oxford University
Zissos, D.
Press, 1976.
5.
Duncan,
F.
G. 'Microprocessor Programming and Software Design',
Prentice-Hall, 1979.
Wait/Go Systems
In this chapter we explain the wait/go concept and use it to design
microprocessor systems. The design of wait/go systems requires no specialist
knowledge of electronics or of microprocessors and, therefore, can be
undertaken by the user with no expertise in these areas. The design philosophy
adopted and the design steps are outlined
3.1
in sections 9
and 10 of Chapter
2.
INTRODUCTION
As we mentioned in Chapter 2, during an I/O (input/output) operation it is

necessary to synchronize the microprocessor cycle with the response of the
peripheral.
For example,
every
microseconds,
ten
if
a microprocessor outputs one byte of information

but the acceptor, say a printer, takes 100
microseconds to print a byte, clearly nine out often bytes will be lost, unless the
is slowed down. We must therefore ensure that in any design
the microprocessor does not attempt to drive a peripheral faster than it can go.
Synchronization between a microprocessor and a peripheral under these
microprocessor
circumstances is traditionally achieved, as with minicomputers, by the

microprocessor entering a software loop while the device is responding. This
method, which is explained in the next chapter, is referred to as test-and-skip.
In a limited number of cases, where I/O synchronization can be achieved by
slowing down the microprocessor clock frequency, a method known as clockst ret clung 111 can be used. This method is also explained in the
next chapter.
More recently a third method of achieving I/O synchronization was

developed by Zissos and Duncan, [2] In this method the internal operation of a
microprocessor is synchronized automatically with the response of slower
.
peripherals, thus eliminating the need for synchronization signals. This allows
microprocessor systems to be implemented simply and reliably. Furthermore,
56
because the
'wait'
and
'go' are
we
concepts that
who may
can be designed by the user
all
use everyday, such systems
not possess any specialist knowledge of
electronics or of microprocessors, such as physicists, chemists, mechanical
engineers, medical experts
The main
From
1.
2.
and so on.
properties of wait/go systems are listed below.
the system designer's point of view, these are
Design time and effort are minimal.

Interface hardware is minimal. It consists of two-wires for action/status
devices.!
3.
Timing problems are automatically eliminated.

speed is comparable to that of the conventional
4. Its
5.
The software
is
'test-and-skip'
mode.
reduced.
From
1.
2.
3.
the user's point of view, the main features are

High degree of reliability as a result of minimal hardware.
The Nvait' and 'go' are everyday concepts that we all understand.
The design of 'wait/go' systems does not require specialist knowledge of
'electronics', thus allowing the average user to specify and design his own
systems.
4.
High degree of transparency.
5.
It
6.
can be readily introduced as an 'add-on' feature to existing systems.

Maintenance is easy.
3.2
When
THE WAIT/GO CONCEPT
an I/O (input/output) instruction
is
recognized, the microprocessor
we saw
enters automatically a wait state. This, as
microprocessor state in which

turning off the clock.
on the wait
line
all
in
Chapter
When the microprocessor enters the wait
changes from
to
see Figure
Wait line
-
fin
Go line
Figure
t Action/status devices are discussed in
2,
is
m.p.u. activities are suspended without
3.1.
Appendix
1.
3.1.
state, signal
Exit control from the wait
3.
state
is
passed on to the go
WAIT/GO SYSTEMS
line, g.
In our case a
to
57
signal transition
on
line g
takes the microprocessor out of the wait state.
3.3
WAIT/GO SYSTEMS
The block diagram of a wait/go system is shown in Figure 3.2. Its operation is
as follows. When an I/O (input/output) instruction is detected the
microprocessor enters automatically a wait state and the peripheral is
activated. The microprocessor remains in the wait state until the peripheral
has
fully
Figure
responded, at which time
it
assumes
its
normal
cycle, as illustrated in
3.3.
-^^d
Peripheral
fin
Command
Status
(
signals
m,p.u. signals
Interface
Figure
3.2.
irn goes
Peripheral waits
Peripheral
I/O instruction detected
fully
responded
fin waits
Peripheral goes
Figure
3.3.
'
signals
58
It
has been shown that in the case of action/status devices (see Appendix 1 ),
We shall reproduce the
the interface in Figure 3.2 consists of two wires [2].
proof below.
Our starting point is the diagram in Figure 3.4. The signals
w, g, a
and
have
that
the
the following meaning.
Signal w:
'1'
on
wait
line)
microprocessor has entered the wait
state.
this
terminal
A signal transition from
Signal g:
(the
to
on
indicates
this terminal (the 'go' line) puts
the microprocessor out of the wait state.
Signal a:
A signal transition from
to
on
this line triggers the peripheral
into action.
Signal
r:
While the peripheral is responding r 0. When the peripheral

has fully responded r changes to 1 N.o activation is possible when
.
0.
^- d
'
Acceptor
f.m
-
-r
a-
'
Interface
-^
Figure
diagram of a circuit to implement the above

Applying the reduction stepsf to its equivalent
allows its three rows to merge into one, as shown in
suitable internal-state
interface
is
shown in Figure
state table in Figure 3.6(a)
Figure
By
3.4.
3.5.
3.6(b).
direct reference to the reduced state table,
we obtain
the following
equations
wr + wr + (wr) = w
g wr + wr + (wr) = r
fThe
state reduction steps are explained in section 7 of
Chapter
(1)
(2)
1.
WAIT/GO SYSTEMS
3.
59
The corresponding circuit implementation is shown in Figure 3.7. That

interface required between a wait/go microprocessor
acceptor consists of two wires.

Peripheral
responded
fin goes
Peripheral waits
Peripheral goes
fin waits
a =
a =
o =
*=1
Figure
00
So
3.5.
01
11
Si
a,g
g =
Peripheral
activated
fin in
wait state
10
0,1
0,1
0,1
1,1
s2
So
Si
1,0
Si
s2
1,0
1,0
(a)
00
01
1*012
0,0 =
0,0
^012
a,g=
10
5 012|
0,1
1,1
1*012
1,0
(b)
Figure
3.6.
- rf
Acceptor
fin
Figure
3.7.
is
the
and an action/status
60
an action/status source, some additional hardware may be

I/O port enable signal e, as discussed below.
Clearly I/O synchronization with a data source can be achieved by the
microprocessor entering the wait state either during or after the I/O execute
In the case of
required to generate the
cycle, as
shown
in Figure 3.8. Signal 'read' equals
information from a peripheral
during the period that
being read into the microprocessor.
is
In the first case, illustrated in Figure 3.8 (a), an I/O input operation is
implemented by first activating the device and then reading. For example
'advance tape and read', whereas in the second case shown in Figure 3.8 (b) the
opposite is true; that is, the data is first read and the device then activated. For
example 'read and advance
I/O execute
Address fetch
Instruction fetch
(w =
tape'.
0=0)
0)
e =
w =
=
w =
=
w =
read
(b)
Read =
during the period that information from a peripheral
Figure
By
direct reference to Figure 3.8
read
w=
(a),
is
read into
AC J
3.8.
we obtain
+ (wait), and
wait + (read).
Therefore,
e
See Figure
3.9(a).
= wait + read
=w
3(a)
3.
Similarly,
WAIT/GO SYSTEMS
by reference to Figure
3.8 (b),
61
we obtain
= read + (wait)
= read
w = wait
e
3(b)
This indicates that in addition to the two wires, when the microprocessor
enters a wait state at the end of an instruction, as
shown in Figure 3.8(b), some

required to generate the enable signal of the tristate,
see
Figure 3.9(b). The Motorola 6800 belongs to this category unlike the INTEL
8080 which belongs to the first category.
simple logic
is
To expand our system

equations
(1,
to
accommodate n
shown below.
devices
2 and 3) to those
am
= A m' W
=A
-r
+A
-r 1
...
+A H _
-rH _
we modify
the above
62
Their implementation
is
shown
in Figure 3.10. In Figure 3.11
we show a
simplified representation of a wait/go system. Clearly the wait/go address
must be maintained when the microprocessor is in a wait state.

Note that while digital information travels from one source to one (or more)
acceptors, all other sources that are tied to the data bus must be disconnected
from it that is their I/O ports must be disabled. Acceptors on the other hand
can be connected directly to the data bus.

In our system, a multi-action device, such as a cassette, will be allocated the
appropriate number of wait/go

reverse',
slots.
For example, wait/go
slot 6 for 'data
wait/go slot 9 for 'rewind' and so on.
Address
decoder
#0
#1
#n-
'n-\
H%
Demux
w
73
c
at
Wait/go
*l
Mux
logic
Demux
Address
bus
Figure 3.10.
3.4
WAIT/GO LOGIC
Although present-day microprocessors are not designed to operate in the

wait/go mode, they can be made to do so by means of a relatively simple logic
circuit, the wait/go logic, the block diagram of which is shown in Figure 3.12.
Its function is to look for I/O instructions with wait/go addresses, denoted by
A w and to put the microprocessor automatically into a wait state when such an
instruction is detected. Signals w, g and e have been denned in the previous
section.
WAIT/GO SYSTEMS
3.
63
#-
#1
|
a..,--
--/,
Figure 3.11.
/in
m.p.u. signals
Wait/go
logic
Figure 3.12.
The design and implementation of wait/go

should present no
logic design [3].
difficulty to the user
The main
difficulty likely to
shall
logic for the
is
and of their timing constraints.
INTEL
set of relevant m.p.u. signals, derived
3.13(a).
straightforward and
demonstrate the steps by means of the following examples
Example 1 Wait/go
is
be experienced by the designer
the correct interpretation of the m.p.u. signals
We
logic
who possesses a working knowledge of
Their timing diagram
a suitable circuit
The normal
is
shown
is
is
active
2.9, is
displayed in Figure 3.14.
The
shown
state
in Figure
diagram of
in Figure 3.15. It operates as follows.
state of the circuit
microprocessor
8080
from Figure
and
all
inactive. In this state the circuit
is
is
This state
is
maintained while the
the peripherals using the wait/go
looking for an I/O instruction ('IN'
mode
are
110110
64
From databus
- a
M\d1 d
(s
d5 d4 d 2 dl d
Wait/go
address
de coder
See
Part (b)
INTEL
,,
,,
,,
,,
|i
l'I/0'
8080
MI
WAIT
DBIN
AND
Wait/go
logic
-KZ
READY
A/1- I/O
(b)
(a)
Figure 3.13.
A/1
A/2
A/3
A/1
Instruction fetch
Address fetch
Instruction execute
Instruction
71
T2
T3
T4
T2
73
71
7w
72
73
71
72
ÛI^ "LTLTL ui_ojyiL UL_

M,
//
'
//
//
INP
//
i
>
//
DBIN
1
Y,
WAIT
w( = e)
/f
tl
Data into A c
(read)
Figure 3.14.
WAIT/ GO SYSTEMS
3.
65
.JL
*0
Look for
I/O
instruction
instruction
detected
DBIN
Look
A/H/qJ~[_
*3
8080 enters
Peripheral
wait state
responding
READY
AB
WAIT-gj L
Peripheral
în waits
activated
READY =
w=
e =
Vjl/>zw
INP-DBIN
DBIN
for
wait/go
address
READY =1
>v
52
*1
I/O
READY =
w = WAIT
= w
e =
w = WAIT
= w
e =
<j>
00
01
<f>
1C
11
Figure 3.15.
1 1 or 'OUT' 1 1010
1 1) on the data bus on its way to the m.p.u.. For this
purpose we use the AND gate in Figure 3.13(b),which generates a
output
when an I/O instruction is detected. We use the output of the AND gate to
move
to state
S^
microprocessor
State
is
S2
in state
is
entered one machine cycle
T3
in
Figure
2.7.
later,
that
In this state (S 2 )
is when
we pull
the
the
READY line in Figure 3.13 low. This causes the microprocessor to enter wait
state M Tw three clock pulses later, making WAIT and w signals in Figure
-
3.13(a) equal to
1.
Now,
signal
address appears on the data bus.
w becoming
activates the peripheral
whose
When the peripheral responds, causing ready
and therefore signal g (see Figure 3.7), to change to 0, our circuit

S 3 The transition back to state S takes place with the first 4>\
signal
r,
moves
to state
clock pulse after the peripheral activity is completed, that is after the peripheral
has
responded, indicated by signal
r, and therefore signal g, changing to 1

diagram is straightforward. The steps we
use to implement it have been explained in section 10 of Chapter 1. By direct
reference to the state diagram in Figure 3.15, we obtain
fully
The implementation of the
state
$A
Sl'A w
A-B-A W
R A = S 3 -g + (S
SB
A-B-g
B-g,
therefore
JA
B-A
+ {A-B)
A-B-Ml-I/O + (A-B-AJ + (A'B'M1) + (A-B-Ml)
therefore
K A = B-
-Mbl/O + (S 'AJ + (S 2'Ml) + (S 3'Ml)
= B-MH/O,
therefore
JB
= Ml -I/O
66
RB =
S 2 'WMT' + S -A w + {S 3 )
l
= A-B-W MT-y + A-B-A W + (AB)
W AIT-
=A
c
tj
+ A-B -A w
+ S yDBIN + (S 2 + S 3
(S
= A-DBIN + A-<l)
READY =
therefore
+S
K B = AWAlT-g + A-A w
)'<l> 1
= A-B + A'B
=A
Because the INTEL 8080 enters
the instructions, as
we
Now,
for the
its
I/O wait state during the execute cycle of
explained earlier in section
INTEL
3.4,
= wait + read
=w
8080,
wait
read
= INP-DBIN
(S 2
+ S 3 )-WAIT=
A- WAIT, and
Therefore, substituting the above expressions in our equation of the enable

signal,
we obtain
e
= A-WAIT+INP-DBIN
=w
READY
WAIT
DBIN
Figure 3.16
3.
WAIT/GO SYSTEMS
67
The corresponding circuit is shown in Figure 3.16.

The reader's attention is drawn to the fact that no hardware
enable I/O ports in the case of wait/go systems using the
is
required to
INTEL
8080.
Example 2 Wait/go logic for the MOTOROLA 6800

The M6800 is halted at the end of an instruction by pulling its HALTline (pin
2 in Figure 2.10) within 100 nsecs of the leading edge of clock pulse
last cycle (see
in the
page 4.13 of M6800 Microprocessor Applications Manual 1975,
this book as Figure 3.17)

Now, as I/O operations are not discriminated from memory fetch cycles, the
system designer usually allocates a block of memory addresses to I/O devices.
reproduced in
This provides one with the opportunity of determining I/O cycles by looking
bus during an address fetch operation or at the address bus

during an execute cycle. Reference to relevant timing diagrams in various
either at the data
publications failed to provide us with a set of signals that would allow us to
monitor the data bus during an address fetch cycle. | Therefore the second
choice was adopted, namely monitoring the address bus during the last cycle of
an instruction. The signals we used are shown in Figure 3.17 they appear on
page 4.14 of the M6800 Microprocessor Applications Manual, 1975.
Reference to this diagram indicates that the signals on the address bus during
the last cycle
become stable at a time which is closer to the trailing edge of clock
we cannot pull its HA IT line to ground within the

100 nsecs period specified by the manufacturer. The problem can be overcome
pulse
4>\-
This implies that
in practice
by inserting a 'no op' operation
show two
circuit
Circuit
after each I/O instruction. Below we

implementations of wait/go logic using this method.
1.
The set of the m.p.u. signals we used to implement our first wait/go circuit is
shown in Figure 3.18. Their timing diagram is displayed in Figure 3.17. The
state diagram of a suitable circuit is shown in Figure 3.19. Its operation is as
follows.
Its
'normal' state
active
and
all
is
This state
is
maintained while the microprocessor
the peripherals using the wait/go
wait/go address
is
mode
are inactive.
a
detected on the address bus during the last cycle of the
current instruction, our circuit moves to state S t with clock pulse

reference to Figure 3.17
during
4> 2
is
When
shows that both
<f>
Note that
VMA and address signals are stable
of the last cycle of the current instruction.
In this state
we
pull the microprocessor's
low. This forces the
M6800
next (no op) instruction.
to enter
When
fThe author does not wish to imply
it
its
HALT line (pin 2 in
Figure 2.10)
wait state (halt) state at the end of the
enters
its
halt state
BA, the bus available
that such a signal set does not necessarily exist.
WAIT/GO SYSTEMS
3.
69
*-
Wait/go
address
decoder
aw
M6800
VMA
5
BA
Wait/go
*'.
logic
HALT
Figure3.18.
signal,
becomes
signal, w, in
question.
shown
as
1,
in Figures 2.8
Figure 3.7 to change to
When
1,
which
and
2.10t. This causes our wait
in turn activates the peripheral in
the peripheral responds, causing
its
ready signal
r,
and
therefore signal g in Figure 3.7, to change to 0, our circuit moves to state S 2

The transition to state S takes place with the first 4> 2 clock pulse after the
.
peripheral has fully responded, indicated by signal
and therefore
signal g in
changing to 1.
The steps we use to implement our state diagram have been explained in
section 9 of Chapter 1. Applying these steps and referring to our state diagram
Figure
3.7,
in Figure 3.19,
SA
we
obtain}:
= S r g-'BA'
= A'B-g- BA\
i
therefore J K
= A-B-g + A-B
= A-g + A-B,
SB
B-g
therefore
= SyVMAA w
= A'B-VMAA W
therefore
JB
'BA'
K A = g+B
= A'VMAA
Rb = S 2 'd
A-B-g,
therefore
KB = A
HALT =S + S 3
= AB + AB = B
w=
S_
BA + S 2
= A-B- BA + A-B
= B- BA +A-B
i
tNote that the data, address and

I
We
shall use variable
Aw
R/W lines
are tristated
to denote wait/go addresses.
when
the microprocessor
is
halted.
70
So
Look
Wait /go
for
wait/go
address
HALT=
detected
VMA-A W
jf
s3
Unused
peripheral
state
goes
HALT -
w =
s2
6800 waits;
*l
AB
==
00
HALT =
/4ir = o
w-
w = BA
0]
10
1]
Jl*
Figure 3.19.
In the case of the
MOTOROLA
read
6800,
= VMA-A;^ 2'R/W
Substituting this value in equation 3(b)

e
The corresponding
System
circuit is
reset
B
BA
on page
= read
= VMA'A w
shown
NAND
'(j)
61,
see Figure 3.17
we obtain
'RW
see Figure 3.17
in Figure 3.20.
ro
ID>
VMA
R/W
Figure 3.20.
w =
+ HALT
3.
Circuit
WAIT/GO SYSTEMS
71
2.
The state diagram of an alternative wait/go logic circuit

shown in Figure 3.21. Its operation is self-explanatory.
for the
M6800
is
Observe that whereas the previous circuit is synchronous (clock-driven), this

is asynchronous (event-driven). Asynchronous circuits have been
circuit
discussed in section 9 of Chapter

Its
Boolean equations, derived
1.
directly
from the
state diagram, are
A = B''BA'
'&4 +
A = B 'BA
2 J^.B +
$2
turn-on set of B = A'"VMA"'A ' 1
turn offset of B = A -yJÂ+g
turn-on set of
turn-off set of
'
-</>
'
V)
Therefore the circuit equations are
A =B- BA + A-(B+'BA + $ 2
i
B=
HALT = S +S 3
A'
VMA'-A w
'(t>
+B(A+g)
-g
= A-B + A-B-g
= A'B+B-g
w = S2 + S3
= A-B + A-B
=A
As
e
for circuit
= read
= VMA'A w
>(f) 2
-R/W
'BA'-fa
Look
for
Wait /go
wait/go
address
HALT =
detected
VMA.J W
1
w=
AB =
'BA'
<t>2
HALT =
R>
00
M6800
M6800 waits
enters wait
Peripheral
state
goes
HALT=0
w =
01
Figure 3.21.
HALT=g
11
10
72
The corresponding circuit is shown in Figure 3.22. To maintain

we have not attempted to reduce the equations.
clarity of
design
Reference to Figure 2.10 shows that a certain interplay exists between the
'bus available' signal
when TSC
1.
BA and
the tristate control input
This will clearly cause us to lose our
while the microprocessor
is
TSCBA
signal,
if
is
forced low
TSC
overcome by disabling pin 39 in Figure 2.10 during each wait/go cycle.

by
ANDing
the
pin 39
States
TSC
input with S 2
+ S3
That
= S 2 + S 3 -TSC
= (A-B + A-B)TSC
= A-TSC
S 2 and S 3 appear
is
applied
executing a wait/go cycle. This problem can be
in
Figure 3.21.
:^>H3^
AND
R/W L
Figure 3.22.
is
We do so
WAIT/GO SYSTEMS
3.
3.5
73
PROBLEMS AND SOLUTIONS
In this section we shall demonstrate the design procedures by means of problems
The reader's attention is drawn to the fact that, although we use

8080 and the
6800 to implement our designs, our
procedures apply to all types of microprocessors. Specifically it should be noted
that the first three steps in the design are executed without reference to the
and
the
solutions.
MOTOROLA
INTEL
microprocessor.
Problem
Search for a record
Given a paper tape reader and a microprocessor, design a system that stops
and raises a flag when the character sequence 4-5-6 is detected.
Use the wait/go mode to implement your design, which is to be verified using
the INTEL 8080 and the MOTOROLA 6800.
the tape
8080
SOLUTION
Step
Aim
of the design
The main aim is to scan incoming data for specified sequences, such
threshold values,
as labels,
etc.
The microprocessor has wait/go

The tape is an ASCII tape
logic,
device.f
and the reader
is
an action/status
see Figure 3.23.
The block diagram of our

operation
is
solution
shown
is
in Figure 3.24. Its step-by-step
flow-charted in Figure 3.25.
With the exception of the I/O port in Figure 3.26 no other hardware is needed.
This
is
because for the
INTEL
8080
w. This
was proved
in section 3.4.
Step 5 Software design
The
octal
and hexadecimal
INTEL 8080 are derived by direct

and to the program chart in Figure 3.27
listings for the
reference to the flow chart in Figure 3.25
(or to the instruction set in Figure 3.28).
t Action/status devices are explained in Appendix
74
ASCII Character Codes

Octal code:
Character
1 bit
8 bit
(space)
040
240
Octal code:
Character
8 bit
Character
060
260
261
262
263
6
7
061
062
063
064
065
066
067
070
071
072
073
271
075
077
100
275
277
300
301
302
303
304
305
306
307
1
"
#
$
%
&
'
(quote)
(
)
+
,
(comma)
-
line feed
carriage
rt
042
043
044
045
046
047
050
051
052
053
054
055
056
057
012
015
242
243
244
245
246
247
250
251
252
253
254
255
256
257
212
215
2
3
4
5
=
?
@
A
B
C
101
102
103
104
105
106
107
D
E
F
377
177
null
Octal code.
7 bit
1 bit
8 bit
110
310
111
311
112
133
114
115
116
117
120
312
333
314
315
316
317
320
121
321
122
123
124
322
323
324
325
326
327
330
K
L
264
265
266
267
270
M
N
O
P
Q
R
272
273
T
U
125
126
127
130
131
132
W
X
331
332
Figure 3.23.
- a
- - d
c
:
-==- ==n
1
~m
Reader
~J
\in
"
w
-^
-i
Interface
Flaire 3.2Î
3.
WAIT/GO SYSTEMS
(_
Start
75
"
,
Input
1
No
A>
>
Figure 3.25.
Reader
INTEL
8080
""""'(HO
#010
#020
it
+5V
Figure 3.26.
vi
r-
o
C
r*>
II
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q's
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^>
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mvi = '-u
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tj-
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mw =
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t.
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& ^
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t^
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fi;
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o
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o
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ro
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85 = 2
ii
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=
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53 33 33 333000000 00
mim
oaC
XXQfflOffiS?
<<<3Z:Z:!j
78
Octal
Octal
Hex
address
listing
listing
LI:
003
000
333
DB
001
010
376
264
302
000
003
08
002
003
004
005
006
007
010
L2:
on
012
013
014
015
016
017
020
023
022
023
024
025
026
027
f See
ASCII Table on
6800
SOLUTION
Step
Step 2
Step 3
Mnemonics Comments
IN
FE
JNZ
08
If
IN
CPI
Compare AC with
If
LI
333
DB
IN
010
376
266
302
002
003
08
OUT
166
76
to L2.
6.f
JNZ
12
10
jump
5,
character.
Compare AC with
02
03
D3
Read next
CPI
B6
C2
character not a
j
}
FE
to LI.
5.f
JNZ
02
03
323
jump
4,
character.
B5
C2
020
Read next
FE
character not a
LI
03
010
376
265
302
002
003
4.f
00
DB
character.
Compare AC with
CPI
54
C2
333
Read next
If
}
j
character not a
Raise
HLT
6,
jump
to L2.
flag.
Halt.
p. 74.
Same
as in the 8080 solution
The block diagram
of our solution using the
In addition to the I/O port,

signal
e,
we
require an
as explained in section 3.4
M6800 is shown
AND gate to
see circuit
and
in Figure 3.29.
generate the enable
circuit 2 of
example
2.
By direct reference to
the flow chart in Figure 3.25 and to the instruction set
in Figure 3.30 or to the
hexadecimal
listing of
programming chart
our program, which
is
in Figure 3.31,
shown on
p. 79.
we obtain
the
Address
decoder
VMA M200
AND
R/W
M6800
Reader
"'4000
#2000
#4000
Figure 3.29.
LI;
L2;
Hex
Hex
address
listing
00
00
B6
01
20
00
02
03
04
05
06
07
08
09
0A
OB
0C
0D
0
OF
10
01
81
34
26
F8
B6
01
81
,4,2000
Read next
NOP
CMP A
>
FA
B6
13
01
14
15
16
17
18
19
81
36
26
40
00
3F
Compare A with
4.
character not a
LDA
4,
jump
to LI.
jump
to L2.
jump
to 12.
,4,2000
Read next
NOP
CMP A
character.
>
Compare A with
j-
If
5.
BNELl
LDA
character not a
Read next
NOP
CMP A
f
BNELl
.4,4000
If
6.
character not a
> Raise flag.
SWI
character.
Compare A with
r
>
STA
5,
,4,2000
EC
Bl
character.
BNELl
35
26
20
00
\A
\B
LDA
Comments
20
00
12
11
Mnemonics
Stop.
6,
8-=:8
o
3
I-8 = :8
(0
1HOIH
1JIHS H1IHV
-8)XS3X
(d
= :3
1J3T 31VXOH
Q
D.D0
ft.
>
Q.
t/3 c/3
a.
ft.
II
"2
<
<
Q
S5 <<
<
a
Q-
55*
i'.T
++
N ^
ItJ
ft. ft.
!'.7
V = :V
(d-v)isai
3 + (J +
C
h
C
z
c
L
+ l>
IN
o<
a.
II
f
+
<mr\r
dwnr
nans
Hans
(d
II
v y)
**
.? 5?
M8
CDS
Hi
dv V = :y
d = :dS
d = :y
*ac
Qh
^J
^S
o
IC
IN
dAV =
II
'-V
>
on 3
o
|/3
Cttl
1S3I
dy= V
:
oo<
xz
cn uj
a.
->
- h^ s
R*z
OJJQ O
<
<< OuBS Hto OO
(d-XI)lS31
o
<
>
.'.7
u-
OS-UJ *0
V = :d
>lc
c
IN
a.
<> w O HC <
.J mJ
dS=d
II
ft.
<<
as
g3o
OHU
uz z
d soo
'ad
U
^ <o.p
d + y = :V
II
>
60
o
o
a=d
(d-a)isai
II
o <
W3 GO
II
os os
"J
T3 os uu os
uj
g
ôonzSs
+ d + g = :a
o Q
O +
v a) 1S31
>3
Xft.
So
-hQ
Q
Q
c
a
-hoo
& s
O a5 osfcQ
KXZ
Qo o
Do o
S5
xumulator and memory imstru CtKms tor thro a A168 OU Mil:ro<:orjaptiter System (Reproduc ed
Microcomputer System Design Data 1976-7)
I
CONO. CODE REG.
AOORESSING MODES
ACCUMULATOR AN ) MEMORY
EXTND
INDEX
DIRECT
IMMEO
OP
OP
9B
AB
OB
EB
fr on1 J46 801
INHER
(All rtfisttr labth
MNEMONIC
OP
Add
ADDA
AOOB
8B
CB
Add Acmltrs
ABA
Add with
ADCA
89
99
A9
B9
ADCB
C9
09
E9
F9
B +
ANDA
ANDB
84
94
A4
B4
M + C->A
M + C--B
A. M--A
C4
D4
E4
F4
B.M->B
BITA
85
95
A5
B5
A. M
BITB
C5
05
E5
F5
B.M
6F
7F
00 -*M
OPERATIONS
Carry
And
Bit Test
OP
BB
FB
CLRA
CLRB
Compare
CMPA
81
91
A1
B1
CMPB
CI
01
El
F1
Compare Acmltrs
CBA
Complement, Vs
COM
63
73
Negate
NEG
2's
Decimal Adjust,
OR
B +
M-B
B-A
conUnts)
00
-A
5F
00
-B
A-M
B-M
2
A-
43
M--M
A->A
53
tWB
00 -
M
A
00 -
00 - B
DAA
19
- B
BCD
7A
DECA
4A
OECB
5A
Characters
B-
1->B
98
A8
B8
AM-A
EORB
C8
08
E8
F8
BM-B
6C
7C
4C
A+1-A
INCB
5C
B+1--B
F6
BA
EA
FA
DA
Push Oata
B+M->B
AA
CA
E6
ORAB
PS HA
06
Or, Inclusive
A + M-*A
9A
B6
C6
36
A-*Msp, SP-1-SP
PSHB
37
B-"Msp. SP-1--SP
PULA
32
SP+1 -SP, Msp--A
33
SP + 1-SP,
M S p-B
PULB
ROL
69
79
49
ROLA
bI
M
AS LA
48
ASLB
58
ASRA
47
ASRB
57
LSRA
44
LSRB
54
76
68
ASL
67
ASR
78
77
Unc
M'
64
74
ii
"
I
"
"*
"
)-
"0
- n
bQ
b7
LSR
D 1
b7
B.
R
n-i
b7
ii
bQ
- n
C
R
STAA
97
A7
B7
A-M
STAB
D7
E7
F7
B-*M
A-M-A
SUBA
80
90
AO
BO
SUBB
CO
DO
EO
FO
B-M->B
10
TAB
16
TBA
17
Subract Acmltrs.
SBA
Subtr. with Carry
SBCA
82
92
A2
B2
SBCB
C2
02
E2
F2
Minus
"7
bI
Ml
56
In c
46
66
RORA
RORB
Test, Zero or
ROR
Transfer Acmltrs
59
ROLB
Subtract
M-A
M-B
A6
96
1-*M
INCA
8A
Store Acmltr.
LDAB
Shift Right, Logic.
ORAA
Shift Right, Arithmetic
88
Shift Left, Arithmetic
EORA
Rotate Right
BCD Format
-M
A-1 -A
M -
->
Converts Binary Add. of

into
6A
4F
86
Rotate Left
50
LDAA
Oata
70
M-"A
40
Load Acmltr
Pull
NEGB
INC
Increment
rtftr to
NEGA
DEC
Decrement
Exclusive
60
#
A
11
COMA
COMB
Complement,
OP
IB
CLR
Clear
TST
6D
70
A-B-A
A-M-C-A
B-M-C-B
A-B
B-A
M-00
TSTA
4D
A -00
TSTB
50
8-00
Figure 3.30 {continued overleaf)
INDEX REGISTER AND!JACK

POINTER OPERATIONS
MNEMONIC
Compare Index Reg
CPX
IMMED
OP
8C
DIRECT
OP
9C
~
4
INDEX
OP
AC
EXTND
OP
BC
INHER
OP
BOOLEAN/ARITHMETIC OPERATION
-(M/M
(X H /X L )
1)
DEX
09
X-1->X
Decrement Stack Pntr
DES
34
SP-1->SP
Increment Index Reg
INX
08
X +
Increment Stack Pntr
INS
31
SP+1-+SP
Load Index Reg
LDX
CE
DE
EE
FE
M-X H ,(M +
Load Stack Pntr
LDS
8E
9E
AE
BE
M-SP H
XH
Decrement Index Reg
Store Index Reg

Store Stack Pntr
Indx Reg
- Stack
Pntr
-Hndx Reg
Stack Pntr
STX
DF
EF
FF
STS
9F
AF
BF
35
TSX
30
RELATIVE
INDEX
-M, X L ^(M
EXTND
Branch Always
BRA
20
None
Branch
If
Carry Clear
BCC
24
C =
Branch
If
Carry Set
BCS
25
C=
Branch
If
Zero
BEQ
27
Z=
Zero
BGE
2C
Zero
BGT
2E
Higher
BHI
22
<
+ (NV)
+ Z=
>
>
Branch
If
Branch
If
Branch
If
Branch
If
Branch
If
Branch
If
Branch
If
Minus
Branch
If
Branch
If
Branch
Branch
OP
OP
BRANCH TEST
N*V =
+ (NV)
2F
BLS
23
<
BLT
2D
NV=
BMI
2B
Not Equal Zero
BNE
26
Overflow Clear
BVC
28
If
Overflow Set
BVS
29
If
Plus
BPL
2A
8D
Zero
Branch To Subroutine
BSR
JMP
GE
7E
Jump To Subroutine
JSR
AD
BO
No Operation
NOP
01
Return From Interrupt
RTI
3R
10
Return From Subroutine
RTS
39
12
9
INHER
CLC
OC
CLI
OE
Clear Overflow
CLV
OA
Set Carry
SEC
OD
SEI
OF
SEV
OB
A--CCR
TAP
CCR-*AcmltrA
TPA
Clear Carry
Clear Interrupt
Set Interrupt
Mask
Mask
Set Overflow
OPERATION
4
I
OP
Operation Code (Hexadecimal);
Number
of
MPU
0-l
o-*v
^c
-I
-*v
06
07
Number
of
Program Bytes;
Arithmetic Plus;
Half-carry
Cycles;
Interrupt
A^CCR
CCR-A
Carry from
memory
(S)-
I-
See special Operations
if
test
is
Test: Result =
10000000?
(Bit
Test: Result =
00000000?
(Bit C)
Test: Decimal value of
(Not cleared
true and cleared otherwise)
(BitV)
if
most
V)
Test:
Operand
10000000
(BitV)
Test:
Operand
01111111
(BitV)
Test: Set equal to result of
(Bit
(Bit
N)
(BitV)
(Bit
N)
BCD
Character greater than nine?
most
prior to execution?
prior to execution?
N C
significant
after shift has occurred
(MS) byte of
result =
complement overflow from subtraction
Test: Result less than zero? (Bit
15=
of
1?
LS bytes?
1)
Load Condition Code Register from Stack. (See Special Operations)
(All)
(Bit
Test: Sign bit of

Test: 2's
significant
previously set.)
I)
Set
when
interrupt occurs.
If
previously
set, a
Non-Maskable Interrupt
required to exit the wait state.
(ALL)
Set according to the contents of Accumulator A.
bit 7
Set
Always
Boolean Inclusive OR;
Boolean Exclusive OR;
Complement
CCR
Transfer Into;
LS
Least Significant
Bit =
MS
Most Significant
Zero;
Reset Always
location
pointed to be Stack Pointer;
M;
bit 3;
bit)
of
Overflow, 2's complement
AND;
Contents of
mask
Negative (sign
Zero (byte)
Arithmetic Minus;
Boolean
from
(Bit set
Byte = Zero;
CONDITION CODE REGISTER NOTES:
O^C
LEGEND:
Mjp
BOOLEAN
=
(^
v3J
i
3F
3E
SWI
OP
Advances Prog. Cntr. Only
WAI
MNEMONIC
See Special Operations
Software Interrupt
OPERATIONS
Test and set
if
t
t
Wait for Interrupt
CONDITIONS CODE REGISTER
=0
BLE
Jump
Acmltr
Lower Or Same
Zero
1)
INHER
it
OP
-MM
1)
MNEMONIC
OP
X- -SP
SP + - X
OPERATIONS
it
1)-X L
(M + 1)->SP L
SP H -*M, SP
L
TXS
JUMP AND BRANCH
1-X
true, cleared otherwise
Not Affected
Condition Code Register
Figure 3.30 (cont'd)
82
is
3.
WAIT/GO SYSTEMS
83
Problem 2 Read and Print n characters

Given a microprocessor, a printer and a paper tape reader design a system to
allow n characters on the tape to be printed under program control.
Use the microprocessor wait/go mode to implement your design, which

be verified using the INTEL 8080 and the
6800.
is
to
MOTOROLA
8080
SOLUTION
Step
To
Aim of the
design
read and print n characters.
logic.
The reader and
printer
are
action/status devices.f
The block diagram of our solution is shown in Figure 3.32. As the printer is an
is needed. The step-by-step operation of the system is flow-
acceptor no I/O port
charted in Figure 3.33.
With the exception of the I/O port

hardware
is
for the reader in Figure 3.34
INTEL
needed, since in the case the
8080 e
w. See
no other
example
in
section 3.4.
'
'
'
Reader
Printer
fin
i
ay
e
w
I
_^
menace
Figure 3.32.
f Action/status devices are explained in
Appendix
1.
a2-
84
The
octal
and hexadecimal
INTEL 8080 are derived by direct

and to the programming chart in
listings for the
Figure 3.27 (or to the instruction

Octal
Octal
003
000
016
OE
001
(n)
(n)
002
003
004
005
006
007
010
001
012
013
014
015
016
014
015
312
016
003
333
010
323
020
303
003
003
OC
OD
CA
OE
L2:
LI:
SOLUTION
Step
3.28).
MVIC
Comments
Load
with
INRC
Increment register C.
DCRC
Decrement
JZ
DB
IN
OS
OUT
n.
Sets condition
flags.
register C. J
03
>3
register
If
register
Read next
is
empty, jump to LI.
character.
Print character.
18
C3
03
03
76
JMP
L2
Jump
HUT
to L2.
Halt.
'
|
Step 2
Step 3
Mnemonics
a }
166
6800
Figure
Hex
listing listing
address
set in
Same
as in the
8080 solution
,1
The block diagram of our solution using the M6800 is shown in Figure 3.35.
As in the previous problem, in addition to the I/O port we require an AND
gate to generate the enable signal
and 2 of example
e,
see circuits
2 in that section.

By reference to the flow chart in Figure 3.36 and to the programming chart
in Figure 3.30 (or to the instruction set in Figure 3.31), we obtain the
hexadecimal
listing of
our program.
It is
shown on page
86.
Problem 3 Print a record

Given a paper tape reader, a printer and a microprocessor, design a system
that prints a record of n characters. The record label
sequence 4-5-6 is used as a label only.
is
4-5-6. Character
WAIT/ GO SYSTEMS
3.
Start
Initialize
85
count
<
Yes
Stop
Read
Print
Decrement count
Figure 3.33.
Use the wait/go mode to implement your design, which is to be verified using
INTEL 8080 and the MOTOROLA 6800.
the
8080
SOLUTION
Step
Aim
of the design
The aim
of the design
is
to print a record.
logic.
The reader and
shown
printer
are
action/status devices.!
The block diagram

operation
is
of our solution
is
With the exception of the I/O port

needed, since for the
INTEL
8080
in Figure 3.34
w. See
example
no other hardware
1
is
in section 3.4.
The octal and hexadecimal listings for the INTEL 8080 are derived by direct
and to the programming chart in

t Action/status devices are discussed in
set in
Appendix
Figure
1.
3.28).
86
Reader
INTEL
Printer
8080
w oio
^020
#010
#020
Figure 3.34.
L2:
Hex
Hex
address
listing
00
00
C6
01
02
03
04
05
06
07
08
09
QA
OB
0C
0>
0
OF
L\
10
27
0B
56
LDA
,n
01
f?
LDA
Load
register
If re S ister
B=
with
Read a
character.
NOP
STA
.4,4000
Print the character.
01
NOP
5A
IE
DEC B
JMP LI
Decrement
Jump
SWI
Stop.
B.
to L2.
n.
um P
,4,2000
40
00
00
02
3F
>
20
00
Bl
Comments
Mnemonics
to L1
3.
WAIT/ GO SYSTEMS
87
Address
decoder
VMA M200^
AND
R/W
M6800
Reader
Printer
"'2000
~"~ H'4000
#2000
#4000
Figure 3.35.
Start
Initialize
count
Read
No
Read
No
Read
No
Yes
Read
Print
Decrement count
Figure 3.36.
<
^rStop

Octal
Hex
listing
listina
Mnemonics
000
333
DB
IN
Read next character.
001
020
376
264
302
000
003
10
FE
CPI
Compare AC
BA
CI
JNZ
Octal
address
003
L\
002
003
004
005
006
007
010
LI:
Oil
012
013
014
015
016
017
020
021
022
023
024
025
026
027
030
LA:
031
032
033
034
035
036
037
Li:
00
03
333
DB
020
10
376
265
302
002
003
333
020
376
266
302
002
003
016
(n)
014
015
312
043
003
If
LI
FE
CPI
Compare AC with
B5
C2
JNZ
If
DB
IN
Read next
FE
CPI
Compare AC with
B6
C2
JNZ
Step 3
If
L2
OE
MVICl
()
oc
OD
INRC
CA
JZ
23
03
L3
IN
333
DB
10
040
303
C3
041
042
043
030
003
18
5,
jump
to LI.
character.
03
76
character not a
Load
register
as in the 8080 solution
jump
to
-LI.
with
n.
Increment register C. 1 Sets conDecrement register C.) dition flags.
If register
Read next
is
empty, jump to L3.
character.
Print character.
JMP
HLT
6,
OUT
LA
6.t
DCRC
"j
Same
5.f
02
03
tSee ASCII Table on p. 74.
Step 2
to LI.
10
18
character not a
LI
D3
Step
jump
4,
character.
02
03
323
SOLUTION
character not a
}
Read next
030
6800
with 4.f
IN
020
166
Comments
Jump
Halt.
to LA.
WAIT/GO SYSTEMS
3.
89
The block diagram of our solution using the M6800 is shown in Figure 3.35.
As in the previous problem, in addition to the I/O port we require an AND gate
to generate the enable signal
example 2
e,
see circuits
and 2 of
in that section.
By reference to the flow chart in Figure

listing of
LI:
12:
our program.
Hex
Hex
address
listing
00
00
B6
01
02
03
20
00
04
05
06
07
08
09
0A
0B
OC
0D
0
OF
10
11
12
34
26
F8
B6
LDA
/4,2000
NOP
CMP A
BNE
LDA
LI
.4,2000
NOP
CMP A
26
BNE
LDA
LI
,4,2000
C6
19
1A
27
HEQ
IB
\C
0B
IA
J56
BNEL2
LDA
LDA
B,n
,4,2000
4.
character not a
4,
jump
to LI.
jump
to L2.
jump
to L2.
character.
>
Compare A with
5.
character not a
5,
character.
Compare A with
1
If
Load
register
6.
character not a
If register
6,
B with
B=
0,
n.
jump
Read a
NOP
with
20
00
01
If
Read next
18
\E
IF
| Compare A
20
00
NOP
CMP A
character.
If
EC
Read next
01
81
35
17
15
Comments
Read next
16
14
programming chart in
we obtain the hexadecimal
to the
3.31),
Mnemonics
20
00
F4
B6
and
3.36
Figure
shown below.
01
81
36
26
13
L3:
01
81
It is
set in
character.
to L4.
90
Hex
Hex
address
listing
Comments
Mnemonics
L
20
21
22
23
24
LA:
25
26
27
28
Bl
40
00
STA
A, 4000^
}
01
NOP
5A
IE
DEC B
JMP
Decrement
L3
00
>
B.
^
>
Jump
to L3.
\A
3F
SWI
3.6
Stop.
REFERENCES
3.
'M6800 Microprocessor Applications Manual,' Motorola, 1975.

D. and Duncan, F. G. 'Microprocessor Interfaces,' Electronics
Letters, vol. 12, No. 23, November 11, 1976.
Zissos, D. 'Problems and Solutions in Logic Design', Oxford University
4.
INTEL
5.
Zissos, D., Bathory,
1.
2.
Zissos,
Press, 1976.
Mimi
8080 Microprocessor Systems User's Manual, September 1975.

J. C. 'Wait/go Microprocessor Systems,' Proceedings
1977,
November
1977.
In
chapter
this
we
outline
step-by-step
methods
for
the
design
and
implementation of test-and-skip microprocessor systems. The clock stretching
method for achieving I/O synchronization is discussed. The design philosophy

adopted is outlined in Chapter 2 (section 2.9) and the design steps we use are
described in section 2.10 of the same chapter.
4.1
The need
INTRODUCTION
an I/O
and 3. One method of
implementing I/O synchronization, the wait/go method, was described in the
previous chapter. In this chapter we shall describe the two alternative methods,
namely test-and-skip and clock stretching.
to synchronize the microprocessor with a peripheral during
operation has been explained in Chapters
mode we
In the test-and-skip
synchronize the microprocessor operation
with the response of a peripheral using a software loop. It works as follows.

After each I/O instruction the programmer inputs the status of the peripheral
and
the
the
tests
test.
whether it has
fully
He continues to do
responded or not.
If not, the
programmer repeats
so until the device becomes ready, at which point
program comes out of the loop and proceeds to execute the next
shown in Figure 4.1. The design and implementation of
instruction, as
microprocessor systems using
this
mode
of operation
is
described in the next
section.
In a limited
slowing
down
number
referred to as clock stretching

4.3.
I/O synchronization can be achieved by

method commonly
can be used. We explain this method in section
of cases where
the microprocessor clock frequency, a
92
Read
status of device
No
Activate peripheral
Other instructions
Figure
4.2
The block diagram
4.1.
of a test-and-skip system
is
shown
in
Figure
indicates the availability /non-availability of the peripheral; r
peripheral
is
ready, otherwise
0. Its
The programmer executes an I/O
step-by-step operation
4.2.
=
is
Signal r
when
the
as follows.
instruction which activates the peripheral,
change from logic 1 to logic 0. He next inputs the status

word, one bit of which is signal r. He then tests to check whether r equals 1 or
not. If r does not equal 1, indicating that the peripheral has not fully responded
causing signal
to
II
II
II
II
I:
ll
II
\tn
Other status
Peripheral
signals
.Command
signals
I/O
signals
Interface
Figure
4.2.
Status
signals
4.
yet,
he inputs the status word again and repeats the
test.
93
He continues to do so
which point the program is resumed as shown in Figure 4.1.

Note that the duration of the test-and-skip loop equals the response time of the
until r equals
1,
at
peripheral.
CLOCK STRETCHING
4.3
Let us denote
by/ max and/min the maximum and minimum clock frequencies in
Hz within which the
microprocessor can operate.
the operating frequency, that
Now
if
is
fmin <f<f max
the response time of the device

1
J
we can clearly synchronize
is t
We use variable/to denote
seconds, where
max
J min
the microprocessor with the device by changing
its
clock frequency to /, where
>t.
If
we assume
trailing
that the microprocessor interstate transitions occur on the

edge of clock signal
then we use (f) 2 as our clock in our clockl5
stretching circuit.
The implementation of such a circuit

l
+i
o-
\ *[
02
0-
0-
r-
fl
'
Figure
4.3.
is
straightforward and
94
should present no
of logic design.
detail in
difficulty to the reader
The method
who possesses
described in Chapter
Chapter 4 of 'Problems and Solutions
Oxford University
To
is
in
a working knowledge
of this
book and
method, we
shall
show how we can
the microprocessor clock frequency by two clock cycles. If
stretch
we denote by
the signal generated by the interface to request a 'two-cycle stretch',
I/O characteristics are shown in Figure 4.3. In Figure 4.4 we
the corresponding
internal-state diagram.
show the
we
diagram,
more
Press, 1976.
illustrate the simplicity of the
variable
in
Logic Design' by D. Zissos,
By
direct reference to the internal-state
obtain
JA
therefore
RA =
SB
RB =
01
S3
'S
=A
-B
'E,
-s
=A
-B
-s,
S2
=A -B,
therefore
K A = B's
therefore J B
therefore
=S O -01+ S l+ S 2+ S
=B
A-s
KB = A
</>l
Â-B-^^+A'B + A-B + A-Bî

= + 0!
02
(So
+ S 3)'02
= (A-B + A-B)'<j) 2
= 5-02
The corresponding
circuit
4.4
In this section
is
shown
in Figure 4.5.
we demonstrate our design steps by means of problems and

The reader's attention is drawn to the fact that,
fully-worked out solutions.
,.j[?l
*'x-+i
01=1
+2''+2
0;=o
,48
= 00
s2
Si
So
JL*
4=1
<t>'
11
01
Figure
4.4.
JL'
\=<f> l
+2*-*2
10
^1
A
j
Figure
although we use the

used apply to
the
first
all
*i-L
f=D
95
-Z)+>
4.5.
INTEL
8080 to implement our designs, the procedures

it should be noted that
the design are executed without reference to the
types of microprocessors. Specifically
three steps in
microprocessor.
Problem
RAM to printer
Design an interface to allow a programmer to transfer data from consecutive

or
through the m.p.u. onto an acceptor.
The acceptor in our case is a digital printer, whose terminal characteristics
are described in Figure 4.6. The microprocessor is the INTEL 8080.
locations in
RAM
ROM
SOLUTION
Step
Aim of the
design
The aim is to design and implement an interface between a microprocessor

and a relatively simple peripheral using the test-and-skip mode of
microprocessor operation.
The relevant I/O signals of the INTEL 8080 are shown in Figure
terminal characteristics of the printer are shown in Figure 4.6.
4.7.
The
The block diagram
of our solution
is
shown
in
Figure
4.8. Its
operation
is

4. Hardware design
The hardware consists of an address decoder, a NAND gate, an inverter and
an AND gate as shown in Figure 4.10. The decoder is used to decode the I/O
address of the printer and the tristate. They can both be allocated the same
address because one is an input device and the other is an output device. If we
Step
S3
> c
TJ
6 cs
-^
S
i -a
43
l>
.s
.>
0
Q.
eB -23
<D
55 .

II
o
S ^
C'H 3
l_
O
S .*
*
7^
a*
g.3
o
TO
-1
35
60
T3
S3
$<

=s
.5 .g <
S
-*
60
3 43 43
2
-
m O +'
l-i
43
^-,
as
S3
ca
>.
60 T3
-i
43
Ch
J3
3s '
too
U 3
3
43 43 a
cu
^ 432
<*>43
5
as
is
.R 60
S3


V3
en
(U
Ifi
T3
3
"etf
r/l
43
CM
o
U S3 o
O o
a
k.
s 'I
o .>; a
?
c
k.
>
<a
K o
? cd
II
rrl
_S3
.
E^ 43
43
S3
Pk
4.
Next instruction
I/O instruction
A/1
97
Ml
A/3
A/1
Address fetch
I/O execute
Instruction fetch
rur_TL
INP
DBIN
OUT
WR
Figure
4.7.
JTTTTT
tm
Printer
Other status
signals
I/O
Status of
printer
signals
Interface
Figure
4.8.
98
denote the address by Am, then
w = Am-OUT-WR;
implemented
this signal is
by the
N AND gate. We open the tristate when I/O IN instruction with address
Am
being executed
is
i.e.
= IN-DBIN-Am.
This signal
is
generated by the
AND gate. Since the printer status signal x can only be monitored when w =
we make w equal
OUT. This reduces
to
monitored to the duration of the OUTpuhe. In

the eight tristate outputs are
zero
all
when
1,
w cannot be
the arrangement we have used,
the time
when
the printer
signal
is
unready.
For the sake of
clarity
we
shall first design the software required to
synchronize the printer operation with the microprocessor. The flow chart
shown in Figure 4.1. The mnemonics are shown below.
OUT
#
IN
LI:
Transfer character from
AC
is
to printer.
( Input the status of
I the printer.
ANA A
Set flags.
JZ
LI
\ ready go
If printer
not
to LI.
By direct reference to our flow chart in Figure 4.9 and either to the
programming chart in Figure 3.27 or to the instruction set in Figure 3.28, we
obtain the octal and hexadecimal listings of our program. These are shown
below (Am = A010).
Octal
Mckl ress
1
II
003
Octal
Comments
Mnemonics
Ilex
/.
000
041
21
001
002
003
(L)
(L)
(H)
(H)
016
OE
004
005
(n)
(n)
014
OC
LXl
Load immediate
the initial
{
MVIC
Load block
{
INRC
LI:
006
007
010
011
012
013
019
015
016
017
015
312
027
003
333
010
247
312
012
003
JZ
17
03
DB
LI
08
Al
ANA A
CA
OA
JZ
03
\I
IN
LI
If register
register C.
is
empty,
jump
to location LI.
Read
status
of printer.
If
Set flags.
\i
printer not ready,
jump
to set
flags.
Decrement
HL.
length into
Increment register
DCRC
OD
CA
address
register C.
condition
L3:
RAM
into double register
to location L2.
4.
Octal
address
020
021
022
023
LI:
024
025
026
027
030
031
032
Octal
Hex
Mnemonics
Comments
176
323
IE
MOVA,m
OUT
Move next character

memory to AC.
INRL
JMP
Increment
03
08
010
054
303
006
003
076
015
323
010
06
03
C
1
L3
MVI A
OUT
D3
RAM
location
L3
Move immediate
code
Print.
HLT
is
into
The contents of
Halt.
J>
initial
RAM address
Initialize
counter
Yes
Read
status of printer
No
Move
from
next character
RAM into AC
Print
Decrement counter
Figure
4.9.
<
Stop
the
AC
and the carriage
returned.
Start
Load
AC
for carriage return, 01
are printed
76
address.
to
08
Jump
82)
166
fron
Transfer character to printer.
2C
C3
{
033
99
100
*~OUT
WR
Figure 4.10.
Problem 2
Reader
to
RAM
Design an interface to allow a programmer to transfer data from a source

through the m.p.u. into consecutive locations in RAM.
The data source in our case is a paper tape reader described in Figure 4.6,
and the microprocessor
is
the
INTEL
8080.
SOLUTION
Step
Aim
of the design
The main aim is to design an interface between a microprocessor and a

peripheral whose input signals have time restrictions.
The
I/O signals of the INTEL 8080 are shown in Figure 4.7. The
diagram and terminal characteristics are shown in Figure 4.6.
relevant
reader's block

of our solution is shown in Figure 4.1 1. Its operation is
4.12. The eight outputs of the status tristate are
Figure
flow-charted in
the reader is not ready.
when
zero
all
arranged to be
The block diagram
4.
101
e2
Xr=
ji
i,
=r
_=
J
Reader
Hn
It'
/
k-
Other status
m-
/-
> Status of reader
signals
I/O
signals
Figure
Start
Load
4.
1 1
initial
RAM address
Initialize
counter
C
Yes
Read
_N.
status of reader
^ReadCT
readv.
Read into
Move AC
AC
into
RAM
Decrement counter
Figure 4.12.
^C
Stop
102
Because the
minimum
duration of an I/O pulse
directly the reader. This time constraint
the
I/O pulse to
set
They
in Figure 4.13.
it
cannot drive
by using
in practice
can be removed when changes to

I
Therefore we can reset the flip-flop with the
shown
0.48 /(sees
a flip-flop. Reference to the tape reader's terminal
characteristics indicates that the drive signal

0.
is
can be overcome
The enable
signals of the
transition in signal
to
two
ex
= INP'DBIN-A q and
e2
= INP'DBIN'A p
/,
as
tristates are
are implemented by the two
AND
gates in Figure 4.13.
By direct reference to our programming flow chart in Figure 4.14 and either
programming chart in Figure 3.27 or to the instruction set in Figure
3.28, we obtain the octal and hexadecimal listings of our program. These are
shown below. (A p = A 020 and A q = A ()M)
to the
).
Octal
Address
Octal
Comments
Mnemonics
Hex.
003 000
001
002
003
004
005
041
21
(L)
{L)
(H)
(H)
016
OE
(n)
(n)
014
OC
LXIH
Load
RAM
initial
address into
ii
MVIC
INRC
HL register
pair.
Load block
length
{ into register C.
Increment register
to set
condition flags.
L3:
006
007
010
011
L2:
LI
012
013
014
015
016
017
020
021
022
023
024
025
026
027
015
312
027
003
333
020
247
312
012
003
333
030
167
054
303
006
003
166
DCRC
OD
CA
JZ
17
03
DB
LI
Decrement
IN
Read
status
{ of reader.
10
Al
ANA A
Set flags.
CA
OA
JZ
If
03
DB
L2
reader not ready,
< jump
L
IN
to location L2.
Read next
character.
Move AC
contents to
18
MOV MA
INX H
77
2C
C3
06
03
76
register C.
is empty,
r
< jump to location LI.
L
If register
JMP
{
L3
HLT
Increment
(
i
Jump
I
Halt.
RAM
memory
address.
to location L3.
4.
103
-"(!
Address
decoder
-Ap
Reader
IF
Ap Aq
'"fflMfl
INTEL
8080
RAM
-~~INP
--
DBIN
-*~OUT
WR
Figure 4.13.
Problem 3 Read and print n- characters

Design an interface between the paper tape reader used in problem 2 and the
problem 1 to allow n characters to be printed n is a variable
denned by the programmer.
printer used in
Use
the
INTEL
8080 to
verify
your design.
SOLUTION
Step
Aim
of the design
is to design an interface between a microprocessor and two
The general aim

devices.
The relevant I/O signals of the INTEL 8080 are shown in Figure 4.7.
The terminal characteristics of the printer and reader are shown in Figure
4.6.
The block diagram
of our solution is shown in Figure 4.15. The method we

adopt consists of reading a character, printing it, decrementing a counter
and waiting for both the reader and printer to respond fully at which time the
shall
104
Start
J>
HL =
:
initial
RAM address
~T~
C=C+1
C: =
C-
<
Yes
Stop
J>
Input status of reader

(device 030)
Yes
Zero
No
Read next character
HL:
=HL+1
Figure 4.14.
process
is
repeated.
When the character count becomes zero, indicating that n
characters have been read and printed,
we
halt the operation, as
shown
in
our
move
the
flow chart in Figure 4.16.
Reference to the reader's terminal characteristics reveals that to
paper tape one character position we need to ground terminal k for
at least
1 n
and must remove the ground before signal changes to 1 As the duration of
an I/O pulse is approximately 0.5 /xsecs it cannot be used directly. The most
sec
4.
i,
II
li
II
II
105
Reader
Printer
H7l
Other status
AM-
signals
I/O
signals
Interface
Figure 4.15.
Start
Initialize
counter
Yes
Read
-^
status of
reader and printer
No
Read
Print
Decrement counter
Figure 4.16.
Stop
106
straightforward
method is to use the I/O pulse to set a flip-flop, and use the
to
This transition occurs 2 msecs after k is

grounded. This makes the duration of signal k about 2 msecs. If we allocate 003
transition in signal
as
to reset
it.
an I/O address to our reader, the I/O pulse INP'DBIN-A 003 can be used
this
purpose. This sets the JK flip-flop during
used also to enable the reader
To
activate the printer
with address 004
is
its 1
to
we ground
its
is
is
= INP'DBIN-A 002
terminal w when an I/O instruction
w = OUT'WR v4004. This signal is
tristate; that is e 1
executed, that
for
transition. This signal

.
implemented by the NAND gate and the inverter shown in Figure 4.17. Status
signals m and x are fed into the second tristate. The output of tristate 2, when
enabled is '000 000 1 1' or '003 8 unless either or both of the devices (reader and
',
printer) are unready. This gives the
programmer the opportunity to enter a

become ready.
the status port I/O address #005.
software wait loop until both the devices
In our solution
we
shall allocate

octal and hexadecimal listings for the INTEL 8080 derived by reference
programming flow chart in Figure 4.18 and either to the instruction set
Figure 3.27 or to the programming chart in Figure 3.28, are
The
to the
in
Octal
address
003 000
001
002
Octal
Comments
Mnemonics
Hex
01
016
01
(n)
(n)
014
OC
MVI
Move
1
INRC
next byte into register C.

of characters.
= number
Increment register
condition
L3:
L2:
LI:
003
004
005
006
007
010
011
012
013
014
015
016
017
020
021
022
023
024
025
015
312
025
003
333
005
376
003
302
007
003
333
003
323
004
303
003
003
166
DCRC
OD
CA
LI
<
t
15
03
DB
in
FE
CPI
03
07
03
DB
If register
register C.
is
empty, jump to
location LI.
Input status.
JNZ
(12
(IN
{ Compare AC with
f
{K
If
next byte.
devices unready,
jump
to location L2.
Read a
character.
03
D3
OUT
04
C3
03
03
76
to set
05
C2
Decrement
JZ
flags.
JMP
| L3
HLT
i Jump to
X location L3.
Halt.
4.
at
T3
107
QNV
^
QMV

-^SOOy
00y
<-8
eooy
108

(
Start
C: = w
1
C=C+1
Figure 4.18.
Interrupt
Systems
this chapter we outline step-by-step methods for the design and

implementation of interrupt systems. The design philosophy adopted and the
design steps are as outlined in Chapter 2, sections 2.9 and 2.10, respectively.
In
5.1
In this
mode
INTRODUCTION
of operation an external event signals the microprocessor that
it
program and to execute instead a

different set of instructions, the interrupt routine, as shown in Figure 5.1. When
the interrupt request is serviced, the interrupted program is resumed. For
example a fire detector may signal the microprocessor that it has detected a
fire. In such a case the microprocessor would suspend execution of its current
program and proceed to execute a service routine that would typically trip
alarm bells, warn personnel in the vicinity, turn on sprinklers, alert the fire
brigade and so on. After the microprocessor has responded to the fire alarm, it
wishes
it
to suspend execution of its current
returns to the interrupted program.
For
reference purposes
last instruction in the
the
first
we denote by A m
interrupted
program
memory where the

and by ^4 S the location of
Note that at the point of
the location in
resides,
instruction in the interrupt routine.
program counter, PC, are A m+l This is

incremented during machine cycle Ml, as can be seen in Figure
interruption the contents of the
because PC
is
2.4.
It
follows that to switch from the
main program
to the interrupt routine,
simply replace the contents of the program counter, PC, by
As
Similarly,
we
we
program at the end of the interrupt routine by

loading the program counter, PC, with A m+V This is the minimum information
required by the microprocessor to resume the interrupted program; we shall
return to the interrupted
110
Current program
Interrupted
program
Interrupt
1
Interrupt
routine
Return
1
Resumed
program
Figure
refer to
it
5.1.
as the program's re-entry point.
In practice, the status of the
condition flags and of the working registers must also be preserved during an
interrupt routine. Working registers are m.p.u. registers that are used by both
program and the
the interrupted
interrupt routine.
program counter, the status of the condition
flags,
The contents of the

and the status of the
[1]
working registers we shall refer to collectively as the program's re-entry point.

The primary reasons for interrupting a program in practice are to initiate,
service, or terminate some process which is capable of being carried out
simultaneously (in parallel) with the execution of a program.
Although the design of interrupt systems is carried out in well-defined steps,

implementation requires relatively more complicated hardware and
software than any other microprocessor mode.
their
5.2
INTERRUPT SYSTEMS
The block diagram of our interrupt system is shown in Figure

an interrupt circuity shared by
all
5.2. It consists
the devices using the interrupt
of
mode, a
has been designed as a general system

to accommodate any type of microprocessor and any type of peripheral. Its
step-by-step operation is flow-charted in Figure 5.3 and summarized below.
peripheral and
its
interrupt interface.
It
When a peripheral requires servicing, or it is ready to transfer data in or out

of the microprocessor,
its
interface,
which monitors
its
signals, raises a flag.
Flags are defined in the next section. The interrupt circuit, which monitors all
the flags, then generates the interrupt signal, signal / in Figure 5.2, and some
meaningful information, which we denote by variable i. Signal / informs the

microprocessor that one or more peripherals wish to communicate with it. If
f
We
shall refer to
it
as interrupt logic.
5.
INTERRUPT SYSTEMS
II
I,
I,
I:
111
II
Hn
INTA
Peripheral
Interrupt logic
<<
I.
II
I.
I.
Command
Other
I/O
flags
signals
/n
Status
signals
signals
Interface
Figure
5.2.
interrupts are enabled, the microprocessor completes
and responds
1
It
in the following
current instruction
generates a signal to indicate that the program has been interrupted.
refer to this signal as Interrupt
shown
2.
its
manner.
in
Figure
Acknowledge, and denote
it
We
by INTA, as
5.2.
Further interrupts are automatically disabled. This ensures that the

microprocessor will not be interrupted again until the programmer is
ready to accept another interrupt.
8.
The re-entry point is stored on stack.

The source of interruption is identified by inputting
Working registers are stored on stack.
The request is serviced.
The interrupt flag is cleared.
The working registers are restored.
9.
Interrupts are enabled.
3.
4.
5.
6.
7.
10.
The interrupted program
is
i.
resumed (PC loaded with re-entry
point).
Although the above sequence of events is typical, variations in the

implementation of the individual steps exist depending on which microprocessor is being used. For example, in the Motorola 6800 all the m.p.u.
registers
and condition
INTEL
8080 only the program counter
flags are automatically stored

is
on
stack,
whereas in the
stored automatically on stack.
112
I
Further interrupts
disabled
'
Re-entry point stored
Identify source of
interruption
*
Save working registers

1
Service request
"
Clear flag
1
Restore working
registers
'
Enable interrupts
|
'RETURN'
instruction
Re-entry point
restored
Figure
Clearly, in cases like this
it is left
5.3.
to the user to store all additional information
which is needed to resume the interrupted program.

Because the interrupt cycles of present day microprocessors are different,
the configuration of the interrupt circuit of each microprocessor will be
unique. As
circuits
we
shall see in section 5.4 of this chapter, the design of interrupt
presents
no
special
difficulty,
if
the
interrupt
cycle
of
the
understood. However, before we discuss in detail

the design and implementation of interrupt circuits, it is essential for the reader
microprocessor in question
is
to have a clear understanding of flags
and
flag sorters,
which we discuss next.
5.
5.3
INTERRUPT SYSTEMS
113
FLAGS AND FLAG SORTERS
Flags
A flag
defined as a signal generated and used by a device to inform
some
The block diagram of a flag
circuit with set, clear, enable and disable facilities is shown in Figure 5.4. The
function of each of the four input signals is as follows. A signal on terminal e
enables the circuit, whereas a signal on terminal d disables the circuit. Clearly
is
other device that
it
wishes to communicate with
it.
these two signals are not applied simultaneously in practice.
When the circuit is
on terminal k sets the flag. The flag is cleared (turned off) by a

on terminal c. If enable and disable facilities are not needed, terminals e
enabled, a signal
signal
and d may be omitted.
Flag circuit
Figure
5.4.
Flag Circuits
In
common with all logic circuits, the terminal characteristics of a flag circuit
can be implemented by
different but equivalent circuits.
we
possible implementations, to which
Below we show two

and flag
shall refer to as flag circuit 1
circuit 2.
Flag Circuit
state
shown
diagram describing both
in Figure 5.5.
By
its
internal
and external operations, 121
direct reference to the state diagram,
turn-on set of
A = B -k
turn-off set of
A = B -k +B -d
turn-on
B = A-e+A-k
set of
turn-off set of
B=A
-d
+A
= d + Ac
i
-c
Invert
>(B
+A
+ k)(B + d)
Invert
+d-(A
we obtain
+ c)
is
14
Therefore,
A =B-k + A(B + k)(B + d)

B = A-e+A-k+B(A + c)d
f = S2
The equivalent
NAND
50
is
= A-B-k
shown
51
in Figure 5.6
52
Flag
Flag
disabled
/=o
E=
AB =
circuit
-k
53
Flag
off
Flag
on
/=o
E=\
00
c+ d
/=0
=1
E=l
01
11
Figure
5.5.
z^y^y^
AND
io-oh
Figure
5.6.
cleared
10
5.
INTERRUPT SYSTEMS
115
Flag Circuit 2
If
enable and disable
facilities
are not needed, and signal k
can be implemented using a

Chapter 1, section 10).
circuit
flip-flop, as
shown
is
a pulse, the flag
in Figure 5.7 (see also
JL*
Figure
5.7.
Identification of Flags
As we mentioned
flags.
earlier, the interrupt signal is generated by ORing all the

This signal simply informs the microprocessor that one or more devices
in the
system wish to communicate with
processor
is
it.
interrupted, the interrupt routine
Therefore,
must
when
the micro-
identify the source of
interruption. There exist
two basic methods for identifying flags: the polling

method and the vectored method. We shall describe each of these methods
below.
The Polling Method

method when the microprocessor
In this
receives
an interrupt
signal,
it
sequences through the devices looking for the individual device(s) that need
servicing. When it finds such a device, it stops sequencing and calls the
corresponding service routine. If the interrupt signal is still on at the end of the
service routine, the polling of the devices continues, otherwises the
program
is
Several implementations of the polling
method we
main
resumed.
method
exist in practice. In the
connected to an input port from which

they are read into an internal register of the microprocessor through the data
bus as shown in Figure 5.8(a). The contents of the internal register are then
examined one bit at a time according to the flow chart in Figure 5.8(b).
shall describe, the flags are
The Vectored Method

method the presence of flags in a system is automatically detected and
the flags are identified by means of a hardware circuit, the flag sorter, the
f
In this
t Flag sorters are also referred to as priority encoders,
and are commercially available as
i.e.
chips.
116
Current program
Preset counter to x:
=m
Read
status of flags
</
No
,
ll
I,
|,
I:
/,
I.
Hii
OR
Jump
to service routine
"
<,
Restore working registers
J m-' m +
(a)
Increment counter (x:=x+l)
No
Figure
shown in Figure 5.9(a). Interrupt signal I is

by
ORing the input flags. The identity of the flag is
all systems,
block diagram of which

generated, as in
5.8.
is
generated in a specified binary code.
We shall use the true binary (8-4-2- 1
code,
we
The design and implementation of flag sorters is straightforward and should
present no difficulty to the reader who possesses a working knowledge of logic
design, outlined in Chapter 1 We shall demonstrate the steps by designing and
unless
specify otherwise.
implementing two-flag, eight-flag and 64-flag sorters.

assume that the higher the flag number, the higher its
We
shall arbitrarily
priority.
5.
INTERRUPT SYSTEMS
117
d
Current program
'/
Input
Vectoring
address
fill
PC =
:
Gump
i
i
1
to
SR)
Return
Flags
Flag sorter
Restore working
registers
(b)
(a)
Figure
A Two-Flag
Sorter
The block diagram
of a two-flag sorter
(input/output) relationship
5.10(b).
By
5.9.
is
shown
shown
is
direct reference to this table,
in
Figure 5.10(a).
form of a truth table
in the
we obtain
Its
I/O
in Figure
the following equations
/=/o+/i
Their circuit implementation
An
is
shown
in Figure 5.10(c).
Eight-Flag Sorter.
The block diagram of an eight-flag sorter is shown in Figure 5.11(a). Its I/O
relationship is shown in the form of a truth table in Figure 5.1 1(b). By direct
reference to this table,
we obtain
the following equations.
/
/o-
/o
Two-flag
A
-e-
sorter
A-
OR
vi(2)
(a)
(b)
Figure 5.10.
(c)
118
= /o +/l +f2 +/3 +/4 +/5 +/6 +//

= fi +/6 /5 + Je J4/3 +JJJih
B =/7 +J7 /6 +J7J6/5 J4/3 +JiJJJMi
= fl+h+JJJz+JJj2
C=f
As eight-input
+J7 /6 + J-Je/s +7JJJ*
priority encoders are available commercially, the
above
equations will not be implemented.
OUTPUTS
INPUTS
/o f\ fi
/o
/1
/2
h
h
Eight-flag
*
h*
^4(2)
sorter
S(2
2=:
C(2 2 )
f* fs
fi
00000000
xxxxxxxl
xxxxxxlO
xxxxxlOO
xxxxlOOO
x
(a)
10
C B A_
#--e--e-
1111
1110
1101
1100
1011
1010
1001
1000
(b)
Figure 5.11.
64-Flag Sorter
The block diagram of a
64-flag sorter
is
shown
arranged into eight groups of eight flags, each
in Figure 5.12.
The
flags are
group being allocated a
flag
interrupt signals from the eight flag sorters are connected to a
sorter.
The
group
selector, itself
an
eight-flag sorter. It operates as follows.
a group flag that is on, generates the system

and a three-bit address DEF which identifies the selected
group. Signals DJE, and F, in addition to being connected to the address bus,
drive a binary-to-decimal decoder. Each of the eight outputs of the decoder
drives in turn the three tristates which connect the address lines of the
corresponding flag sorter to the address bus, as shown in Figure 5.12.
The group
selector selects
interrupt signal, /,
Note that our 64-flag sorter arrangement can be used directly to

accommodate less than 64 flags by simply grounding the unused flag
terminals.
5.
INTERRUPT SYSTEMS
119
method we used to derive a 64-flag sorter using eightcan be used to produce a system for handling up to 4012 flags
simply by using the 64-flag sorter in Figure 5.12 as the module.
Clearly the modular
flag sorters,
Group
Address bus
/o:
8-flag sorter
<
fi~
h:
*l
8-flag sorter
hi
g
f\(>~.
8-flag sorter
hi"*3
/243
8-flag sorter
fn
hi:
8-flag sorter
f39
Ao:
5
"*5
8-flag sorter
<
/47
As
6
8-flag sorter
<
fs5
h(>
8-flag sorter
<
fa
e e l e 2 e 3 e4 e S e 6 e 7
Binary to decimal
decoder
._^lFlag
jC
^ J address
D >
_
^ 1IGroup
__
Group
flags
'
Group
selector
Figure 5.12.
address
120
5.4
In this section
explained
we
INTEL 8080 INTERRUPT SYSTEM
shall design the interrupt
earlier, in
order to design
interrupt cycle, which, as

of
it is
The
we shall
its
system for the
interrupt circuit we
see, is
rather unique.
INTEL 8080. As we
must understand
its
A detailed explanation
given below.
Interrupt Cycle of the
Reference to
its
INTEL 8080
[3]
m.p.u. signal chart in Figure 2.8 shows that a logic
14 interrupts the program,
if
on pin
the interrupt terminal has not been disabled.
Program interruption is indicated by a logic 1 on pin 16. There are no time

constraints on the interrupt signal it can occur at any time. The reason for this
;
is
that synchronization with the internal operation of the microprocessor
achieved by setting an internal latch with clock pulse
</>
during the
is
last state of
the instruction cycle in which the interrupt request occurs.
As we already mentioned, the method used by the INTEL 8080 chip is

rather unique. It is probably best understood by first examining the step-bystep execution of the restart instruction, the format of which is 11 ddd 111. The
three letters ddd represent an octal number from to 7. As in the case of an I/O
instruction, the restart instruction is executed in three machine cycles.
Let us assume that the restart instruction has been loaded somehow into the
instruction register//? in Figure 5.13. During the following two machine cycles
High address
~X
Location pointed by
00 000 000
Low
f^^^
00 000 000
W//////A
00 001 000
address
PC
\<-:<tt-y.v\ 00 010 000
Old
PC
y/////////< oo
PC
00 000 000
00 ddd 000
on
ooo
/////////A 00 100 000

Stack
IR
'//////////, 00 101 000
y////////A 00 110 000

Internal
circuitry
Figure 5.13.
y/////////f 00 111 000
INTERRUPT SYSTEMS
5.
the contents of the
program counter
PC
are pushed
121
on
stack, eight bits at a
time. In parallel to the stacking operation, the contents of the instruction

register (11
ddd 111) drive some internal circuitry
in the m.p.u. chip,
which
responds by generating sequentially two eight-bit words shown below
00 000 000, and
00 ddd 000.
As each set of eight bits in the program counter is pushed on stack, the two
words generated internally 00 000 000 and 00 ddd 000 are moved into
PC, 00 000 0000 in the portion that holds the high address and 00 ddd 000 in the
portion that holds the low address. The implication of this is that the next
instruction to be executed will be fetched from one of the eight locations listed
eight-bit
below.
when ddd = 000
00 000 000
(000 8 )
00 000 000
(000 8 )
00 000 000
(000 8 )
00 001 000
(010 8 )
when ddd = 001
00 000 000
(000 8 j
00 010 000
(020 8 )
when ddd = 010
00 000 000
(000 8 )
00 011 000
(030 8 )
when ddd = 011
00 000 000
(000 8 )
00 100 000
(040 8 )
when ddd = 100
00 000 000
(000 8 )
00 101 000
(050 8 )
when ddd =101
00 000 000
(000 g
00 110 000
(060 8 )
when ddd = 110
00 000 000
(000 s
00 111 000
(070 8 )
when ddd =111
As we saw
in the previous section, the three variables
instruction, are generated
by a
ddd
in the restart
flag sorter.
we
shall see how the restart instruction can be used to interrupt the
8080 for emergency situations when interrupts are disabled. This
feature, which is analogous to the non-maskable interrupts in the Motorola
6800 chip, is essential in process control applications, in medical and other
Later
INTEL
similar high-risk environments.
Let us
now
return to the interrupt cycle of the
INTEL 8080. This resembles
very closely a normal fetch instruction shown in Figure 2.2 and
exception that
(2)
(1)
An INTA
The program counter
is
(interrupt acknowledge) status signal
not incremented, and
(3)
The
2.4,
is
with the
generated,
interrupt terminal
is
disabled.
If during the INTA -DBIN interval we disconnect the memory from the data
bus and 'jam' onto it a restart instruction, as shown in Figure 5.14, the program
will vector to one of the eight locations shown in Figure 5.13 depending on the
output of the flag
sorter, ddd.
For example, if the output of the flag sorter is 010
122
INTA.DBIN
INTEL
INT
i:
i,
ii
I,
Flag sorter
1
II
Memory
J
Interrupt flags
Figure 5.14.
the
program
will
branch to location 00 010 000 (020 8 )
in
memory
with high
address 00 000 000 (000 8 ).

In existing systems, typically but not necessarily, high address 00 000 000
(000 8 ) specifies a
ROM.
Since service routines written by users must reside in
RAMS (you cannot write in ROMS), the locations in ROM specified by 00 ddd
000 contain JUMP instructions to specific locations in RAM, as shown in
Figure 5.15. Unless
specify otherwise,
is
ROM
000,
000o
RAM
RAM to which
assume that the
303
003 8
303
RAM
(JUMP)
First instruction of s.r.m
003
010 8
shall
that the locations in
program jumps to are 000 8
that the result
we
00 000 01 1 (003 8 ) and

to 070 8 From the user point of view, this means
of an interrupt signal is to cause the program to vector to one of
address in our case

the
we
(JUMP)
070.
303
"
First instruction of s.r.n
003
(JUMP)
t
First instruction of s.r.t
003
Figure 5.15.
5.
INTERRUPT SYSTEMS
123
RAM
003 g
ddd = 000
000 g
ddd - 001
yyyyyyyy^^y^.
ddd = 010
010 8
'yyyyyyyyyyyyyyyy^ 0208
ddd = Oil
y//////////////^: 0308
Output of 1
ddd = 100
flag sorter!
y/^/^XMZ
040 8
^//////////////^
050 8
ddd = 101
ddd = 110
ddd=
yyyyyyyyyyyy^^^
111
yyyyyyyyyyyyyy^^.
m,
Figure 5.16.
eight locations in
RAM, depending on the values of the ddd signals, as shown in
Any of the eight locations can be used to store the first instruction
Figure 5.16.
of a routine designed to service an interrupting device. If a service routine
contains
more than eight instructions, the programmer can use a

move to a different location in memory.
'jump'
instruction to
--^d
INTEL
8080
INT
INTA
m
QTmrru
AND
^/^prL^Î
ibet
o-
Flag sorter
Peripheral
njjTTT
Other
flags
/n
INP
Interface
Figure 5.17.
Command
OVi
Status
signals
signals
124
The program counter is restored to its pre-interrupt value by executing a

Working registers are restored by executing the appropriate
return instruction.
'pop' instructions.
The block diagram
of a microprocessor interrupt system using the
8080 can now be drawn as
INTEL
Figure 5.17.
EMERGENCY INTERRUPTS FOR THE
5.5
One
in
of the essential features in any system
INTEL 8080
when operating
in medical,
and other high-risk environments, is its ability to respond with the

least possible delay to emergency situations. In the case of the INTEL 8080, as
we have seen earlier on, when it enters an interrupt cycle, its interrupt terminal
is
automatically disabled. To be re-enabled an enable-interrupt {EI)
instruction must be executed. Until such an instruction is implemented the
microprocessor will not respond to external interrupts that is emergency
industrial
signals are ignored during this period. This time interval can be dangerously
extended
if,
either
due to some oversight on the part of the programmer or due

he fails to enable the interrupts at the beginning of
to carelessness or ignorance,
a service routine to allow for such emergencies.
(EMERGENCY). Ml. DBIN/ \

INTEL
8080
,-U
w_,.
Emergency
Memory
address
Figure 5.18.
can be eliminated in practical situations by 'jamming' onto the

data bus a restart instruction when an emergency arises with a specified value
for ddd, as shown in Figure 5.18. This will cause the program to vector almost
instantly to an emergency service routine, irrespective of whether the interrupt
Such
risks
terminal
is
disabled or not.
5.
5.6
As we
MOTOROLA
we do
understanding of
so, as
its
all
M6800 we can
microprocessors,
MOTOROLA
Interrupt Cycle of the
Reference to
with
interrupt cycle. This
its
125
6800 INTERRUPT SYSTEMS
shall see later, in the case of the
systems. Before
The
INTERRUPT SYSTEMS
is
design two interrupt
we must have a
6800
[4]
m.p.u. chart in Figure 2.9 shows that the
interrupted by a logic
clear
described next.
M6800 can
be
on pin 14, if interrupts are not disabled. As in the case

of the INTEL 8080, there are no time constraints on the interrupt signal it can
occur at any time. The reason for this is that synchronization with the
'0'
instruction in progress
(f)
during the
is
achieved by setting an internal latch with clock pulse
last state of the instruction cycle in
which the interrupt cycle
occurs.
Its interrupt
sequence
summarized below.
is
The current
2.
instruction is completed,
Further interrupts are disabled,
3.
The
1.
m.p.u. status
pushed automatically on stack
is
in the following order
PC L
PC H
IRl
IR H
ACCA
ACCB
CC
4.
The program counter is next loaded with the contents of memory locations
FFFS (PC H ) and FFF9 (PC L These contents, as we have already explained,
).
specify the address of the
The
reader's attention
is
first
drawn
instruction of the interrupt routine.

to the fact that at this point the source of
interruption has not been identified.
To resume
the interrupted
user executes a return
from
program
at the
end of the interrupt routine the

whose hexadecimal
interrupt {RTI) instruction,
code is 2>B. Execution of this instruction restores the pre-interrupt m.p.u. status
by 'popping' from stack the m.p.u. registers in the reverse order.
Because in the case of the M6800 the source of interruption can be identified
method or the vectored method, described in section

we have the choice of designing two interrupt systems, each using a
different method of flag identification, as shown next.
using either the polling

5.3.3,
126
Interrupt
System
In this system
we
interruption. Its block
operation
is
method to identify the source of

shown in Figure 5.19. Its step-by-step
use the polling
diagram
is
flowcharted in Figure 5.8(b).
VMA
ii
ii
ii
,i
M6800
IRQ
NOR
fofi
fi
Figure 5.19.
Interrupt
System 2
In system 2
we
operation
is
method to identify the source of

shown in Figure 5.20. Its step-by-step
use the vectored
interruption. Its block
diagram
is
flowcharted in Figure 5.21.
--^d
5.
INTERRUPT SYSTEMS
Start
127
Read
Convert
to starting
address of
SR(A J
11
Jump
to
SR( A s )
''
Stop
Figure 5.21.
5.7
EMERGENCY INTERRUPTS FOR THE MOTOROLA 6800
Emergency interrupts are handled by the non-maskable interrupt input on pin

39 (see Figure
2.9).
5.8
In this section

although
we
use the
INTEL
8080 and the Motorola 6800 to implement our
designs, our procedures apply to
should be noted that the
first
all
types of microprocessors. Specifically,
it
three steps in the design are executed without
reference to the microprocessor.
Problem
An
event-counter
Pulses representing events arrive randomly on line q in Figure 5.22. Design

an interrupt system that allows a print-out of the event-count to be produced
each time a manual switch m is activated. Activation of the switch, which can be
assumed to be infrequent, resets the count.
Implement you design using
(i)
the
INTEL
(ii)
the
MOTOROLA
8080,
and
6800.
I/O addresses available to the designer are 003 8 and 004 8

M6800.
,
8080, and 2000! 6 8004! 6 and 8006 16 for the

,
for the
INTEL
128
Required system
Print-out
Figure 5.22.
8080
SOLUTION
Step
Aim
of the design
The aim of the design is to obtain an event-count on

interrupt mode, as shown in Figure 5.23.
request, using the
The block diagram of the

in
interrupt system using the
INTEL
8080
is
shown
Figure 5.17 and the microprocessor I/O signals in Figure 4.7.

The terminal characteristics of the printer are shown in Figure 5.24.
The block diagram
shown in Figure 5.25. Its

Each time a pulse arrives
the current program and execute a service routine
of our general solution
operation, flowcharted in Figure 5.26,
on
line q,
we
shall interrupt
is
is
as follows.
Count
Print
Figure 5.23.
00
<D
> c
T3
3
T3
J3

ed
-a
o O
E
C
3 o
O
00
ft
c
.5?
<
ft
-Ai
as
rt-22
55 .
c3
S
O 3
tso e
-S
+"'
43
->
o
"S
S
Wh
O
o
i-i
8 a
fe0
*3
'S
>-'
3
J3X1
<
is
8.
,2 00
as
+-'
O
c
43
C O 
R O
cd
CI
i.
ft
as
>
SS
T3 XJ
D
U J3
<
00
o
v c
c
II
as
a>
t-i
.a
&0
3
a
-.5
"
"J
i-*
 (50
C
L?
"8
jg 43
as
S3 ->
*J
a
o
a
o
<L>
ft
'32
60X
o^
T3
<43 .
**
35
.3 =
43
C
o
o
R 8
e g
S>
as
X XI
C
>
S n
D
cd
S3
as
-^
U
<
"i
vs
_, -^
Xo
<
'
4>
J3
ai
at
<
t-
! *3
o
JS
60 ^3
d
_
as
-o.o
C >
o >
o
c a
=s
o o
<
22
J2
<
43
^ 2
^
<L>
t5
ra
.22
130
-^-^d
o/
li
Printer
Hn
INTA
Interrupt logic
TT
1
Other
I,
II
flags
/n"
I/O
signals
Interface
Figure 5.25.
that increments a counter by
1.
Similarly,
when
switch
m is activated, we shall
interrupt the current program and execute another service routine which
produces a print-out of the event-count and resets the counter to 0.
Reference to Figure 5.27, the block diagram of our

indicates that the signals to be generated
1.
2.
by our
INTEL
8080 solution,
interface are
The two flags, f and/1; and

The print pulse, w.
If no enable and disable facilities are required for our flag signals, they can be
implemented using flag circuit 2, described in section 5.2 of this chapter. If we
use the q pulses to set flip-flop/ in Figure 5.28, and the activation/release of
switch m to set flip-flop /,, then the equations of our interface signals are
Cn
= OUT-WR-A 003
cx
rl
w and
m,
w = OUT-WRA,
INTERRUPT SYSTEMS
5.
131
'/
Further interrupts
disabled
1
Re-entry point saved
/f
^\y
Yes
No
_^
'

1
Print event-count
Increment event-count
Reset event-count to
zero
1
Clear/,
Clear /
'
Restore working
Restore working
registers
registers
Enable interrupts
Enable interrupts
'Return'
'Return'
instruction
instruction
1
Re-entry point restored
Figure 5.26.
If we further
make the assumption
system, a two-flag sorter will suffice.
such a circuit consists of an
that/ and/j are the only two flags in the
As we saw
in section 5.3 of this chapter,
OR gate (Figure 5.10). Under these conditions the
hardware component of our system
is
shown
in
Figure 5.28.
The programming
flow charts for the
INTEL
8080 are shown
in Figure
132
INTEL
8080
INT
Flag sorter
IIIIIIH
Other
flags
"fi
fo
<<
INP
DBIN
OUT
WR
Interface
D^J
]
Figure 5.27.
= 110/,
1111
INTA
AND
DBIN
INT
,-u
I
-
Address
decoder
llll.
Printer
-/,
OR
^003
^004
/o
W
r
(Not used)
INTEL
~L
l\J
~"
UZL
~
\fo
NAND
NAND
- OUT
- WR
Figure 5.28.
5.
INTERRUPT SYSTEMS
133
5.29.f By direct reference to them and to the instruction set in Figure 3.28 (or
to the chart in Figure 3.36), we obtain the octal and hexadecimal listings shown
below.
Octal
Octal
Hex
address
listing
listing
Mnemonics
Service Routine
Comments
(Count)
//
003
010
365
Oil
012
013
004
04
323
003
D3
014
015
016
361
373
311
PUSH PSW
365
170
323
031
032
033
034
035
036
037
040
6800
flags.
clear
flag/
Restore
.
F\
POP PSW
FB
EI
AC and flags
Enable interrupts.
C9
RET
Return.
(Print)
F5
PUSH PSW
Save
78
MOV Afi
Move B
D3
OUT
I/O
AC
and
flags.
into A.
to load printer
and
3E
MVI A
Load
0D
015
for carriage return.
L>3
OUT
041
004
076
015
323
004
006
060
042
043
044
361
373
311
F\
POP PSW
FB
El
Restore AC and flags.

Enable interrupts.
C9
RET
Return.
04
04
06
Same
5.3.
AC
with ASCII code
Activate printer.
MVIB
Clear register
30
as for 8080 solution
was made to Figure
clear /j.
SOLUTION
f Reference
I/O cycle to
03
Service Routine
030
Save AC and
Increment B.
INRB
OUT
(our
counter).
134
Count routine
Print routine
Start
Start
'
Save
AC
Save
AC and
condition flags
Print
Increment count
Clear
Reset count
Restore condition
Clear /j
flags
"
"
AC
and
Restore
condition flags
E.I.
."
'Return'
E.I.
''
'Return'
Figure 5.29.

In the case of the
M6800
the designer has the option to use a polling or a
we shall use the polling system

The block diagram of our solution in
vectored interrupt system. In this solution

described in section 5.3 of this chapter.
this case is
shown
in Figure 5.30. Reference to
it
indicates that the signals to be
generated by our interface are

1.
2.
3.
Two
flag signals,
f and/
to initiate the count
The enable signal e for the I/O port, and

The w signal to activate the printer.
and
print routines,
5.
INTERRUPT SYSTEMS
135
Address
decoder
VMA
U AND
R/Wt~-
i,
Address
decoder
Printer
0-
w--
NOR
IRQ
--x
M6800
Other
flags
/o"
h
H
VMA
/?/>P
ii
ii
Interface
"2
Figure 5.30.
As before, we shall assume that/ and/j are the only two flags in the system.
This allows us to generate the interrupt signal and the address of the
interrupting device using a single
AND gate, as explained in section 5.2 of this
chapter. If we further assume that
our two
flags,
Figure 5.31.
no enable/disable facilities are required for

they can be generated by the two JKFFs, as shown in
A pulse on line q sets the count flip-flop, turning/ on; similarly a

m sets the print flip-flop, turning/^ on. If hexadecimal addresses
pulse on line
2000 and 8006 are used to clear the two
flags,
the equations of the clear signals
are
r
= VMA -R/W-A 2000
-</>
2,
and
r^VMA-R/W-Anot-fc
NAND gates
and 2
in
Figure 5.31 implement these two signals.
136
^d
^8004
VMA Lr
R/W
AND
'0'-
I,
l:
II
Address
decoder
Printer
+2
oM
IRQ
NOR
^ ^
Ji
^
(Not used)
M6800
l
0 *
i j
0 K
r,
Cl
fl
NAND
NAND
--
VMA
0,
Figure
In this system
printer
is
we can
activated
and
these two operations
Note the degree
5.31,
activate the printer
the flag
is
when we
clear flag/t Because the
may
occur at
w=
on a 1 to
the same time, making
reset (turned off)
signal transition,
(See Figure 5.31).
of similarity between the
INTEL
8080 and the
M6800
systems.
The programming flow chart of our solution is shown in Figure 5.32.f By

it and to the M6800 programming chart in Figure 3.30 (or to
its instruction set in Figure 3.31), we obtain the hexadecimal listing of our
direct reference to
service routine.
f Reference
was made
to Figure 5.3.
Current program
E
Further interrupts
disabled
M.p.u. status saved
Input
No
Yes
Print event-count
Increment event-count
Reset event-count
Clear
Clear /j
'Return' from
'Return from
interrupt'
interrupt'
instruction
instruction
M.p.u. status restored
Figure 5.32.
00
Hex
Hex
address
listing
50
B6
51
80
04
87
25
07
52
53
54
55
56
57
58
59
LI:
5A
5B
5C
5D
5E
LDAA
r Input address
from flag
v sorter.
<
RARA
Rotate right A
to count routine,
BCS LI
Jump
if
LDAB
Move
00
counter
FF
STAB
^ into B
C Print
\ and clear
RTI
INC
1 flag/,.
Return.
r
)
increment
\ counter
F6
Fl
80
06
3B
1C
00
5F
60
FF
61
20
00
62
63
Comments
Mnemonics
Fl
2>B
STAB
carry flag
Clear
I Aag/
RTI
Return.
is set.
138
RAM to printer interface
Problem 2
Design and implement an interface between an eight-bit microprocessor
and a digital printer.

Use the interrupt mode
implement your design, which is to be verified

(ii) the MOTOROLA 6800. I/O addresses
and
using
the
8080,
available are 004 8 005 8 and 006 8 for the INTEL 8080, and 2000! 6 4000! 6 and
8004 16 for the M6800.
to
INTEL
(i)
8080
SOLUTION
Step
Aim
of the design
the design
The aim of
data,
which
is
the interrupt
is
to enable the
programmer
stored in consecutive locations in
mode, as shown
in
to transfer a block of
RAM, into,an acceptor, using
Figure 5.33.
The block diagram

in Figure 5.17
of the interrupt system using the
and the microprocessor I/O
The terminal
INTEL
8080
is
shown
signals in Figure 4.7.
characteristics of the printer are
shown
in Figure 5.24.
The block diagram of our solution

flow-charted in Figure 5.35,
next character to be printed

the accumulator.
is
is
is
shown
in Figure 5.34. Its operation,
as follows. At each
program interruption the
transferred from the next location in
RAM into
From the accumulator it is output onto the data bus and the
been printed and the printer

by generating flag/7
When the last character of the block has been printed, the programmer
disables the interrupt flag and no more characters are printed. The next block
printer
is
activated. After the character has
becomes ready, the next interruption
transfer
is
initiated
is
initiated
by the programmer re-enabling the
flag.
The block diagram of our solution using the INTEL 8080 is shown in Figure
5.36. The two signals to be generated by the interface hardware are
1
2.
The
The
print
command,
interrupt flag/7
w,
and
5.
INTERRUPT SYSTEMS
139
Print
Figure 5.33.
/in
INTA
Interrupt circuit
MMMJ
Other
I/O
flags
signals
Interface
Figure 5.34.
140
Current program
word count
Initialize
31
rteX^
Yes
End of block
\ôurit=0^>
Disable
NoJ
Decrement
byte address
1
Restore working
registers
Enable interrupts
Return instruction
Figure 5.35.
transfer
/7
INTERRUPT SYSTEMS
5.
The most straightforward method
of generating signal
141
w is to decode an I/O
instruction with one of the available I/O addresses, say 004 8 In such a case
.
If
the duration of signal
stretch
it
= 0UT-WR>A 004
is less
than
microsecond, we would have to
using standard methods, or add to the printer a front-end logic, using
methods outlined in Appendix 1.

Flag/7 should be turned on when the printer becomes ready, that
the
status signal changes to
when
terminal
It
is
when
its
can be cleared when we activate the printer, that
w is grounded.
If we
use a clocked flip-flop to generate/,, as
is
we
explained in section 5.2 of this chapter, then the equations of its clock and reset
signals
The
become
flag flip-flop is
flip-flops, unless
we
shown
c1
rx
=w
x,
and
in Figure 5.37.
The reader is reminded that our

on the trailing edge of a clock
specify otherwise, switch
pulse and reset with a ground, that
is
with a logic
0.
-d
INTA
AND
DBIN
iTTrnrf
ll
T _L_I
Address
decoder
INT
Printer
Flag sorter
INTEL
,1
I,
;>
I,
8080
fl
Other flags
INP
ii
DBIN I
OUT
WR
Interface
Figure 5.36.
142
In addition, the interface must provide the programmer with the facility to
use software for enabling and disabling the interrupt flag. Such a facility can be
supplied by a flip-flop, which can be turned on and off under program control.
If we allocate octal addresses 005 and 006 for this purpose, the relevant
equations are
c
= OUT'WR-A 005 and
= OUT-WR-A 006
Their circuit implementation
is
shown
Figure 5.37.
in
INTA
DBIN
jmw-r
Address
decoder
Printer
Flag sorter
INT
nTTTTTT
Other
INTEL
T ^
flags
AND
-wv
fi
*r
AND
NAND
NAND
'004
Figure 5.37.
OUT
WR
5.
INTERRUPT SYSTEMS
143
The programming flow chart of our solution is shown in Figure 5.38.f By

it and to the programming chart in Figure 3.27 (or to the
instruction set in Figure 3.28), we obtain the octal and hexadecimal listings of
our service routine shown below.
direct reference to
Octal
address
003
060
1
2
3
4
5
6
7
070
1
2
3
4
5
6
7
100
1
2
3
LI
6
7
10
Octal
Hex
listing
listing
365
345
032
056
003
276
323
004
053
042
056
003
041
055
003
065
302
105
003
323
006
341
361
373
311
5
5
PUSH PSW
\A
IE
LHLD
PUSHH
IE
MOV A,M
D3
OUT
04
2D
DCX H
22
SHLD
Output character and

)
I
locations 003-056/7. This
2D
}
DCRM
C2
JNZ
45
03
| LI
>3
06
Same
POPH
POP PSW
C9
RET
as for the
Step 3
to Figure 5.3.
Decrement
HL
and copy into
is the
address in memory where the
next byte resides.
Load HL with the address of the
location in memory where the
byte count is stored.
Decrement byte count.
OUT
1
1
8
003-056/7).
Move next byte into AC.
clear flag.
IX I
03
35
HL
Move into
the address of the
next byte (contents of locations
f
J
03
21
Step
was made
SOLUTION
t Reference
Save working registers.
}
J\
03
6800
Step 2
Comments
Mnemonics
EI
8080 solution.
If
the byte count
jump
is
not zero,
to location LI.
Disable/, if byte
count is zero.
Restore working registers.
Enable further interrupts

and return.
144
Start
Save A, Hags, H,
Move
next byte into
Print byte and

clear flag
Decrement byte count
Yes
End of block
Decrement
byte address
Disable
Restore A,
flags,
transfer.
7
H, L
Enable interrupts
Return
Figure 5.38.
Reference to our system block diagram in Figure 5.39 shows that the signals
to be generated
by our interface are
command,
1.
Print
2.
Interrupt flag/7
If
we
w,
and
allocate hexadecimal address 8004 to the printer, then
w = ^8004 VMA-R/W'(j) 2
If
the duration of signal
is
see
less
NAND
than
gate in Figure 5.40
microsecond, we would have to
5.
INTERRUPT SYSTEMS
145
- -
Address
decoder
VMA
U AND
R/wr*
,,
Address
decoder
,1
M6800
Printer
^MJ}
IRQ
Flag sorter
Other
flags
-A
VMA
"
R/W
"
"
Interface
Figure 5.39.
'stretch'
it
using standard methods, or add a front-end logic to the printer,
using the methods outlined in Appendix
1.
Flag/7 should be turned on when the printer becomes 'ready', that

its status signal x changes to 1. It can be cleared when we activate the
that
is
when terminal w is grounded.
If
is
when
printer,
we use a clocked flip-flop to generate/7
as we explained in section 5.2 of this chapter, then the equations of its clock
reset signals
The
and
become
flip-flop is
flops, unless
and
we
shown
c1
x,
rx
w.
in Figure 5.38.
and
The reader is reminded that our flipon the trailing edge of a clock pulse
specify otherwise, switch
reset with a
ground, that
is
a logic
0.
must provide the programmer with the facility to

use software for enabling and disabling the flag. The most straightforward
method is to introduce an enable flip-flop, which can be turned on and off
under program control. If we allocate hexadecimal addresses 2000 and 4000
for this purpose, then the equations of flip-flop's clock and reset signals are
In addition, the interface
= A 2000 VMA-R/W-(I) 2 and
7^
= A 4000 VMA-R/W-fc
SYSTEM DESIGN AND MICROPROCESSORS
146
The output of the flag

shown in Figure 5.40.
R/w
ANDed
flip-flop is
with
to generate signal
/7
as
Address
,JJtHtIL
decoders
Printer
+2
IRQ
-o- /
Flag sorter
n
II
ii
I,
II
ii
ii
fM
Other
x t
oo
-r
flags
AND
M6800
1 /
o k
0 K
NAND
AND
fl
NAND
2
'8004
'2000
VMA
-^ R/W
-+2
Figure 5.40.

is shown in Figure 5.41. By
programming chart in Figure 3.30 (or to the
Figure 3.31), we obtain the hexadecimal listing of our service
The programming
direct reference to
instruction set in
routine.
it
flow chart of our solution
and
to the
5.
INTERRUPT SYSTEMS
147
Start
J>
Move
next character
into
ACC A
Print character
and
clear flag
Decrement byte count
Yes
End of block
transfer.
Disable flag
Decrement byte
address
RTI
Figure 5.41.
Hex
Ilex
address
listing
00
5F
60
B6
61
mH
62
63
64
65
66
67
68
69
6/4
6B
6C
6>
6
LI:
IDA A
STAA
80
04
1A
00
5F
27
04
1A
70
00
72
3B
location 005F.
Move
into
Print character
and
DECn
}
BEQ
LI
|
DEC m L ^
I
RTI
STAA
next character
00
62
71
\
\
"l
Bl
Comments
Store block length in
3B
Bl
40
6F
Mnemonics
AC.
clear flag/7
Decrement the
block length.
If
block length
jump
RTI
is
zero.
to LI.
Decrement pointer
to next character.
Return.
Disable
flag/7
.
Return.
148
5.9
1.
Zissos, D.
and Duncan F. G.
REFERENCES
'Digital Interface Design',
Oxford University
Press, 1973.
2.
Zissos, D. 'Problems
and Solutions
in
Logic Design', Oxford University
Press, 1976.
3.
INTEL
4.
M6800 Microprocessor
8080 Microprocessor Systems User's Manual, September, 1975.

Applications Manual, Motorola, 1975.
D.M.A. Systems
In this chapter
we
be concerned with the design and implementation of

is with systems that allow data to be
transferred directly between a peripheral and the memory in a microprocessor
system. The design philosophy and design steps are outlined in Chapter 2,
direct
memory
sections 2.9
shall
access systems, that
and 2.10
respectively.
6.1
INTRODUCTION
In the methods we have discussed so far for transferring data between a

microprocessor and a peripheral (wait/go, test-and-go, and interrupts), the
information moves through the m.p.u., as shown in Figure 6.1(a). These
methods require several instructions to be executed for the transfer of each byte.
For example, if we use the interrupt mode, we must
1.
Disable further interrupts,
2.
Store the re-entry point
3.
Identify source of interruption
4.
5.
Service the request

Clear the flag
6.
Restore the re-entry point
7.
Enable interrupts, and

Return to the current program, as explained
8.
For
if
not automatically disabled
in chapter 5.
large blocks of data this can involve excessive amounts of m.p.u. time.
if the rate of the incoming information is greater than
the rate at
Furthermore,
which the microprocessor can write into memory, some of the information will
clearly be lost.
In a system, however, in which a direct link
is
established between
memory
150
and peripheral, as shown diagrammatically in Figure 6.1(b), the abovementioned problems would be eliminated, since we should be able to transfer a
byte of information between memory and a peripheral in one memory cycle.
Contrary to common belief, the design and implementation of such systems is
straightforward. As we shall see later on in the chapter, the interface hardware
is uncomplicated and the software required to drive it minimal, approximately
a dozen instructions for each block transfer.
The duration of a direct memory access is normally expressed in memory

A memory cycle is a time cycle in which the appropriate signals to read or
write into memory are generated. Because a memory cycle is effectively 'stolen'
from the m.p.u. operation each time a d jn.a. cycle is executed, a d.m.a. cycle is
cycles.
often referred to as cycle steal.

All microprocessors have a facility that allows the designer to establish a
between the microprocessor memory and a peripheral, as shown in
direct link
Figures 6.1(b). This
facility is called
a direct memory access, or d.m.a. in
abbreviated form.
Memory
Peripheral
m.p.u.
(a)
d.m.a. path
Memory
Peripheral
m.p.u.
(b)
Figure
6.2
6.1.
DMA. SYSTEMS
d.m.a. system is shown in Figure 6.2. It has been

designed as a general system to accommodate any type of peripheral and all
types of microprocessors. Its step-by-step operation is flowcharted in Figure
6.3
1.
and
is
summarized below.
The programmer
initializes
the d.m.a. interface.
He
does so by using I/O
instructions to output to the interface the initial memory address and the
block length. The d.m.a. interface is, therefore, allocated an I/O address by
means of which the programmer can
access
it.
6.
D.M.A.
SYSTEMS
151
1. Initial
Memory
memory
c> address
2.
Block length
3.
'Go*
command
Address
1
'
Interface
Figure
2.
6.2.
He next outputs a third item to the interface, a 'go' command. This signal is
used to initiate the block transfer, which is then completed autonomously,
that is without programmer intervention.
3.
When the block transfer is completed, the interface generates a flag signal, e,
4.
to inform the programmer that the block transfer has been completed.
The programmer acknowledges flag e by executing an I/O instruction,
which clears it. Signals c, t and f are defined in the next section.
6.3
DMA.
INTERFACES
The design of d.m.a. systems, as already stated, is straightforward and should

present no difficulty to the reader who possesses a working knowledge of logic
design, outlined in Chapter
1.
A d.m.a. interface is best designed as two separate units, to which we shall

refer as interface I
and
interface
see Figure
6.4.
The
basic function of
by the programmer and

to generate the start and stop signals for interface 2, whose basic function is to
control the transfer of data between the memory and the peripheral.
interface
The
to accept the initial information output
step-by-step operation of each interface
Interface
Its
1 is
is
described below.
block diagram
is
shown
in Figure 6.5. It consists of
two counters
152
Start
Load
)
memory
initial
address
Load block length
Issue 'go'
command
Block transfer begins
Block transfer ends
Disable interface
Raise end-oftransmission flag e

,
Stop
Figure
1. Initial
Memory
Control
signals r><ci
nn
mp
cfc>
J
6.3.
memory
address
2.
Block length
3.
'Go'
command
-i
Peripheral
signals
Interface
.Command
(Start)
'
signals
'i
(Stop)
Interface 2
Figure
6.4.
Status
signals
6.
D.M.A.
SYSTEMS
153
and a flip-flop. The two counters are used to

accept the initial memory address and the block length. They are loaded as
follows. The programmer transfers into the accumulator the initial memory
address and executes an I/O instruction with address A p This generates an I/O
pulse on the load terminal of the two counters, which transfers the
accumulator contents (the initial memory address) into counter 1. At the same
time, because the two counters are connected in cascade, the contents of
counter 1 are pushed into counter 2. The programmer then transfers into the
accumulator the block length and executes the same I/O instruction. This
causes the memory address in counter 1 to be pushed into counter 2, and the
connected in cascade,
five
gates
value of the block length (held in the accumulator) to be loaded into counter
1.
Next the programmer executes another I/O instruction with a different

address, denoted in Figure 6.5 by A q This generates a pulse on the clock
terminal of our flip-flop, shown as a JKFF. Because J = 1 the flip-flop, which
has been initially reset by the system reset signal, sets turning signal E on. This
signal, as we shall see later, causes interface 2 to start the block transfer, by
initiating a d.m.a. cycle each time the peripheral becomes ready.
.
Load pulses
(Step-down pulse)
Hn
K
AND
E
I/O pulse
AND
Figure
6.5.
154
While a d.m.a. cycle is being executed, signal t equals 1. We use this signal to
decrement our two counters in Figure 6.5.
At the end of the block transfer counter 1 contains all zeroes, which is
indicated by a logic 1 generated at the output of the NOR gate. This signal,
denoted by variable e in Figure 6.5, is used by interface 2 to stop the block
transfer.
At the same time
it is
end-of-block transfer signal,
e,
ANDed with flip-flop signal E to
generate the
which, as we have already explained, informs the
that the block transfer has been completed. The programmer

acknowledges flag e by executing an I/O instruction with address A r This,
when decoded by AND gate 3 in Figure 6.5, generates a pulse on the flip-flop's
programmer
reset terminal
r,
In Figure 6.6
turning off signal
e.
we show the block diagram
of interface
for a microprocessor
with an eight-line data bus and a sixteen line address bus. For the sake of
clarity we do not show the peripheral in this diagram. Signals c, t and t' are
explained next.
j-HSI
Load pulse
"
''
"
'i
ii
'
a
I
AND
Hn
It,
NOR
AND
I/O pulse
AND,
Interface 2
Figure
6.6.
6.
D.M.A.
SYSTEMS
155
Interface 2
The function of
we have already stated, is to control the

memory and the peripheral. To
possible microprocessor-independent, we shall
interface 2, as
transfer of data between the microprocessor
make our
designs as far as
assume the existence of a microprocessor with
cycle-steal characteristicsf as
,
described below.
Signal
c.
to
signal
transition
on
this
terminal
tristates
the
microprocessor for one d.m.a. cycle. This, as we saw in section 6.1

is a time cycle during which the appropriate signals to read or write
into
Signal
Signal
memory
are generated.
1 when the microprocessor is tristated, otherwise

used to define the duration of a d.m.a. cycle.
generated during the presence of signal t, and is used as
This signal equals
t.
t'.
0. It is
Signal
t'
is
the read/write pulse for
D.M.A.
D.M.A.
memory.
cycle requested
cycle granted
Decrement counters
and 2
Stop block transfer
*<
Raise e
St P
"^
Activate peripheral
Figure
The implementation of microprocessor
6.7.
cycle-steal characteristics
is
discussed in section 6.5.
156
6.4
In this section
we show
THE TWO-WIRE INTERFACE

that the implementation of interface 2 in Figure 6.4
between a microprocessor with cycle-steal characteristics (explained in the

previous section) and an action/status device! consists of two wires. To prove
this result we shall use the design steps outlined in Chapter 1, section 9. For
the sake of simplicity, initially we shall ignore the presence of signals E, e
in
Figure
6.8.
This does not invalidate our
and
t'
results.
Interface 1
Status
signals
Microprocessor
Peripheral
Interface 2
_^_
I!.
signals
Figure
Step
Command
6.8.
I/O characteristics
signals are shown in Figure 6.9. The desired

output is as described in the previous section,
and
relationship between input
by the peripheral when it becomes ready to
requested
that is a d.m.a. cycle is
the d.m.a. cycle is granted, the transfer of
When
memory.
read or write a byte in
which the microprocessor resumes its
of
end
the
one byte takes place, at
The I/O (input/output)
activity
and the peripheral
is
triggered into action. See Figure 6.10.
Figure
6.9.
diagram of a suitable circuit is shown in Figure 6.11. Its

microprocessor is
operation is as follows. State S is maintained while the
cycle, indicated
d.m.a.
the
of
end
the
At
cycle.
d.m.a.
tristated, that is during a
toS 1 transition
The
S
S
state
to
moves
circuit
the
to
0,
v
by signal t changing
The
internal state
are explained in
t Action/status devices
Appendix
1.
SYSTEMS
D.M.A.
6.
157
End of d.m.a
cycle
/i7i
Hn
goes
Peripheral
activated
tristated
Peripheral linked
Peripheral
memory
to
ready
Figure 6.10.
causes action signal a to change from
action.
0,
our
to
1,
triggering the peripheral into
When the peripheral responds, indicated by its ready signal becoming

circuit
peripheral
is
moves
responded, signal
S 2 The
to state
responding, that
while
is
circuit
remains in state S 2 while the
equals zero.
When the device has fully
which causes the circuit to move to state S v In

S l5 signal c changes from to 1 requesting a cycle
changes to
1,
moving from state S 2 to state

from the microprocessor. When the cycle steal is granted, indicated by
= 1, our circuit moves to state S The cycle repeats itself.
steal
End of cycle-steal
So
Device responded
----~,
--"
r
Si
s2
Device on
Cycle-steal
c=l
a
Cycle -steal granted
c=
Device started to
respond
=
=
Figure 6.11.
In this step, as
diagram into a
we have
already explained,
we
translate the internal state
and apply Caldwell's reduction steps. The table

derived directly from our state diagram in Figure 6.11 is shown in Figure
6.12(a). Applying the reduction steps (section 7, Chapter 1), allows its three
rows to merge into one, shown in Figure 6.12 (b).
state table
By
direct reference to the reduced state table,
Introducing
E and
e,
we obtain
t-r
+ t'r + (t'r) =
(1)
-r
(2)
-r
+ (t
-r)
we obtain
c
E'e-r
t
(3)
(4)
158
X'
51
50
c,a
51
10
11
01
00
1,0
1,0
52
50
1,0
1,1
0,1
SI
52
0,1
0,1
(a)
|5012|
|5012
|5012
10
11
01
00
5012
5012
c,a
1,0
1,1
0,1
<,<=o,o
(b)
Figure 6.12.
between a cycle-steal microprocessor and

6.13.
action/ status peripheral consists of two wires, as shown in Figure
data starts
of
transfer
Reference to equations 6.3 and 6.4 indicates that the
That
is,
the
d.m.a.
interface
with a d.m.a. cycle and ends with the activation of the peripheral.
6.5
CYCLE-STEAL LOGIC
The cycle-steal characteristics which we defined
in the previous section are
not
therefore, left to the user to design a
available in current microprocessors. It is,

front-end logic to implement our cycle-steal
in
characteristics
a given
6. 14(a).
microprocessor. The block diagram of such a circuit is shown in Figure
to be
likely
difficulty
main
The
The design procedure is straightforward.
pin
m.p.u.
of
the
interpretation
correct
experienced by the reader is the
functions from published data.

As we mentioned earlier, unless
we
specify otherwise, we shall
assume that a
Figure 6.14(b). We
d.m.a. cycle extends over three clock pulses, as shown in
logic for the
cycle-steal
the
designing
by
procedure
shall demonstrate the
INTEL
8080.
Cycle-steal Logic for the
The
INTEL 8080
relevant m.p.u. signals are
shown
in Figure 6.14(a).
buses.
line (pin 13) disconnects the address and data
labelled
HLDA
(Hold Acknowledge), and appears on
A logic
on the hold
The response
signal
is
pin 21. This signal goes
6.
Initial
D.M.A.
SYSTEMS
159
memory
address
2.
Block length
3.
Go command
^p-~-
I/O signals
Interface 1
P*
(See Fig. 6.5)

Peripheral
11
E
(Go)
(Stop)
Figure 6.13.
flit
m.p.u. signals
Cyclesteal
logic
(a)
Clock
uu
:ju
(b)
Figure 6.14.
INV
AND
160
high within a specified delay of the leading edge of <f> 1 in machine state T3. The
data and address buses are floated within a brief delay of the rising edge of the
next
INTEL
clock pulse. For a detailed timing diagram the reader
is
referred to the
8080 Microcomputer Systems User's Manual, September 1975, page
2-12.
In Figure 6.15(b)
tristates the
we show
INTEL
8080
reference to this diagram,
SA
=S =
SB
approximately three clock pulses. | By direct
we obtain
A-B,
RA =
the internal state diagram of a logic circuit that
for
S 3 c-HLDA
-
A- B- c- ELDA,
= S 'HLDA = A-B-HLDA,
RB =
S2
A-B,
So-c
+ ^ + S;, =
=
S1
JA
therefore
K = B- c-HLDA
therefore
JB
therefore
HOLD =
=B
therefore
= A-HLDA
KB = A
A-B-c + A'B + AB
A-c + B
+S 2 + S 3-HLDA =A-B + A>B+A'B-HLDA

= B+A-B'HLDA
= B+A-HLDA
t>
The corresponding
(primitive) circuit
6.6
In this section
S2
is
= A-B
shown
in Figure 6.16.

although we use the

apply to
Specifically,
INTEL
8080 to implement our designs, our procedures
types of microprocessors with or without cycle-steal logic.
all
it
should be noted that the
first
three steps in the design are
executed without reference to the microprocessor.
D.M.A. Problem
Reader
to
RAM interface
Design a d.m.a. interface between an eight-channel paper tape reader and

of a microprocessor system.
the
RAM
I/O addresses available are

t In this implementation signal c
A 00A A 005 and A 006

,
must not be removed before
HLDA
is
generated.
D.M.A.
6.
SYSTEMS
HOLD A
(13)
logic 1
on
161
this terminal tristates
the address and data buses
INTEL
8080
+ HLDA
(21)
(a)
logic 1 acknowledges 'hold'. This

signal goes high within a specified
delay of the leading edge of <f> v The

address and data buses are floated
within a brief delay after the rising edge
of the next 
S3
t=
t'
clock pulse
Look
for c
HOLD
t
HLDA
f =
01
10
(b)
Figure 6.15.
HOLD
y~
*
iÂ
HLDA
HLDA
System
reset
Figure 6.16.
SOLUTION
Step
Aim
of the design
the design
The aim of
is
to enable the
programmer
characters from a data source directly into a
using the d.m.a.
to transfer a block of
RAM of a microprocessor system
facility.
The microprocessor
is
tristated for three clock pulses
162
a pulse on terminal
0.5 to 1.5
of
c,
as
shown
Assuming a clock frequency of
in Figure 6.14.
MHZ, the duration of signal t is between 2 and 6 microseconds, and
t' between 667 nanoseconds and 2 microseconds.

The write cycle of the RAM to be used is shown in Figure
The reader is an action/status device see Appendix 1.
6.17.
databus
MoInternal
address
o.d.
(output disable)
c.e.
(chip enable)
RAM
R/W
Data
"
Address
~j)<~
o.d.
At
R/W
least
650 nsecs
At
least -
At
least
50 nsecs
150 nsecs
Figure 6.17.
1. Initial
cfc>
memory
address
2.
Block length
3.
'Go'
command
?-^r>î
Reader
(data source)
i
Interface
Figure 6.18.
address
6.
D.M.A. SYSTEMS
No
163
'
JYes
l^V
f =
No
Yes
Read
into
RAM
No
Decrement/increment
RAM address
Decrement word count
Activate reader
No
Raise e
Stop
Figure 6.19.
'
164
*3g
i
r
o
jossaoojdojonu uiojj
(qgiq) ssajppE Xjoui9J\
r
MOijjapufi
(moj) ssajppe Ajouj3J\
(moi) junoo
pjo^
wi
6.
D.M.A.
SYSTEMS
165
The block diagram
of our solution
is
shown
operation, after the initial conditions have been loaded,
is
flow-charted in
Figure 6.19.
Our starting point is the block diagram shown in Figure 6.4, showing a general
The implementation of interfaces 1 and 2 is shown in Figure 6.5
we assume that the block length is not greater than 256 words, then
corresponding system using the INTEL 8080 is shown in Figure 6.20.
d.m.a. system.
and 6.13.
the
If
The software required
to initiate the transfer of n characters from the reader
into consecutive locations in
RAM,
given the interface in Figure 6.20,
AC with
initial
RAM
address (high)
Load AC with
initial
RAM
address (low)
Load AC with block
length
Load
is
OUT
004
Load
RAM
initial
address.
OUT
004
OUT
Load block
004
length.
OUT
Start block
005
transfer.
When
execute service routine
OUT
006
EI
Clear
RET
Return.
flag.
Enable interrupts.
D.M.A. problem 2
System modification
Modify the solution of the previous problem so that only valid data, indicated
by
V=
1,
are read into
RAM.
SOLUTION
The specified modification is implemented by suppressing a d.m.a. cycle and
when V-r = 1 [Introducing variable r in the equation
initiating a read cycle
166
is sampled only when r = 1]. This is achieved by

modifying signals c and a in Figure 6.20 to the following form
ensures that the data
= EreV
tVr.
D.D.T. Systems
In this chapter
we
shall
be concerned with the design and implementation of

is with microprocessor
direct data transfer (d.d.t.) microprocessor systems, that
systems that allow data to be transferred directly between peripherals. The

design philosophy and design steps are outlined in Chapter 2, sections 9 and 10,
respectively.
7.1
INTRODUCTION
We wish to obtain a print-out of some

punched on a tape. We are told that for this purpose we
can use a tape reader and a printer in a microprocessor system with one
condition. We must not tie up the microprocessor for more than a few
microseconds each time we produce a print-out.
The methods available to us are
Let us consider the following situation.
information which
1.
To
is
read each character into the accumulator and print
Figure
7.1.
it,
as
shown
in
This method requires several instructions to be executed for the
transfer of each byte
problem
3 in
from the reader to the printer, as the solution of

Chapter 4 shows. As the execution time of each instruction is
typically a few microseconds, this

2.
To
read the complete tape into
d.m.a. channel in each case, as
method
is
automatically eliminated.
memory (RAM) and
shown
then print
it,
using a
in Figure 7.2. If there are n characters
on the tape, we shall need 2 x n d.m.a. cycles for the actual data transfer plus
half a dozen or so instructions to initialize the two interfaces, as we
explained in the previous chapter. The total time involved in this case,
although considerably
still
likely to
less
than the time involved in the previous method,
is
be over 100 microseconds with present-day microprocessors.
168
This figure
is
well in excess of the 'few microseconds' specified in the
problem. Furthermore,
this
available for this purpose,
that memory (RAM) space is

may not always be the case, and requires 2
method assumes
which
d.m.a. channels.
3.
To
establish a direct data link between the reader
show diagrammatically
in
Figure
transferred between the source
microprocessor, which
is left
7.3.
and the
printer, as
In such a system the data
we
is
and the acceptor independently of the
free to continue
with
its
own
activities,
thus
allowing us to meet the imposed restriction.
For the sake of clarity,
in Figures 7.1, 7.2
and
7.3
we do not show
peripherals.
Reader
Memory
-*
m.p.u.
Printer
Figure
7.1.
Reader
'
Memory
m.p.u.
Printer
Figure
7.2.
Reader
Memory
m.p.u.
Printer
Figure
7.5.
the other
7.
D.D.T.
SYSTEMS
7.2 D.D.T.
The block diagram

hardware
accessed.
set)
is
169
SYSTEMS
of our d.d.t. system
is
shown
in
given an I/O (input/output) address by
7.4. The
means of which
Figure
interface
it
can be
When the user wishes to establish a direct data link between a pair (or
of peripherals, he proceeds as follows.
He first determines whether the peripherals he intends to use are available or

not. He does so by polling signal b in Figure 7.4. This is a status signal that
indicates whether the peripherals in question are busy or not b equals
;
when
one or more of the peripherals are busy, otherwise b = 0. If the devices are
found to be free (not busy) he executes an I/O instruction with the address
given to the interface.
The
by
from the system

changing the
and (iii) initiating the data transfer which
interface responds
(i)
isolating
the section of the bus that links the peripherals in question,
value of the busy signal b from
to
1,
then takes place autonomously, that
is
(ii)
without programmer intervention.
When the complete data block has been transferred, signal b changes to and the
bus section becomes untristated.
- a
Hn
Source
'
I/O
Acceptor
Command
Status
signals
signals
Command
'
signals
Status
'
signals
Interface
signals
Figure
7.4.
INTERFACES
7.3 D.D.T.
The design and implementation of d.d.t. interfaces follow well-established

procedures and should present no difficulty to the reader who possesses a
working knowledge of logic design.
1]
170
it has been shown that the interface

For the sake of completeness we reproduce
In the case of action/status devices,!
hardware consists of two

the proof below.
Our
starting point
is
wires. 121
the block diagram in Figure 7.5(a). Its operation
is
flow-charted in Figure 7.5(b). For clarity of design we show no external control

signals at this stage.
From the implementation point of view, the interface is a logic circuit with r t
and
r2
as input signals,
and % and a 2 as output signals, see Figure 7.6. We shall

1, section 9 to implement our circuit, as
use the steps outlined in Chapter
we show below.
Step
External characteristics
See Figure
7.5.
Source
Acceptor
#1
#2
#1
#2
a2
activated
#2 idles
#1
fully
fully
responded
responded
#1 idles
#2 activated
Interface
(b)
(a)
Figure
7.5.
A suitable internal state diagram is shown in Figure 7.7. Its operation is as

follows.
Let us assume that device
is
active
and device 2
inactive.
The
corres-
our diagram is S This state is maintained while device 1

remains active. When it has fully responded, indicated by r t changing to 1, our
circuit moves to state S v Reference to Figure 7.7 shows that a 2 equals in state
S and 1 in state S l9 that is the S to S t circuit transition causes action signal a 2
to 1. This signal change activates device 2. When r 2 changes
to change from
ponding
state in
to 0, indicating that device 2 has
begun to respond, our
circuit
moves to
state
S 2 It remains in this state until device 2 has fully responded, indicated by r 2

changing to 1. When r 2 equals 1 our circuit moves to state S v As a t equals in
.
fSee Appendix
1.
7.
DDT. SYSTEMS
171
S lt the S 2 to S 1 circuit transition activates device 1 When

to state S
it responds, indicated by signal r t changing to 0, our circuit moves
itself.
repeats
cycle
The
responded.
fully
1
has
until
device
where it remains
state
S 2 and
in state
"
Interface
(see Figure
7.5(a))
"
Figure
7.6.
s\
SO
S2
#1
#1 responding
a2 =
fl,
idles
#2 responding
#2kttes
Figure
a1
a2
=
=
7.7.
The state table corresponding to our state diagram in Figure
7.7
is
shown in
Applying the reduction steps described in section 7 of Chapter 1,

the three rows of the table merge into a single row, as shown in Figure 7.8(b). In
the first square we enter circled entry S 012 since there is no other state that our
circuit can assume. The outputs in this square at this stage are <$>, 4>, indicating
Figure
7.8(a).
optional values.

By direct reference to the reduced state table in Figure
7.8(b),
we
obtain
"i
r x r 2
+r
r 2
+ (r
-r 2 )
r2
7(1)
r i -r 2
+r
-r 2
+ (ri
-r 2 )
rt
7(2)
r x -r 2 has not been used in the derivation of our

a t and a 2 a x = a 2 = in the first square in Figure
Since the optional product

final expressions for signals
7.8(b).
We shall refer to equations 7.1 and 7.2 as primitive interface equations. Their
implementation consists of two wires, as shown in Figure 7.9.
172
01
00
50
av a 2
51
1,0
1,
50
51
10
11
1,0
52
51
52
0,1
1,1
0,1
0,1
(a)
r
l'2
00
01
10
11
\co/
<lol2>
5012
= 0,0
<f>,
0,1
1,0
(b)
Figure
7.8.
'
#2
#i
-/
Figure
Go/No-go
- r
a 2"
7.9.
Control
In order that
we do not
lose information, unless
we
specify otherwise,
we
shall start a data transmission with a read operation and end it with a write
operation, as shown in Figure 7.10. Our read and write operations are as
defined in Figure 7.11.

inactive (G
this
We
0) states of
use signal
our system
to define the active (G
see Figure 7.12.
diagram, we obtain
The corresponding
ai
= G-r 2 +G-r 2 =
a2
= G-r
circuit
is
r2
shown
in
Figure 7.13.
By
1)
and the
direct reference to
7.
D.D.T.
Start
SYSTEMS
173
~)
No
*C
stop
JYes
Read
Write
Figure 7.10.
a, =
ux
-r 2
= G .^
Read
Write
Figure 7.11.
Figure 7.12.
#2
#1
-
-t 1
AND
Figure 7.13.
A
o-
'stop'
Figure 7.14.
4T
- r
174
If
the start/stop
commands
we can
are pulses,
use the JK flip-flop
in
Figure
7.14 to generate control signal G. Other implementations are clearly possible.
Read
Inhibit
(/ 2
= 1)
In our system a read inhibit operation
operation (a 2
shown
0)
By
in Figure 7.15.
is
implemented by suppressing a read
initiating in its place a write operation {a 1
and
direct reference to this Figure,
a2
= G -r
r2
-i
+G-r
-i 2
we
= G -rj,
as
obtain
'h
\.
=
a-,
a,
G.r,
Figure 7.15.
Write Inhibit
As
(/,
in the case of the read inhibit,
suppressing a write operation (a t

(a 2
= G -r 2
),
as
shown
we implement
a write inhibit cycle by
=0) and initiating instead
in Figure 7.16.
By
obtain
i
a2
= G -r,
r2
J
i
+G -r 2 -^
/,
=r 2
ax
=0
a 2 = G.rj
a2
a\
G.r 2
Figure 7.16.
'
01
00
al
a2 =
G./-J
a2
ax
a2
'
Figure
10
11
a 1 = G. ri
a read operation
7.17.
=0
=0
ax
=0
a2
G.r 2
we
7.
SYSTEMS
D.D.T.
175
Interface Equations
The values of the action signals for all combinations of read and write inhibit
7. 7. By direct reference to it, we obtain
signals are displayed in Figure
We
ai
?\
'h
a2
/,
-7
'
+ 'i
r2
-G -^
'h 'G
i
-?2
'
ri
-G
7(3)
-r 2
7(4)
above equations as our interface equations.
shall refer to the
7.4
In this section

The reader's attention is drawn to the fact that
although we use the INTEL 8080 to implement our designs, our procedures
apply to all types of microprocessors. Specifically, it should be noted that the
first
three
steps
in
the
design
executed without reference to the
are
microprocessor.
Problem
Copy
a tape
Reproduce a given paper tape using the
d.d.t.
mode.
SOLUTION
Step
Aim of the
The aim
d.d.t.
design
of the design
mode.
No
is
to
move data from a source to an acceptor using the
processing of data
is
required.
The reader and punch

generates an end-of-tape
are action/status devices. In addition the reader

(e.o.t.) signal.

operation
is
solution
is
shown
Reference to Figure 7.18 shows that the signals to be generated by our
and G.
and a 2 are derived
interface are: a u a 2 , b
Signals a r
directly
from our interface equations
176
-*-a
f^Di
^-j.^
G
fin
Tape reader
e.o.t.
Tape punch
(#2)
(#1)
,
,
~r
l
a \~
a2 -
r2
'
'
r
Interface
I/O
signals
1
Figure 7.18.
Execute I/O instruction
ft:
I
=
Punch
'
Read
-c
=Tn
e.o.t.
b:
=
"
C_
Stop
Figure 7.19.
7.
D.D.T.
SYSTEMS
(equations 7.3 and 7.4) by substituting Os for
The equation
for signal b
r1
a2
= G-r
177
and
2.
r2
is
+ r 2 + e.o.t. see
Figure 7.20
Address
decoder
AND
INTEL
8080
Tape reader
#1
\K
Tape punch
#2
AND
e.o.t.
NAND
~e.o.\
-~OUT
Figure 7.20.
We use a flip-flop, in our case aJKFF, to generate the go/no-go signal G. We

set the flip-flop with
tape
an I/O instruction.
It resets
automatically with the end-of-
(e.o.t.) signal.
With the exception of the I/O

Problem 2
'go' instruction,
no other software is required.
Clean a tape
Copy a paper
tape deleting rub-out characters
(all Is).
SOLUTION
Step
Aim of the
design
The aim of the design

rub-out characters
is
to reproduce incoming data selectively. In our case
(all Is) will
not be reproduced.
178
The tape reader and tape punch
are action/status devices. In addition to the
action/status signals, the tape reader generates an end-of-tape
(e.o.t.) signal.
The block diagram

operation
is
of our solution
is
shown
U2
AND
G
i
'
/*n
Tape reader
e.o.t
Tape punch
#1
#2
-r
a l~
- /'
'
I/O
r
Interface
signals
Fig ure 7 2 1.

Reference to Figure 7.21 shows that our interface, as in the previous
problem, is required to generate four signals, namely a t a 2 b and G.
,
and a 2 are derived directly from our interface equations

for x and 2 respectively. Signal
7.3
and
(equations
7.4) by substituting d and
that is d = 1 indicates a
signals;
bus
data
eight
the
ANDing
d! is generated by
rub-out (delete) character. It is sampled when r t = 1, that is when the data
Signals a x
from the reader
The equation
is
stable.
ax
5-r t
a2
cl'G r 1
for signal b
r1
Signal G, as in problem
-r 2
+ G -r,
-d
is
+ f 2 + e.o.t.
1, is
see Figure 7.23.
generated by the JK flip-flop in Figure 7.23.
It is
7.
DDT. SYSTEMS
Start
179
'<
Load tape
No
x^Devices^
^s^ready/^
i
Yes
Execute I/O instruction
b:=l
Punch
Read
No
ft:0
Stop
Figure 7.22.
set
by the I/O
(e.o.t.)
'go' instruction
and
is
reset automatically with the end-of-tape
signal.
With the exception of the I/O
'go' instruction,
no other software is required.
180
Address
AND
decoder
T
Reader
Tape punch
d'
#1
#2
d'r
x-
AND
r 2-
OR
GINTEL
8080
r \-
AND
d'
AND
d''
AND
NAND
'l
2
e.o.t.
e.o.t.
0/T
WR
Figure 7.23.
7.5
REFERENCES
1.
Zissos D. 'Problems and Solutions in Logic Design', Oxford University
2.
Zissos D.,
Press, 1976.
Duncan
F.
G. and Colin T.
J.
'Logic-free
Electronics Letters, Vol. 10, No. 17, August 22, 1974.
Data Channels',
Appendix
The concept of action/status devices
implementation is outlined.
A1.1
In 1974 Zissos,
explained and a method for their
is
ACTION/STATUS DEVICES
Duncan and
Collin proved that the interface between a pair of
action/status devices consists of two wires. 11

terminals, an action terminal
Signals a
and
Signal
A
No
Signal
a.
r.
to
and a
'
2]
Action/status devices have two
status terminal, as
shown
in
Figure Al.l.
have the following meaning.

1
signal transition
activation
is
on the action terminal
possible
when
This signal indicates the availability

of the device.
activates the device.
0.
(r
1)
or unavailability
(r
0)
Now, most devices in practice require a sequence of command signals to

operate them, and do not therefore fit our action/status model. Such devices,
however, can be readily modified into action/status devices by means of some
simple circuitry, the front-end logic, which
A1
.2
we
describe below.
FRONT-END LOGIC
The block diagram of a front-end
logic
is
shown
in Figure A1.2. Its function
is
monitor the status signals of the device and to generate the correct sequence
of command signals to drive the device when action signal changes from to 1
In addition it generates the status signal r. Its implementation is
straightforward and uses the procedures outlined in Chapter 1
to
182
Status
signals
Front-
Action/
end
Device
status
device
logic
Command
signals
Figure Al-1.
The main
Figure
difficulty likely to
interpretation of the status
useful, in that
it
be experienced by the reader
and command
manufacturer. Such an exercise,
A 1-2.
is
the correct
from data supplied by the

although tedious, has been found in practice
signals
provides the user with the opportunity to clearly understand
and idiosyncrasies of the device before he uses it. We

below some general guidelines for the design of front-end logic circuits.
In order that the input drive requirements of all devices equipped with front-
the operational features

give
end logic are

but instead
state
we
identical, the action signal
it is
used to
generate the
status signals.
When
is
not used to drive the device directly,

next state. In this
initiate the circuit transition to the
first
command
signal
and monitor the corresponding
the device has fully responded to the
first
command
our front-end logic generates the second command signal. The process
continues until the device has fully responded to the last command signal. At
this point the circuit assumes its initial state when a = 0. This ensures that the
signal,
front-end logic responds only to the leading edge of an action pulse, and allows
the device to free-run by connecting its ready (status) signal to its action
terminal.
We shall demonstrate our steps by means of the following example.
Example
Design the front-end logic for a digital printer (Figure Al .3), whose terminal
characteristics are.
Terminal
w A ground on
this terminal
(w
0) positions the print wheels
according to the input data.

Terminal x While the print wheels are being positioned, x = 0. This signal
changes to 1 when the wheels are correctly positioned.
Terminal y Grounding terminal y causes the print hammers to strike and the
paper to advance to its next line position.
Terminal z Signal z = when the print hammers are being activated and the
paper
advancing, otherwise z
a, x and
diagram of a suitable
In this example
state
is
z are input signals

circuit is
shown
1.
and w, y and
in Figure
r are outputs.
The
A 1.4. By direct reference
APPENDIX
to this
ACTION /STATUS DEVICE
1.
183
diagram we obtain
A = B-x
A = B -a-z l^B + a + z
of B = A -a
turn on set of
turn off set of

turn on set
Digital
printer
w x
A 1-3.
Figure
51
50
H>=1
M>
yr=
AB-=
00
01
az,
10
LI
w=l
w=
- i
r = z
r ==
52
53
Figure
A 1-4.
Therefore, the circuit equations are
A =B-x+A-(B + a + z)
B = A-a+B-(A + z)
w = S t =A'B
y
S
*^2
=A+B
+ S +S 2
1
'
-x
+ S3
"^
= S2 + x
=A+B+x
The
circuit
implementation of these equations shown in Figure
consistutes the front-end logic of the printer (Figure
A 1.5).
A 1.5
184
;=D
H>
:=D>
Figure
A1.3
1.
Zissos, D.,
Duncan,
F.
A 1-5.
REFERENCES
G. and Collin, T. J. 'Logic-free Data Channels',

No. 17, August 1974.
Electronics Letters, Vol. 10,

2.
Collin, T.
J.
Calgary, 1974.
'Logic-free
Data Channels', M.Sc.
Thesis, University of
Appendix 2
The INTEL 8085

A2.1
GENERAL
The INTEL 8085 has been evolved from
[t]
the
INTEL
8080 as a
result of
evolutionary advances in technology, which have been taking place in the last
ten years or so,
Its
main
and of the experience acquired using microprocessor systems.

from the system designer's point of view are summarized
features
below.
(i)
Single
+5V Power Supply.
This feature
is
particularly useful in the case
of portable equipment, as well as keeping the cost and complexity of
small systems low.

(ii)
Single
System Clock.
The use
of
single-phase
clock
reduces
considerably the timing constraints on the interface signals that must be

observed by the system designer. The minimum and maximum clock
frequencies are 0.5
MHZ and 3 MHZ. The clock circuitry
chip and only an external crystal or an

signal, 0, is
output on pin 37
see Figure A2.1.
on the trailing edge of

attention is drawn to the fact that
transitions take place
The
cycle,
reader's
One phase
built
on the
The
internal circuit
</>.
two-phase, non-overlapping lock
oscillator.
is
RC network is required. The clock
of this clock
is
is
internally a
50% duty
generated from the external
made
available to the user.
(iii)
Reduced Chip Count. The high level of component integration allows a

minimal system to be produced using three i.e. chips, namely 8085
(m.p.u.), 8155 (RAM) and 8355/8755 (ROM/PROM).
(iv)
M.P.U. Signals. These are shown in Figure A2.1. Generally speaking they
are clearly-defined and well-chosen, with perhaps two exceptions, (a)
fFor a more detailed description of the
INTEL
8085 see reference
[1].
186
READ Y
(35)
a*
^>
d*
A '0' puts the 8085 in the wait state and a '1' takes
The
line is
machine
sampled during
on
cycle,
it
out,
T2 and Tw of each
$ see Figure
states
the leading edge of
A2.5.
(6)
TRAP
Non-maskable interrupt. A '0' to '1' transition causes

the program to vector to location 000 044 8
(9)
RST 7.5
'0'
'1'
to
transition causes
location 000 075 8

(8)
(7)
(10)
program
RST6.5
^
^
RST 5.5
T causes program to vector to location 000 065

A T causes program to vector to location 000 055
INTR
'1'
HOLD
(36)
RESET IN
A '0' resets program counter

state
tristates a, d,
Ml-
RD,
Figure A2.5.
7/1 in
and disables the
cycle.
WRJ/OM and ALE terminals.
(39)
8085
program (asynchronous). A RST

CALL instruction is jammed on the data
bus during the Interrupt Acknowledge

'1'
interrupts
(restart) or
INTEL
to vector to
INTR
and
It
forces the 8085 into
also sets
all
KSTmasks
terminal.
Sj
Software halt
(29)
(33)
^
^
I/OM*
WR*
'0'
indicates data out
(32)
RD*
'0'
indicates
(ID
INTA
This signal
(3D
(30)
(3)
is
from the 8085.
">
Not
in the input
limited to 1/Os.
mode J
generated during the instruction cycle

It is used
and has the same timing
AT
ELDA
acknowledges HOLD. Lines

beginning of the next clock cycle.
ALE*
Use
trailing
edge to latch address
as
RD
(pin 32).
tristated at the
lines
to 7.
The
following edge of ALE is set to guarantee setup and hold

times for the address information.
RESET OUT
Indicates 8085
SID
Serial input data.
(5)
(4)
-> SOD
(37)
>
</>
Serial
halt'.
is
being
output data.
System clock.
Figure A2.1.
Tristated during 'software
d bus
Instruction fetch
INTR (interrupt) signal is accepted.
instead of
>
^
indicates 'I/O execute'.
an
after
(38)
Read
'1'
(34)
Write
Status information-
reset.
APPENDIX
Terminal
I/OM
THE INTEL
(pin 34 in Figure A2.1)
'halt' instruction. If, therefore, in
I/OM
signal
will
go high
is
187
8085
tristated
during a software
a given system a pull-up resistor is used,
(logic 1)
when
the microprocessor
is
erroneously indicating to the system that an I/O instruction

executed, and (b) No
is
in a wait state, as
being
'WAIT' signal is provided to indicate when the 8085

is
Multiplexed Data Bus.
(v)
halted,
is
the case with the 8080.
The INTEL 8085 uses a multiplexed data bus. The
multiplexing operation
is
probably best understood by referring to

It can be seen from these Figures
Figures 2.2 and 2.3 on pages 35 and 36.

that during state Tj of each
information. Therefore,
it
bit address, eight of the 16
during state
machine cycle the data bus,
d,
carries
no
follows that in an eight-bit machine with a 16-
address signals can be output on the data bus
T and latched before it (the data bus) is used for memory or

x
I/O data. This would release eight
pins, that
can be used for other
method of bus-multiplexing is used in the INTEL 8085.

Figure A2.2 we show the time-multiplexing of the data bus during an
purposes. This
In
instruction-fetch
denoted
cycle,
{Address Latch Enable)
is
by
Ml
in
Figure
a timing pulse generated by the
each machine cycle before
it
enters state 72.
The
A2.3.
I
trailing
'ALE'
NTEL 8085 in
edge of A LE
is
allow for set up and hold times for the address information. For
set to
timing diagrams,
if
needed, see reference [1]
Ml
71
PC H to^ g -^ 15
PC L to d
d latched with ALE
PC L
M1-T2
l^^L
PChIoAi-Ak
ALE-
dto I.R.
mi-t:
pc l
LATCH
PC H toA t -A ls
Latch to
A 0~ A 7
dtc I.R.
Ml-TA
i,Ml-[T2+
73]
I M1-[T2
PC H toA % -A X5
Latch to
- A7
d tristated
Instruction
Figure A2.2.
73]
05
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II
vt
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rs
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r~-
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r~
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189
8085
_
00
00
W
oo
^
S
r-
m
2
tJ-
s'z
c en
00
(/3
<
<U
s-c
(50
<
aj
:~r
rii i^lvelmlUiîglJi
-i-i-i_-iSiSiSi
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I T T 7 7
190
The INTEL 8085 has an identical instruction set as the

INTEL 8080, with the exception of two additional instructions, the SIM
(Set Interrupt Masks) and RIM (Read Interrupt Masks); see Figure A2.3.
SIM transfers the contents of the AC into the Interrupt Mask Register,
and RIM allows status information to be read into AC, as shown in
Instruction Sef\
(vi)
Figure A2.4.
(vii)
Wait /Go Mode. The design and implementation of 8085 wait/go systems,
as with
all
microprocessors,
is
discussed in the next section.
straightforward. 8085 wait/go systems are
of wait/go logic
The design
would have
been somewhat simpler, had a wait signal been made available to us. A
Nvait' signal, as we have already explained in Chapter 3, is a signal
indicating to the system that the microprocessor has entered a wait (idle)
state.
(viii)
Test-and-Skip Mode. Systems using the test-and-skip mode can be

designed and implemented conventionally, as we show in section A2.3.
The interrupt structure provides for (a) A non-maskable

vectored interrupt, TRAP, on pin 6 (see Figure A2.1). (b) Three
Interrupt Mode.
(ix)
direct
direct vectored interrupts,
on pins
7,
and 9 and
vectored interrupts, as in the case of the
DMA.
(x)
Mode.
No
special
INTEL
exist
features
(c)
Eight indirect
8080.
the
for
design
and
implementation of the systems using the d.m.a. mode.

(xi)
D.D. T. Mode.
As
in the case of the d.m.a.
INTEL
mode, the
8085 has no
special features.
A2.2
WAIT/GO SYSTEMS
present-day microprocessors, the INTEL 8085 does not

are
execute wait/go cycles. These, as we have already explained in Chapter 3,
the
which
during
A
by
denoted
w
I/O cycles with wait/go addresses,
the
microprocessor enters the wait state automatically and leaves it when
a
produce
to
user
the
to
is
left
It
1.
to
line changes from
In
common with
all
signal
on the
'go'
The
wait/go logic, which will allow him to initiate wait/go cycles.
63.
page
on
3.12
Figure
in
shown
is
logic
block diagram of a wait/go
point is the internal state diagram of the INTEL 8085 during
circuit, the
Our
starting
I/O cycle. This is shown in Figure A2.5. As in the case of the

a wait/go cycle by causing the microprocessor,
implement
8080, we
the execution of an
INTEL
when it leaves state M3- T3, to

The transition to state M3-T3
line, g,
enter wait state

is
M3- Tw
to be initiated
by a
instead of state
to
M3- T3.
change on the
'go'
in Figure A2.6.
fThe instruction set defines the set of operations that can be performed by a central
processor unit.
T
lip
II
II
II
ll
ll
%
Q
^
is
rr
l
ii
Itj}
6
to
OS
+
^
--Or-i
II
II
OOOJ^
o
II
II
II
3
3
ii
II
ii
>**
ilco
1=1
5!
1
^
9-ooto,
-e-H5j
^
3
II
ii
***>
IS
ii
or
ii
>x
*=!
IS
||
0|
^
^
Jl
to
T3
"S,
^+
"
^
S3
&s ^<fc 3HCo

II
IS
c o
t~
3
'B
II
ICp
"
".
<
"
IS
ItO
+;
HOOi/l
-S-ooco
ii
ii
o
to
o
to
+
"
"B. ?f

"8
-ft
00
ll
>** i ^
1
Q
^
S
Q
^
ll
is
o"
II
IS
*=!
i-H
JL
Co
g.
rii
y-
CO
^
Q
^r
lOOO
II
II
II
"^
0,
=
READY
1*
3
O/M
to
to
-OOto
II
II
II
-S-ooO
_-
IS
ii
"N
>-i 
(37)
Wait/go
So
(29)
..
(33)
(35)
logic
READY
Figure A2.6.
by
by applying a logic '0' on pin 35. Since this
'0' on the
line is sampled during states T2 and Tw we need to generate a logic
READ Y line when the 8085 enters state M3- T2 and the a bus contains a wait/go
Now,
pulling
reference to Figure A2.5 shows that the 8085 enters the wait state
its
READYhne low,
that
is
The '0' signal on the READ Y line is maintained until the 'go' signal,
'0'
from
to T, at which time we must pull the READ Y line high. This
changes
g,
3- T3, at which point it resumes its
allows the microprocessor to move to state
normal operation. Reference to the m.p.u. chart in Figure A2.1 shows that
during the execute cycle of an I/O instruction a '1' is generated on pin 34. This
address, A w
denoted by I/OM. Also I/OM may be pulled high during a software

A2. 1 (iv). It is, therefore, necessary for our wait/go
logic not to look at the I/OM terminal during a software 'halt'. Reference to the
m.p.u. chart (Figure A2.1) shows that during software 'halt' both thestatus
equal to '0'. Therefore, use AND status signal I/OM with
signals S and S
signal
is
halt, as we explained in section
S -S 1
that
l5
is
the signal looked at by the wait/go logic
demultiplexing and multiplexing of the

to Figure 3.10
on page
It
+S
(S
t ).
V and
'g'
</>,
lines.
The reader
is
referred
62.
suitable internal state
A2.7.
I/OM
our wait/go logic must

For the sake of clarity we do not show the
Therefore, in addition to signals
monitor status signals S and S t
I/OM, A w and
is
diagram
for our wait/go logic
is
shown
in
Figure
operates as follows.
The normal state of the circuit is Q0. This state is maintained while the 8085
maintain
is active and the peripherals using the wait/go mode are inactive. To
is
looking
circuit
our
this
state
In
high.
the 8085 active we keep its READY line
bus
the
address
sample
it
must
purpose
this
For
for a wait/go address, A w
8085
when
the
Now,
Figure
A2.5.
71
in
M3state
in
when the microprocessor is
is in state M3-T1,
I/OM = 1, and
.
Thus, we can use signal
l/OM(S + S 1 )A w
to
move
to the next state.
APPENDIX
8
O
II
THE INTEL
8085
193
j
line
1 ^H
come
II
wait
II
II
8085inAf3-7w,
Peripheral
/t42Y
responding
"
[papuodsai
Xnnj |BJ3qdu3,j]
to of
II
II
state
out
high
Pull
Ot
'3
c
0.
*=!
=!
"e3
Ibc
J3
a.
c
v
II
I-H
r^
II
II
from
peripheral
VV
peripheral
8085inM3-n
Activate
read
11
"
Data
01
^1
000
11
11
<
'
11
-.00
11
11
11
11
_c
lO
oo
o Ooo
00
00
OS
o
CO
*=!
IS
,0
< so
^^
J9 *
o
>
</f
^00
II
II
H OO
-e-
II
II
CO
c
-o
13
<<
00
a 00O
II
II
194
io
II
1^
loq
OS
loq
05
U
Q
<
IB
I-t;
Icq
00
oi
<
s-
60
'^Kj,,
TU
o h
to
to
It
N
160
1^
(J
l<J
03
HJ
03
I"
APPENDIX
Because
circuit transitions in the
THE INTEL
8085 chip and
in
195
8085
our logic take place on the
Ql
same time as the

Q\ we pull the
READY signal low. This allows the microprocessor to enter the wait state on
the next clock pulse. Our circuit at the same time moves to state Q2. At this
point we generate our 'wait' signal, w. The change of signal w from to 1 is used
trailing
edge of
<j>,
our
moves
circuit
microprocessor moves to state
M3-T2
to state
at the
in Figure A2.5. In state
To ensure that our circuit does not get 'out of step',

Q3 until signal g goes low. This tells us that the
peripheral began to respond. We remain in state Q3 until the peripheral has
fully responded, that is until 'go' signal g changes back to 1. In state QA we pull
to activate the peripheral.
we do not move
the
to state
READY line high to allow the 8085 to come out of the wait state. It does so
on the next clock pulse. At the same time our wait/go logic moves to state Q5.
Data is read from the accumulator, if the peripheral is a source, when the 8085
is in state M3-T3. Therefore, in state Q5 enable signal e must be high.
From state Q5 we can go directly to state Q0. However, this would result in a
six-state diagram, that is in a circuit with two unused states. To avoid this
Chapter 1 (page
normal operation of our circuit.
situation, for reasons outlined in section 6 of

states
Q6 and Ql
in the
Clearly, the value of the
when
the 8085
terminal
is
is
we
insert
READ Y signal need only be specified in state Q0 and
in state
sampled only
14),
M3-T2
in states
or
M3-Tw
T2 ad
Tw
This
(see
is
because the
READY
Figure A2.1).
Because the 8085 enters the wait state during the I/O execute
can be equated to w see equation 3(a) on page 60.
cycle, signal e
To
is
line, w, we use a race-free code

Such a code, derived by direct reference to Figure 1.8,
avoid unwanted signal spikes on our wait
to define our eight states.
shown
in Figure A2.7.
SA =
ra =
SB =
=
Q1
By
= ABC,
therefore J A
qS= ABC,
we obtain
= BC
therefore
K A = BC
therefore
JB
Q0jl/OM(S + S 1 )A w + Q 4
ABO I/OM- (S + S
)A w + ABC,
AC-l/OM(S + S
Rs = Q2g + Q6 = ABCg + ABC,
S c = Q3g = ABCg,
R C = Q1 = ABC,
READY= Q0 + Q4 + Q1 + (Q5) + (Q6)

= ABC + ABC + ABC + (ABC) + (ABC)
= AB+C
e = w = Q2 + Q3 + Q4 + (Q5)
= ABC + ABC + ABC + (ABC)
=A
Reset signal = System reset + TRAP
therefore
therefore
therefore
)A w
+AC
K B = ACg + AC
Jc
= ABg
K c = IB
196
System
reset allows
rest of the system,
our
and
circuit to get in line (to
TRAP
allows
it
be synchronized) with the
to get out of the wait state in
emergencies.
The corresponding
circuit
is
shown
in Figure A2.8.
SYSTEMS
A2.3 TEST-AND-SKIP
The block diagram of a test-and-skip microprocessor system with one device is

shown in Figure 4.2. Its operation is flow-charted in Figure 4.1.
The I/O signals, as in all microprocessors, are generated by executing I/O
instructions. In the case of the INTEL 8085 the I/O instructions transfer data
in or out of the microprocessor through the Accumulator. Up to 256 input and
up to 256 output ports can be directly addressed. Condition flags are not
affected by the execution of I/O instructions.
The I/O signals are shown in Figure A2.9. Their timing is shown in Figure
A2.10. For the sake of clarity, we are not showing 'rise' and 'fall' times. For
detailed timing diagrams, the reader
referred to reference [1].
is
The block diagram of a test-and-skip system using the INTEL 8085 with one
acceptor and one source is shown in A2.ll. Signal rp = 1 when the source has
data available. Similarly, rq 1 when the acceptor can accept data. Tristate
signal ep is generated by ANDing Ap, Rd and I/OM.
RD
IO/M
WR
T indicates db\xs in input
mode.
T indicates I/O execute.

A T indicates data from
AC
is
on r/bus.
Figure A2.9.
A2.4 INTERRUPT
SYSTEMS
[1]
The INTEL 8085, as we have already mentioned, has five interrupt inputs.
TRAP,RST7.5,RST6.5,RST5.5andINTR see Figure A2.12. There areno time
constraints on these inputs they can occur at any time. The interrupt terminals
(pins 6, 7, 8, 9, 10 and 1 1 in Figure A2. 2) are sampled during the last clock period
;
APPENDIX
<***,,
n n
THE INTEL
A/2
A/1
T4
T\
T2
197
8085
A/3
T3
r2
73
^_TLRJLmUl^RJ
RD
I/O (IN)
1
IO/M
"1
I
I/O (OUT)
WR
Figure A2.10.
of the instruction that is being executed. They have a fixed priority relative to
each other, shown below
TRAP
highest priority
RST1.5
RST 6.5
RST 5.5
INTR
lowest priority
m
Address
decoder
An A D An
'P 'q
Other
status
signals
INTEL
Source
Acceptor
#P
#q
8085
Interface
(32)
(34)
MM'
~m
Interface
-*~RD
IO/M
(31)
Figure A2.ll.
Jf7?
198
TRAP
a non-maskable
is
emergency
RST
situations. This signal
are being sampled, but
it
will
(restart) interrupt,
used primarily for
must be high when the interrupt terminals
not be recognized again until
it
goes low, then
high.
The three direct restarts, RST 7.5, RST 6.5 and RST 5.5 can be individually
masked (disabled) under program control using the SIM instruction see
Figure A2.4. Note that RST 7.5 request can be set even though its mask is set
and the interrupts are disabled. Reference to Figure A2.1 shows that a '0' on
pin 36 sets
INTR
is
all
the
RST masks, that is
it
disables pins
used as a general purpose interrupt.
input in the 8080; that
is, if
7,
and 9
in
Figure A2.12.
to the interrupt
It is identical
INTRA were the only valid interrupt and iUNTEFF
(interrupt enable flip-flop)
and enter an
same as the interrupt cycle of the 8080.
the 8085 will reset the flip-flop
is set,
interrupt-acknowledge cycle. This
is
the
This cycle is identical to an instruction fetch cycle with two exceptions. INTA
sent out instead of
INTA
is
RST
must provide the op code of an instruction

Although any instruction will do, the logical choice is either a CALL
(restart) instruction.
(6)
INTEL
RD see Figure A2.10. The address lines are ignored. When
sent out, the interrupt logic
to execute.
or a
is
<-
TRAP
is
because both instructions force the
Non-maskable
restart interrupt.
o
to
transition
causes the 8085 to vector to locations 000 044 8 at the

end of the current instruction. Must be high when
terminal is being sampled. Asynchronous.
RST7.5
(9)
This
'0'
to
location
8085
T transition causes program to vector to

000 075 8 at the end of the current
Asynchronous.
instruction.
RST 6.5
(8)
(7)
(10)
^
<-
RST 5.5
AT
causes program to vector to location 000 065 8 at

the end of the current instruction. Asynchronous.
AT causes program to vector to location 000 05 5
at
the end of the current instruction. Asynchronous.
AT interrupts program at the end of the current
INTR
instruction.
jammed on
A CALL
or
RESTART
instruction
is
the data bus during the interrupt cycle.
Asynchronous.
(11)
INTA
>
This signal
after
is
generated during the instruction cycle
an INTR signal is accept ed.l t is used instead of
and has the same timing as RD.

Figure A2.12.
ÎNTR
is
disabled by
RESET as well
as immediately after an interrupt
is
accepted.
APPENDIX
THE INTEL
8085
199
microprocessor to push the contents of the program counter onto the stack
before jumping to a new location. If this statement is not clear, the reader is
1 in Chapter 5 (pages 109 and 1 10). Because in the case of the
8080 we have used the RST instruction (see section 5.4, page 120), we shall now
referred to section
CALL instruction.
use the
After receiving the
opcode
in state
M1-T3
in
Figure A2.5, the processor
Ml* TA and determines that two more bytes are

required. The 8085 then executes two more machine cycles to obtain the
second and third bytes. As in the case of the opcode, bytes 2 and 3 are jammed
decodes
it
in the next state
on the data bus when INTA = 0. The program counter is not incremented
during interrupt acknowledge cycles.
During machine cycles MA and M5 the 8085 pushes the upper and then
lower bytes of the PC onto the stack and places the two bytes accessed in M2
and M3 in the lower and upper halves of the program counter. This has the
effect of jumping the execution of the program to the location specified by the
CALL
instruction.
In Figure A2.13
we show a simple arrangement, consisting of a scale-3
CALL
Initially the counter is reset by the RD
pulse
counter and three I/O ports, for jamming a
instruction during an
interrupt cycle.
pulses
on
its
reset line.
INTR (interrupt) signal is accepted, RD

pulses are suppressed. Instead three INTA pulses with the same timing as RD
During the interrupt cycle
are generated.
AND
INTEL
We
110
after
an
use these pulses to step up our counter. If our counter
110
A B
AND
AND
rr
rr
A B
A B
8085
INTA
INTA
(11)
TFF
TFF
RD
(32)
Figure A2.13.
is
200
incremented during the trailing edge of a clock pulse, then the correct timing for
CALL instruction is
AB INTAinsert opcode 11001101
AB INTA insert byte 2 (low address)
AB INTA insert byte 3 (high address)
The counter resets with the next RD pulse.
inserting the three-byte
A2.5
1.
MCS85
User's
Manual
REFERENCE
(Preliminary), Intel Corporation 1976, 1977.
73 555
Index
Asynchronous sequentive
ASCII
circuits
115
characters, 74
Flag identification, 1 1
polling method, 1 1
vectored method, 1 1
Flag sorters (priority encoders)
Action/status devices, 96, 181
Boolean algebra, 2
Theorems:
1. Redundancy,
2-flag sorter,
1 1
64-flag sorter, 118
2.
Race-hazard, 3
3.
De Morgan's
Front-end
logic,
182
Gates, 11
I/O ports, 50
I/O signals,
stretching, 93
Clock-driven
1 1
8-flag sorter, 117
Boolean reduction, 8
circuits,
25
Clock pulses, 25
Clocked flip-flops, 26
Combinational circuits,
circuits, 113,
Flag, definition,
Accumulator [AC], 34
Clock
Flag
see Event-driven circuits
for
for
1
(DFFs), 25, 26
D.D.T. mode, 46
D.D.T. problems and solutions, 175
problem 1: Copy a tape, 175
problem 2: Clean a tape, 177
D.M.A. mode, 46
D.M.A. problems and solutions, 160
problem 1: Reader to
interface, 160
problem 2: System modification, 165
Design philosopy, 53
Design steps, 53
flip-flops
RAM
Emergency interrupts for the INTEL 8080, 124
EPROMS, 48
Event-driven circuits, 20
design factors, 20
design steps, 20
INTEL
INTEL
8080, 97
8085, 185 et seq.
for M6800, 68
I/O synchronization, 39
INTEL
8080,
instruction set for, 77
INTEL
8085
instruction set for, 185 et seq.
M6800
instruction set for, 80
Interface, definition, 52
Interface equations, 171
Interrupt Acknowledge,
1 1
Interrupt cycle,
of the Motorola 6800, 125

of the INTEL 8080, 120
of the INTEL 8085, 185 et seq.
Interrupt mode, 45
Interrupt routine, 109
Interrupt signal, 110
Interrupt systems, 109, 110
Problem 1: An event-counter, 127
INDEX
202
Problem
RAM
2:
to printer interface, 138
Instruction register (IR), 34
Instruction
JK
flip-flops
sequential,
SR
flip-flops (SRFFs), 25, 26

Semiconductor memories, 47
EPROMS, 48
PROMS, 48
RAMS, 49
ROMS, 47
Logic design definition,
Sequential circuits,
Memories
Memory
see Semiconductor
memories
State reduction,' 14
Microprocessor,
definition, 32
modes of operation, 44
D.M.A., 46
D.D.T., 46
Terminal characteristics
the
PR40
96
printer,
a reader, 96
flip-flops (TFFs), 25, 26

Test-and-skip systems, 91
45
test-and-skip, 45
problems and solutions, 94

to printer, 95
problem 1:
problem 2: Reader to RAM, 100
problem 3: Read and print in characters, 103
Time sharing mechanism, 34
wait/go, 45
RAM
M.P.U. charts
8080, 43
8085, 185 et seq.
Motorola 6800, 44
M.P.U. signals, 42
INTEL
INTEL
of,
a digital printer, 182
interrupt, 45
INTEL
INTEL
Sequential equations, 1,15

Stacks, 50
synchronization, 38
internal,
96
et seq.
(JKFFs), 25, 26
Logic circuits
combinational,
characteristics,
Re-entry point, 110

Restart instruction, 120
ROMS, 47
set,
of INTEL 8080, 77
of INTEL 8085, 185
of M6800, 82
Reader terminal
Tristates, 13
Two-wire
8080, 43
8085, 185 et seq.
Motorola 6800, 44
NAND circuits,
NAND gates,
interfaces
for wait/go systems, 59
action/status devices, 181
Unused
states, 14
Wait/go
cycles,
Printer terminal characteristics, 96,

Priority encoders (flag sorters), 115
82
concept, 56
logic,
62
Program counter (PC), 34
for the
Program,
for the
Program
definition, 32
for the
charts,
for
INTEL
8080, 76
for
M6800,
81
PROMS,
48
Pulse-driven circuits,
for the
definitions, 13
RAMS,
49, 162
M6800
M6800
8080, 63
8085, 185 et seq.
(circuit 1),
67
(circuit 2), 71
Wait/go mode, 45
Wait/go states, 38
Wait/go systems, 55
main
Race-free diagrams, 21
Race-hazards, 13
INTEL
INTEL
properties, 56
problems and solutions, 73

problem I: Search for a record, 73
problem 2: Read and print n characters, 83
problem 3: print a record, 84
Following his pioneering work in Logic Design, Professor Zissos now

presents the field of microprocessors in an accessible and easy-to-read
form. Microprocessors have become more and more readily available
over the last ten years, bringing computer technology into play in
contexts as different as the home, the hospital or the factory. Computers no longer have to be megaliths, expensive, unwieldly and complicated to maintain and operate: the new microprocessor systems,
often portable, and using increasingly powerful and compact "chips" at
very low cost, are the perfect working alternative to the inscrutable
world of traditional computer hardware.
designed to satisfy the current demand for knowledge
microprocessors work and how they can be used. It is
written in the direct, demystified style characteristic of Professor
Zissos, and is designed not only lor those with a specialist knowledge
ol electronics but also for the non-specialist, (such as system designers,
communications experts, non-electronic engineers, physicists, chemists
and medical experts who wish to construct their own microprocessor
systems.) No previous knowledge of microprocessors is assumed, A
special feature of this book is the inclusion of the author's original
work with his research assistant J.C. Bathory on the wait/go operation
of microprocessors. At the end of each chapter the reader will find a
section on 'Problems and Solutions', which illustrate in detail the steps
used in design and implement, microprocessor systems: all design
algorithms are independent of the microprocessors themselves right up
to implementation stage, and always work.
This
book
about
is
how
comprehensive account of the $ubje<

in the fields of teleeommunioatioi
engineering, digital system design, civil and
This
ihose
inst
be of great interest lo
medical physics and biolechanicaJ engineering, and
will
rumen la lion.
Other hooks by D. Zissos art: Logic Design Algorithms (1972), Digital Interface
Design (1974), and Problems and Solutions in Logic Design (1976), all published by
Oxford University Press.
London New York San Francisco

Subsidiary of Harcourt Brace Jovanovich, Publishers
24-28 Oval Road. London NW1, England
Fifth Avenue, New York, NY 10003, USA
!
AuHtralian office. I'O
Printed
in
England
Box 300, North Ryde,
NSW
2113, Australia
0.12.781750,6
mm

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icroproce

System Design with

SYSTEM DESIGN WITH

Department of Computer Science. University of Calgary,

Research Assistant, University of Calgary

Subsidiary of Harcourt Brace Jovanovich. Publishers

ACADEMIC PRESS INC (LONDON)

United States edition published by

:cond Printing 1979

Aii Rights Reserved

No part of this book may be reproduced

Library of Congress Catalog Card Number: 78-54544

THE IMPACT OF THE NEW TECHNOLOGY ON COMPUTING

new technology on the computing environment. It

summarize the opinions which

have formulated from the extensive

discussions which have already been carried out.

demise of computer centres and the impending obsolescence of networks.

own powerful computing system on the desk for a few pounds.

show that whilst there will be a shift towards dispersed

costs are averaged over the

computer installation they are found to comprise about 80% software,

realise that the

not provide a viable market

data processing capability of the world in 1978 represented two weeks

The data processing market place

comprise the low volume/high cost

level units will

be constructed from the

chips with a corresponding increase in costs. Such systems, in terms of

Computer systems do not however consist of hardware

be provided in the same

purpose chips for example will also be single purpose, relatively

unalterable by the user, and will not be maintained.

work. The low volume/high cost software

be that mainly supplied to the

data processing market place. The relatively low volumes involved

high prices. Because of such prices the user will

There are however some potential dangers

in the exploitation of the

on the present generation of microprocessors is

rather primitive, mainly at assembler or

uncommon for such a user to outlay 5

further back-up equipment.

or 10 times the cost of the

Even then the software development

human activity. Furthermore the advent of the

microprocessor to be followed within 2 years by the 32-bit system will render

where user development

no one should underestimate the

my view that the new computing environment will consist of a hierarchy

of computing systems connected together via a network. Exactly

a particular place will depend more on the Post

Office networking charges than microprocessor costs.

Any shift in tariffs will

result in a shift in dispersion. In this view of the future, computing centres,

networks, and personal computers

and a widening of the community of people for whom the applications of

only can he use extra storage at

considering carefully the essential design characteristics of sympathetic

fail in this objective,

the anticipated rapid expansion of

computing into new areas may not take

The potential of the microprocessor is now universally recognized. However