40 Ei 4p2-Lic Lab Manual

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*
CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

Rf
10k
R1
+Vcc
4.7k
OU
T
LM741
Vi
3
4
CRO
-Vcc
Vo
CIRCUIT DIAGRAM OF NON-INVERTING AMPLIFIER:
RF
10k
R1
+Vcc
1
4.7k
OUT
LM741
Vi
/*KSRCT DEPARTMENT OF EIE*/
-Vcc
CRO
Vo
DESIGN OF
INVERTING, NON-INVERTING AMPLIFIER USING OP-AMP
Ex. No:
DATE:
AIM:
To design, construct and test an Inverting Amplifier for a given gain.

To design, construct and test a Non Inverting Amplifier for a given gain.
To measure CMRR of the differential Amplifier
APPARATUS REQUIRED:
S.No
Name of the Apparatus
Range
Quantity
1.
Function Generator
3 MHz
2.
CRO
30 MHz
3.
Dual RPS
0 30 V
4.
Op-Amp
IC 741
5.
Bread Board
6.
Resistors
1
Based on Design
Each 1
THEORY:
INVERTING AMPLIFIER:
The input signal Vi is applied to the inverting input terminal through R 1 and the non-inverting input
terminal of the op-amp is grounded. The output voltage V o is fed back to the inverting input terminal through
the Rf - R1 network, where R f is the feedback resistor. The output voltage is given as,
Vo = - ACL Vi
Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal.
NON INVERTING AMPLIFIER:
The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies
the signal without inverting the input signal. It is also called negative feedback system since the output is
feedback to the inverting input terminals. The differential voltage V d at the inverting input terminal of the opamp is zero ideally and the output voltage is given as,
Vo = ACL Vi Here the output voltage is in phase with the input signal
CIRCUIT DIAGRAM OF COMMON MODE CONFIGURATION:
CIRCUIT DIAGRAM OF DIFFERENTIAL MODE CONFIGURATION:
DESIGN:
DESIGN OF AN INVERTING AMPLIFIER WITH CLOSED LOOP GAIN - 2:
We know for an inverting Amplifier ACL = -RF / R1
ACL = -RF / R1 = 2
RF=2 R1
Choose
R1=4.7k
Then
RF=2x4.7k=9.4k
RF 10k
DESIGN A NON-INVERTING AMPLIFIER WITH CLOSED LOOP GAIN - 3:

We know for a Non-inverting Amplifier ACL = 1 + RF / R1
ACL = 1 + RF / R1 =3
RF=2 R1
Choose
R1=4.7k
Then
RF=2x4.7k =9.4k
RF 10k
CALCULATION:
In general, gain can be calculated by using the formula A= Adm/Acm
CMRR = Adm /Acm
Adm (Differential Mode Gain) = V02 Vin
Acm (Common Mode Gain)
= V01 Vin
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
PIN DIAGRAM OF OP-AMP:
TABULATION:
Input
Output
GAIN
S.No.
Amplitude
Time period
Amplitude
Time period
( No. of div x
Volts per div )
(No. of div x
Time per div )
( No. of div x
Volts per div )
(No. of div x
Time per div )
ACL = -RF / R1
1.
2.
NON-INVERTING AMPLIFIER:
Input
Output
GAIN
S.No.
Amplitude
Time period
Amplitude
Time period
( No. of div x
Volts per div )
(No. of div x
Time per div )
( No. of div x
Volts per div )
(No. of div x
Time per div )
ACL= 1+(-RF/ R1)
1.
2.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is
applied to the inverting input terminal of the Op- Amp for inverting amplifier and to non inverting
terminal for non inverting amplifier.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a
graph sheet. Then the gain is calculated from the output and verified with designed gain.
5. Calculate the CMRR value of the differential amplifier in common mode and differential mode. CMRR
is expressed in db and for higher value of CMRR op amp is better.
6. Then the gain is calculated from the output and verified with designed gain.
MODEL CALCULATION:
NON-INVERTING AMPLFIER:
MODEL GRAPH:
Non-Inverting amp
Vin
Inverting amp
Vin
(V)
(V)
t(sec)
t(sec)
Vo
(V)
Vo
(V)
t(sec)
t(sec)
VIVA QUESTIONS:
1. What are the casues for offset voltage, offset current and bias current?
2. What are the assumptions made in delivering the closed loop gain of the amplifier circuits?
3. What is the negative feedback system?
4. What is the order of the input impedance of the non-inverting amplifier?
5. What is the output offset voltage?
6. How the offset voltage is reduced to zero in case of 741 Op amp?
7. What is the difference between DC voltage follower and AC voltage follower?
8. Explain the application of a differential amplifier for instrumentation and control applications?
9. What are the casues for offset voltage, offset current and bias current?
11. How the offset voltage is reduced to zero in case of 741 Op amp?
12. What are the ideal characteristics of op-amp?
13. What are the popular IC packages available in op amp?
14. The negative sign in the output voltage of the inverting amplifier indicates what?
15. Define CMMR.
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
Calculation / Graphs
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
Signature of faculty
CIRCUIT DIAGRAM OF NON-INVERITNG SUMMER:

Rf
+Vcc
OUT
LM741
Va
V1
R2
-Vcc
V2
CRO
Vo
R3
V3
DESIGN OF AN NON-INVERTING SUMMER:
V1 Va
V2 Va
V3 Va
R1
R2
R3
VO
(1
Rf
R
When R1= R2= R3= R= Rf/2

V0= V1+V2+V3
TABULATION:
S.No
V1(volts)
V2(volts)
V3(volts)
Designed Output
Voltage
V0=
V1+V2 +V3(volts)
Obtained Output
Voltage
Vo=V1+V2+V3(volts)
Ex. No:
DESIGN OF ADDER,SUBTRACTOR,COMPARATOR & ZEROCROSSING

DETECTOR USING OP-AMP
DATE:
AIM:
To design, construct and test an Inverting and Non Inverting Summing Amplifier using op-amp.
To design, construct and test a Subtractor using op-amp.
To design, construct and test an Inverting and non inverting comparator.
To design, construct and test a Zero Crossing Detector.
APPARATUS REQUIRED:
S.No
Range
Quantity
1.
CRO
30 MHz
2.
Dual RPS
0 30 V
3.
Op-Amp
IC741
4.
Bread Board
5.
Resistors
Based on design
As per requirement
6.
Multimeter
7.
Function Generator
3 MHz
9.
Single RPS
0-30 V
THEORY:
SUMMER:
Op-amp may be used to design a circuit whose output is the sum of several input signals. Such a circuit is
called a summing amplifier or a summer. For inverting summing amplifier the in[put voltages V 1,V2 and V3 are
given through the input resistance to the inverting terminal of the op-amp. The non inverting terminal is
connected to the ground through the compensating resistor. The output of the inverting summing amplifier is
given below if R1 = R2 = R3 = R
V0= - (V1+V2+V3 )
When R1= R2= R3= 3Rf
VO
V1 V2
3
V3
10
CIRCUIT DIAGRAM OF INVERITNG SUMMER:

Rf
R1
V1
R2
V2
+Vcc
1
R3
Va
OUT
LM741
V3
-Vcc
4
RCOMP = R1 || R2|| R3 || R4
CRO
Vo
DESIGN OF AN INVERTING SUMMER:
V1
R1
V3
R3
V2
R2
Vo
Rf
When R1= R2= R3= 3Rf

VO
V1
V2
3
V3
TABULATION:
Designed Output
Voltage
S.No
V1(volts)
V2(volts)
V3(volts)
V0=
V1+V2 +V3(volts)
Obtained Output
Voltage
Vo=V1+V2+V3(volts)
11
For non inverting amplifier the input voltages are applied to the non inverting terminal of the op-amp.the
output is the sum of the input voltages.
When R1= R2= R3= R= Rf/2,
V0= V1+V2+V3
SUBTRACTOR:
A basic differential amplifier can be used as a subtractor. One of the input voltage is given to the
inverting terminal of the op-amp and other input is given to the non-inverting terminal of op-amp. The output
voltage is the difference between the two input voltages. If the input voltages are V 1 and V2 means the output
voltage is given as
V0= V1- V2
NON INVERTERING COMPARATOR:
A fixed reference voltage Vref is applied to the inverting (-) input terminal and sinusoidal signal uin is
applied to the non-inverting (+) input terminal. When vin exceeds Vref the output voltage goes to positive
saturation because the voltage at the (-) input is smaller than at the (+) input. On the other hand, when vin is less
than Vref the output voltage goes to negative saturation. Thus output voltage Vout changes from one saturation
level to another whenever vin = Vref ,.as illustrated in figure. In short, the comparator is a type of an analog-todigital converter (ADC). At any given time the output voltage waveform shows whether vin is greater or less
than Vref. The comparator is sometimes referred to as a volt-level detector because for a desired value of V ref,
the voltage level of the input voltage vin can be detected.
Diodes D1 and D2 are provided in the circuit to protect the op-amp against damage due to excessive
input voltage. Because of these diodes, the differential input voltage vd is clamped to either + 0.7 V or -0.7 V,
hence the diodes are called clamp diodes. There are some op-amps with built-in input protection. Such op-amps
need not to be provided with protection diodes. The resistance R1 in series with vin is used to limit the current
through protection diodes D1 and D2 while resistance R is connected between the inverting (-) input terminal
and Vref to reduce the offset problem.
When the reference voltage Vref is negative with respect to ground, with a sinusoidal signal applied to
the non-inverting input terminal, the output voltage will be as illustrated in figure. Obviously, the amplitude of
vin must be large enough to pass through Vref for switching action to take place. Since the sinusoidal input signal
is applied to the non-inverting terminal, this circuit is called the non-inverting op-amp comparator.
12
CIRCUIT DIAGRAM OF SUBTRACTOR:

R
R
V2
+Vcc
1
Va
OUT
LM741
R
V1
3
4
-Vcc
CRO
Vo
DESIGN OF SUBTRACTOR:
By using superposition principal,
To find the output V01 due to V1 alone, make V2 =0
V01
V1
R
(1
) V1
2
R
Similarly the output V02 due to V2 alone,

V02= -V2, Thus, V0= V01+ V02 = V1- V2
TABULATION:
Sl.No
V1(volts)
V2(volts)
Designed Output
Voltage
V0= V1 - V2 (volts)
Obtained Output Voltage

V0= V1 - V2 (volts)
13
INVERTING COMPARATOR:
In an inverting op-amp comparator the sinusoidal input is applied to the inverting (-) input terminal to
the op-amp. The circuit for an inverting comparator in which the sinusoidal input signals vin is applied to the
inverting (-) input terminal while the reference voltage V ref is applied to the non-inverting (+) input terminal
show in figure. In this circuit Vref is obtained by the use of a potentiometer forming a potential divider
arrangement with dc supply voltage + Vcc and VEE. As the wiper connected to (+) terminal is moved toward +
Vcc, Vref becomes more positive, while if it is moved toward VEE, Vrefbecomes more negative. Comparators
are used in circuits such as discriminators, voltage level detectors, oscillators, digital interfacing, Schmitt trigger
etc.
ZERO CROSSING DETECTOR:
It is an applied form of comparator. The zero-crossing detector provided the reference voltage V ref is
made zero.The output voltage waveform indicates when and in what direction an input signal Vincrosses zero
volt. In some applications the input signal may be low frequency one (i.e. input may be a slowly changing
waveform). In such a case output voltage V OUT may not switch quickly from one saturation state to the other.
Because of the noise at the input terminals of the op-amp, there may be fluctuation in output voltage between
two saturation states (+ Vsat and Vsatvoltages). Thus zero crossings may be detected for noise voltages as well
as input signal vin. Both of these problems can be overcome, if we use regenerative or positive feeding causing
the output voltage vout to change faster and eliminating the false output transitions that may be caused due to
noise at the input of the op-amp.
14
CIRCUIT DIAGRAM OF NON-INVERITNG& INVERITNG COMPARATOR:
OUTPUT WAVEFORMS OF NON INVERTING COMPARATOR:
OUTPUT WAVEFORMS OF INVERTING COMPARATOR:
15
PROCEDURE:
ADDER & SUBTRACTOR:
1. Connections are given as per the circuit diagram for adder.
2. Apply the input voltage to the corresponding resistors
graph sheet. Repeat the above to get the different value of input voltage Same procedure can be adopted
to Subtractor but the output is the difference of input voltages
COMPARATOR:
applied to the corresponding terminals of Op-Amp.
4. Reference voltage to the comparator is fed with the single RPS.
5. The output waveform is obtained in the CRO and the input and output voltage waveforms are plotted in
a graph sheet. Then the gain is calculated from the output and verified with designed gain.
ZERO CROSSING DETECTOR:
3. Connect the non inverting terminal of the op-amp to grount and switch on the dual RPS.
4. Observe the output wave form from the CRO and draw the input and output waveform.
16
CIRCUIT DIAGRAM OF ZERO CROSSING DETECTOR:
OUTPUT WAVEFORM OF ZERO CROSSING DETECTOR:
VIVA QUESTION:
1. What is comparator?
2. List the different types of comparator?
3. How the reference voltage to the comparator can be applied?
4. List out the application of comparator.
5. What is zero crossing detector?
6. What is a window detector?
7. What is meant by regenerative comparator?
8. Define upper threshold voltage and lower threshold voltage in Schmitt trigger.
9. Define the term Gain of an op amp.
10. Explain how to measure the phase angle between two voltages.
11. Give the characteristics of an ideal op-amp:
12. How a non-inverting amplifier can be courted into voltage follower?
13. What is the necessity of negative feedback?
14. What are 4 building blocks of an op-amp?
15. What is the purpose of shunting C facross Rf and connecting R1 in series with the input signal?
17
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
18
CIRCUIT DIAGRAM OF DIFFERENTIATOR:
CIRCUIT DIAGRAM OF INTEGRATOR:
19
Ex. No:
DESIGN OF DIFFERENTIATOR & INTEGRATOR USING OP-AMP
DATE:
AIM:
To design and test a Differentiator circuit for the given operating frequency using op-Amp IC 741.
To design an Integrator circuit for the given operating frequency using op-Amp IC 741.
APPARATUS REQUIRED:
S.No
Range
Quantity
1.
Function Generator
3 MHz
2.
CRO
30 MHz
3.
Dual RPS
0 30 V
4.
Op-Amp
IC 741
5.
Bread Board
6.
Resistors
Based on Design
Each 1
7.
Capacitors
0.55nF,0.01uF
Each1
THEORY:
DIFFERENTIATOR:
The differentiator circuit performs the mathematical operation of differentiation: that is, the output
waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting
amplifier if an input resistor R1 is replaced by a capacitor C1. The expression for the output voltage is given as,
Vo = - Rf C1 (d Vi /dt)
Here the negative sign indicates that the output voltage is 180
out of phase with the input signal. A
resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for
the input bias current. A workable differentiator can be designed by implementing the following steps:
1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of
C1< 1 F, calculate the value of Rf.
2. Choose fb= 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.
20
PIN DIAGRAM:
TABULATION:
DIFFERENTIATOR:
S.No
Measurements
Input
Output
Input
Output
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )
3.
Calculated Frequency
INTEGRATOR:
S.No
Measurements
Amplitude
1.
Time period
2.
3.
21
The differentiator is most commonly used in wave shaping circuits to detect high frequency components
in an input signal and also as a rateofchange detector in FM modulators.
INTEGRATOR:
A circuit in which the output voltage waveform is the integral of the input voltage waveform is the
integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor
Rf is replaced by a capacitor Cf. The expression for the output voltage is given as,
Vo = - (1/Rf C1) Vi dt
Here the negative sign indicates that the output voltage is 180
out of phase with the input signal.
Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < f b. The input signal
will be integrated properly if the Time period T of the signal is larger than or equal to R f Cf. That is,
T R f Cf
The integrator is most commonly used in analog computers and ADC and signal-wave
DESIGN:
DIFFERENTIATOR:
To design a differentiator circuit to differentiate an input signal that varies in frequency from 10 Hz to
about 1 KHz, a sine wave of 1 V peak at 1000Hz is applied to the differentiator, draw its output waveform.
Given fa = 1 KHz
We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf C1)
Let us assume C1 = 0.01 F:
Then
Rf = 15.9k , since fb = 20 fa, fb = 20 KHz
We know that the gain limiting frequency fb = 1 / (2 R1 C1)
Hence R1 = 820 ,
Since R1C1 = Rf Cf =0.55Nf
22
MODEL GRAPH:
INTEGRATOR:
Vin
Model graph
t
t
Vo
t
t
DIFFERENTIATOR:
Model graph
Vin
Vin
IV
Model graph
IV
t
-IV
-IV
2V
Vo
Vo
t
t
-2V
23
INTEGRATOR:
To obtain the output of an Integrator circuit with component values
Rf Cf = 0.335ms, Rf = 10 R1 and Cf = 0.01 F
and also if 1 V peak square wave at 1500Hz is applied as input.
We know the frequency at which the gain is 0 dB, fb = 1 / (2 R1Cf)
Therefore fb = 10 fa
Since fb = 10 fa, and also the gain limiting frequency fa = 1 / (2 Rf Cf)
We get,
R1 = 3.3k
and hence Rf = 33k
PROCEDURE:
applied to the inverting input terminal of the Op-Amp.
graph sheet.
24
VIVA QUESTIONS:
1. How the differentiation can be performed in op amp circuits?
2. What are the applications of integrator and differentiator?
3. What is an inverting integrator?
4. What are the limitations of basic differentiator and integrator?
5. Write down the input and output relation for the differentiator and integrator?
6. Derive the design equations of the differentiator and integrator?
7. Why integrators are preferred over differentiator in analog computer?
8. What are the frequency compensation techniques available in op amp?
9. What are the applications of Differentiator?
10. What do you mean by unity gain bandwidth?
11. What did you observe at the output when the signal frequency is increased above fa?
12. How would you eliminate the high frequency noise in integrator?
13. What are the main applications of the Integrator?
14. Is it possible to design an analog computer using integrator and differentiator?
15. What happens to the output of integrator when input signal frequency goes below fa?
25
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
26
CIRCUIT DIAGRAM ACTIVE CLIPPER:
MODEL GRAPH:
TABULATION:
ACTIVE CLIPPER:
S.No
Measurements
Input
Output
Amplitude
1.
Time period
2.
3.
27
/* 40 EI 4P2- Linear Integrated Circuits Laboratory*/
Ex. No:
DESIGN OF CLIPPER AND CLAMPER CIRCUITS USING OP-AMP
DATE:
AIM:
To design and test the operation of active diode (precisions circuits) with the help of clipper and
clamper circuits using Op-Amp.
APPARATUS REQUIRED:
S.No
1.

IC 741
Range
--
Quantity
1
2.
Resistors
1k,2.2k,4.7k
3.
Capacitors
0.1 F,0.01 F
4.
Diode
IN4001
5.
CRO
--
6.
Power supply
15 V,(0-30) V
7.
Probe
--
8.
Bread Board
--
THEORY:
ACTIVE CLIPPER:
Clipper is a circuit that is used to clip off (remove) a certain portion of the input signal to obtain a
desired output wave shape. In op-amp clipper circuits, a rectified diode may be used to clip off certain parts of
the input signal. The figure shows an active positive clipper, a circuit that removes positive parts of the input
signal. The clipping level is determined by the reference voltage Vref. With the wiper all the way to the left,
Vref is o and the non-inverting input is grounded. When Vin goes positive, the error voltage drives the op-amp
output negative and turns on the diode. This means the final output VO is 0 (same as Vref) for any positive
value of Vin. When Vin goes negative, the op-amp output is positive, which turns off the diode and opens the
loop. When this happens, the final output VO is free to follow the negative half cycle of the input voltage. This
is why the negative half cycle appears at the output. To change the clipping level, all we do is adjust Vref as
needed.
ACTIVE CLAMPER:
In clamper circuits, a predetermined dc level is added to the input voltage. In other words, the output is
clamped to a desired dc level. If the clamped dc level is positive, the clamper is called a positive clamper. On
the other hand, if the clamped dc level is negative, it is called a negative clamper. The other equivalent terms for
/*KSRCT-DEPARTMENT OF EIE*/
28
CIRCUIT DIAGRAM ACTIVE CLAMPER:
MODEL GRAPH:
Input put Waveforms of Clamper for Different V REF

TABULATION:
ACTIVE CLAMPER:
S.No
Measurements
Input
Output
Amplitude
1.
Time period
2.
3.
29
clamper are dc inserter or dc restorer. A clamper circuit with a variable dc level is shown in figure. Here the
input wave form is clamped at +Vref and hence the circuit is called a positive clamper.
The output voltage of the clamper is a net result of ac and dc input voltages applied to the inverting and
non-inverting input terminals respectively. Therefore, to understand the circuit operation, each input must be
considered separately. First, consider Vref at the non-inverting input. Since this voltage is positive, is +VO is
positive, which forward biases diode D 1. This closes the feedback loop and the op-amp operates as a voltage
follower. This is possible because C1 is an open circuit for dc voltage. Therefore VO = Vref. As for as voltage Vin
at the inverting input is concerned during its negative half-cycle D1 conducts, charging C1 to the negative peak
value of the VP. However, during the positive half-cycle of Vin diode D1 is reverse biased and hence the voltage
VP across the capacitor acquired during the negative half-cycle is retained. Since this voltage V P is in series with
the positive peak voltage VP, the output peak voltage VO=2VP. Thus the net output is Vref+ VP, so the negative
peak of 2VP is at Vref. For precision clamping C 1Rd<<T/2, where Rd is the forward resistance of the diode D1
(100 typically) and T is the time period of Vin. The input and output wave forms are shown in figure.
Resistor R is used to protect the op-amp against excessive discharge currents from capacitor C 1
especially when the dc supply voltages are switched off. Negative clamping at a negative voltage is
accomplished by reversing diode D 1 and using the negative reference voltage Vref as shown in figure.
PROCEDURE:
ACTIVE CLIPPER:
1. Assemble the clipping circuit as shown in figure with R=2.2k. Use IN4002 diode.
2. Feed 3VP, 1 KHz sinusoidal input. Observe the input and output voltages on a CRO.
3. Look at the output signal while turning the potentiometer through its entire range.
4. Record your readings in table for a desired clipping level. Plot the input and output voltages on the
same scale.
ACTIVE CLAMPER:
1. Design a positive clamping circuit with clamping level at zero as shown in figure.
2. Note that Vref = 0V. Consider C1 = 0.1F, R = 4.7 K and RL = 10 K. Use IN4002 diode.
3. Assemble the circuit.
4. Feed 5VPP, 10 KHz sinusoidal input.
5. Using a CRO observe the input and output voltages simultaneously.
6. Determine the clamping levels of the output voltage. Tabulate your readings in table.
7. Plot the input and output voltages on the same scale.
30
VIVA QUESTIONS:
1. The clipper circuit can be called go-no go detector. Explain why it is called so?
2. In the Clipper circuit, if the POT is adjusted for Vref = -1V, what would be the output?
3. Set Vref = 0V in the clipper circuit and observe the output waveform and record your comments.
4. If the diode is reversed in the clipper circuit what would the output voltage be?
5. If the diode is reversed in clamper circuit what would the output be like?
6. State the difference between active and passive clippers.
7. List the advantages of clipper circuits.
8. Why the clamper circuit is called as DC Restorer?
9. Define CMRR.
10. Mention the non-linear applications of Op-Amp.
11. List the linear applications of Op-Amp.
12. Define Slew rate.
13. Infer the effects of slew rate in linear and non-linear applications.
14. Define Duty Cycle.
15. Define Time period and Frequency.
31
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
32
CIRCUIT DIAGRAM OF INSTRUMENTATION AMPLIFIER
INPUT POWER SUPPLY DESIGN:
33
Ex. No:
DESIGN OF INSTRUMENTATION AMPLIFIER USING OP-AMP
DATE:
AIM:
To design and analyse the performance characteristics of instrumentation amplifier for the specified
gain value using op-Amp.
APPARATUS REQUIRED:
S.No
Range
Quantity
1.
Dual RPS
0 30 V
2 Nos
2.
Op-Amp
IC 741
3 Nos
3.
Bread Board
1 No
4.
Resistors
5.
Decade Resistance Box
1 K ,100 K , 120 K ,10K

-
4 Nos
1 Nos
THEORY:
An instrumentation amplifier is typically the first stage in an instrumentation system. It is used to
amplify the signal produced by a transducer such as a thermocouple or a strain gauge. An instrumentation
amplifier is a difference amplifier i.e., it amplifies the voltage difference between its two input terminals,
neither of which is required to be a signal ground. An instrumentation amplifier should have the following
characteristics: high input resistance, high voltage gain, and high common-mode-rejection-ratio (CMRR).
The instrumentation amplifier depicted in Figure does not suffer from the disadvantages listed
above; it has high input resistance and high CMRR. It is clear from the circuit diagram that the input
resistance seen by the source is governed by the input resistance of the op-amps used in the circuit. The
input resistance of the instrumentation amplifier is thus very high.
The instrumentation amplifier consists of an input stage followed by a second stage (which is just a
basic difference amplifier). It is easily shown that the differential voltage gain of the first stage is (1 +
2R2/R1). We know that the differential gain of the second stage is R4/R3. The overall differential gain of the
instrumentation amplifier is thus
It is easily shown that the common-mode voltage gain of the first stage is unity. We know that the
common mode gain of the second stage is R4/ (R3 CMRRo). The overall common-mode gain of the
instrumentation amplifier is thus
34
PRACTICAL CIRCUIT OF INSTRUMENTATION AMPLIFIER:
TABULATION:
S.No.
THEORATICAL VALUE
GAIN
V1 (mV)
V2(mV)
V1-V2
Vout (mV)
PRACTICAL VALUE
GAIN = Vout/(V1-V2)
35
The above two gives the CMRR of the instrumentation amplifier. We have
The CMRR of the instrumentation amplifier is thus greater than that of the op-amps by a factor (1 +
2R2/R1) which can be large. In fact, if we set R4 = R3, we see from Eq. 2-12 that this multiplying factor is the
(large) differential voltage gain of the instrumentation amplifier. In a number of instrumentation and consumer
applications one is required to measure and control the physical quantities. Some typical examples are
measurement and control of temperature, humidity, light, Intensity, water flow etc. These physical quantities are
usually measured with the help of transducer. The output of the transducer has to be amplified so that it can
derive the indicator or display system. The functions performed by an instrumentation amplifier are,
High gain accuracy.
High CMRR.
High gain stability with low temperature coefficient.
Low dc offset.
Low input impedance.
These are specially designed op-amp such as VA725 to meet the above started requirement of a good
instrumentation amplifier. Monolithic instrumentation amplifiers are also available commercially such as
AD521, AD524, and AD624 by analog devices L40036, and L40037 by national semiconductors.
DESIGN:
V01= (1+R2/R1) V1 (R2/R1) V2,
V02 = (1+R2/R1) V2 (R2/R1) V1
V0 = V02 V01
= (V2V1) (1+2R2/R1),
Gain = Vo/Vi
=> Vo / (V2V1)
=> (1+2R2/R1
PROCEDURE:
1. Circuit connections are given as per the experimental setup.
2. The input signal is given.
3. The dual power supply is switched ON.
4. The input is varied in steps and the corresponding output readings are noted from CRO.
5. The practical gain is calculated from the readings
36
MODEL GRPAH:
VIVA - QUESTIONS:
1. What is the negative feedback system?
2. What is the order of the input impedance of the non-inverting amplifier?
4. Define the term Gain of an op amp.
5. What is the necessity of negative feedback?
6. What are 4 building blocks of an op-amp?
7. What is the purpose of shunting Cf across Rf and connecting R1 in series with the input signal?
8. Mention any two specifications of a DAC.
9. Name any two types of ADC.
10. Define duty cycle ratio.
11. What is meant by quasi stable state?
12. How an Op-amp is used to generate square wave?
13. What are the changes to be done in a symmetric square wave generator to generate asymmetric square
wave?
14. Write down the design equations of duty cycle and frequency of oscillations for astable circuit.
15. Mention the merits of Instrumentation Amplifier.
37
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
38
CIRCUIT DIAGRAM:
LOW PASS FILTER:
MODEL GRAPH:
39
Ex. No:
DESIGN OF FILTER CIRCUITS USING OP-AMP
DATE:
AIM:
To design and test the operation of active filters (Low Pass, High Pass) with the help of Op-Amp.
APPARATUS REQUIRED:
S.No.
1.

IC 741
Range
--
Quantity
2
2.
Resistors
1.6K,10K,5.86K
As per the need
3.
Capacitors
0.1 F
5.
CRO
--
6.
Power supply
15 V,(0-30) V
7.
Probe
--
8.
Bread Board
--
THEORY:
LOW PASS FILTER:
An active filter generally uses an operational amplifier (op-amp) within its design and in the Operational
Amplifier tutorial we saw that an Op-amp has high input impedance, low output impedance and a voltage gain
determined by the resistor network within its feedback loop.
Unlike a passive high pass filter which has in theory an infinite high frequency response, the maximum
frequency response of an active filter is limited to the Gain/Bandwidth product (or open loop gain) of the
operational amplifier being used. Still, active filters are generally much easier to design than passive filters, they
produce good performance characteristics, very good accuracy with a steep roll-off and low noise when used
with a good circuit design. This second order low pass filter circuit has two RC networks, R1 C1 and R2 C2
which give the filter its frequency response properties. The filter design is based around a non-inverting op-amp
configuration so the filters gain, A will always be greater than 1. Also the op-amp has a high input impedance
which means that it can be easily cascaded with other active filter circuits to give more complex filter designs.
The normalized frequency response of the second order low pass filter is fixed by the RC network and is
generally identical to that of the first order type. The main difference between a 1st and 2nd order low pass filter
is that the stop band roll-off will be twice the 1st order filters at 40dB/decade (12dB/octave) as the operating
frequency increases above the cut-off frequency c, point as shown.
40
HIGH PASS FILTER:
MODEL GRAPH:
41
DESIGN:
LPF:
The gain magnitude equation of the Low Pass filter can be obtained by converting equation into its
equivalent polar form, as follows. | Vo / Vin | = AF/1+ (f / fl)4
Where
fH =
=> cut-off frequency of the filter
The operation of the low pass filter can be verified from the gain magnitude equation. 1. At very low
frequencies, that is
1. f < fH | Vo/Vin | = AF
2. At f = fH, | Vo/Vin | = AF/2 = 0.707 AF
3. At f > fH | Vo/Vin | < AF
1. Choose a value for the high cut-off frequency, fH(1 KHz).
2. To simplify the design calculations, set R2=R3=R and C2=C3=C. Then choose a value of C1F
(0.0047 F).
3. Calculate the value of R using the equation R=1/2frC.
4. Finally, because of the equal resistor (R2=R3) and capacitor (C2=C3) values, the pass band voltage
gain AF = (1+) of the second-order low-pass filter has to be equal to 1.586.That is, Rf = 0.586R1. This
gain is necessary to generate Butterworth response. Hence choose a value of R1100K (33 K) and
calculate the value of Rf.
HIGH PASS FILTER:
The basic electrical operation of an Active High Pass Filter (HPF) is exactly the same as we saw for its
equivalent RC passive high pass filter circuit, except this time the circuit has an operational amplifier or op-amp
included within its filter design providing amplification and gain control.Like the previous active low pass filter
circuit, the simplest form of an active high pass filter is to connect a standard inverting or non-inverting
operational amplifier to the basic RC high pass passive filter circuit as shown.
Second Order High Pass Filter consists of RC networks for filtering. Second Order High Pass filter can
be constructed from a Second Order Low Pass filter simply by interchanging frequency determining
components R & C . Op-Amp is used in the non inverting configuration. Resistor R1 and RF determine the
gain of the Filter.
A first-order high pass active filter can be converted into a second-order high pass filter simply by using
an additional RC network in the input path. The frequency response of the second-order high pass filter is
identical to that of the first-order type except that the stop band roll-off will be twice the first-order filters at
40dB/decade (12dB/octave). Therefore, the design steps required of the second-order active high pass filter are
the same. Higher-order High Pass Active Filters, such as third, fourth, fifth, etc are formed simply by cascading
42
TABULATION:
LOW PASS FILTER:
Vin = 1V
S.NO.
Input Frequency
f(Hz)
Output Voltage Vo(v)
Gain Magnitude
Gain in dB
|Vo/Vin|
20 log |Vo/Vin|
43
together first and second-order filters. For example, a third order high pass filter is formed by cascading in
series first and second order filters, a fourth-order high pass filter by cascading two second-order filters together
and so on.
HPF:
The gain magnitude equation of the Low Pass filter can be obtained by converting equation into its
equivalent polar form, as follows. | Vo / Vin | = AF/1+ (f/fl) 4
Where
fH =
=> cut-off frequency of the filter
The operation of the low pass filter can be verified from the gain magnitude equation. 1. At very low
frequencies, that is
1. f < fH | Vo/Vin | = AF
2. At f = fH, | Vo/Vin | = AF/2 = 0.707 AF
3. At f > fH | Vo/Vin | < AF
1. Choose a value for the high cut-off frequency, fH(1 KHz).
2. To simplify the design calculations, set R2=R3=R and C2=C3=C. Then choose a value of C1F
(0.0047 F).
3. Calculate the value of R using the equation R=1/2frC.
4. Finally, because of the equal resistor (R2=R3) and capacitor (C2=C3) values, the pass band voltage
gain AF = (1+) of the second-order low-pass filter has to be equal to 1.586.That is, Rf = 0.586R1.
This gain is necessary to generate Butterworth response. Hence choose a value of R1100K (33
K) and calculate the value of Rf.
PROCEDURE:
LOW PASS FILTER:
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Connect channel -1 of CRO to input terminals (Vin) and channel -2 to output terminals (Vo).
4. Set Vin = 1V & fin=10Hz using function generator.
5. By varying the input frequency in regular intervals, note down the output voltage.
6. Calculate the gain (Vo/Vin) and Gain in dB = 20 log (Vo/Vin) at every frequency.
7. Plot the frequency response curve (taking frequency on X-axis & Gain in dB on Y-axis) using Semi log
Graph.
8. Find out the high cut-off frequency, fH (at Gain= Constant Gain, Af 3 dB) from the frequency
response plotted.
9. Verify the practical (fH from graph) and the calculated theoretical cut-off frequency (fH = 1/2RC).
44
TABULATION:
HIGH PASS FILTER:
Vin = 1V
S.NO.
Input Frequency
f(Hz)
Output Voltage Vo(v)
Gain Magnitude
Gain in dB
|Vo/Vin|
20 log |Vo/Vin|
45
HIGH PASS FILTER:

1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Connect channel -1 of CRO to input terminals (Vin) and channel -2 to output terminals (Vo).
4. Set Vin = 1V & fin=10Hz using function generator.
5. By varying the input frequency in regular intervals, note down the output voltage.
6. Calculate the gain (Vo/Vin) and Gain in dB = 20 log (Vo/Vin) at every frequency.
7. Plot the frequency response curve (taking frequency on X-axis & Gain in dB on Y-axis) using Semi log
Graph.
8. Find out the low cut-off frequency, fL (at Gain= Constant Gain, Af 3 dB) from the frequency response
plotted.
9. Verify the practical (fL from graph) and the calculated theoretical cut-off frequency (fL = 1/2RC).
46
VIVA-QUESTIONS:
1. How filters are classified? Give one example for each classification.
2. What is an active filter and why it is called so?
3. How an active filter differs from a passive filter?
4. What are the advantages of active filters over passive filters?
5. Draw the circuit diagrams of active filters LPF and HPF.
6. Draw the frequency response of all filters (LPF, HPF, BPF, BRF and All-pass).
7. What is the gain roll off rate for a 1st order and 2nd order filter?
8. What is the formula for cut-off frequency?
9. What is a 3 dB frequency and why it is called so?
10. What are the other names for 3 dB frequency?
11. Define UGB.
12. Why 3dB line is used to determine the bandwidth of the device.
13. Mention the merits of active filters.
14. Define magnitude and phase of filter.
15. List the demerits of active filter.
47
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
48
CIRCUIT DIAGRAM:
RC PHASE SHIFT OSCILLATOR:
MODEL GRAPH:
sine wave
amplitude
1
0.5
0
-0.5
-1
0.5
1.5
2.5
time
3.5
4.5
49
Ex. No:
DESIGN OF OSCILLATOR CIRCUITS USING OP-AMP
DATE:
AIM:
To design and test the functioning of RC phase shift and Wien Bridge Oscillator circuit with the help of
Op-Amp.
APPARATUS REQUIRED:
S.No.
1.

IC 741
Range
--
Quantity
2
2.
Resistors
1k,1.2k,50k,4.7k,1,5k
As per the need
3.
Capacitors
0.1 F,o.001 F
As Per the need
5.
CRO
--
6.
Power supply
15 V,(0-30) V
7.
Probe
--
8.
Bread Board
--
THEORY:
RC phase shift oscillator is a sinusoidal oscillator used to produce sustained well shaped sine wave
oscillations. It is used for different applications such as local oscillator for synchronous receivers, musical
instruments, study purposes etc. The main part of an RC phase shift oscillator is an op amp inverting amplifier
with its output fed back into its input using a regenerative feedback RC filter network, hence the name RC
phase shift oscillator.
By varying the capacitor, the frequency of oscillations can be varied. The feedback RC network has a
phase shift of 60 degrees each, hence total phase shift provided by the three RC network is 180 degrees. The op
amp is connected as inverting amplifier hence the total phase shift around the loop will be 360 degrees. This
condition is essential for sustained oscillations. We have already discussed about RC phase shift oscillator using
transistor.
The feedback network offers 180 degrees phase shift at the oscillation frequency and the op amp is
configured as an Inverting amplifier, it also provide 180 degrees phase shift. Hence to total phase shift around
the loop is 360=0degrees, it is essential for sustained oscillations. At the oscillation frequency each of the
resistor capacitor filter produces a phase shift of 60 so the whole filter circuit produces a phase shift of 180.
50
WEIN BEIDGE OSCILLATOR:
MODEL GRAPH:
sine wave
amplitude
1
0.5
0
-0.5
-1
0.5
1.5
2.5
time
3.5
4.5
51
The energy storage capacity of capacitor in this circuit produces a noise voltage which is similar to a
small sine wave, it is then amplified using op amp inverting amplifier.
By taking feedback, the output sine wave also attenuates 1/29 times while passing through the RC
network, so the gain of inverting amplifier should be 29 in order to keep loop gain as unity. The unity loop gain
and 360 degree phase shift are essential for the sustained oscillation. RC Oscillators are stable and provide a
well-shaped sine wave output with the frequency being proportional to 1/RC and therefore, a wider frequency
range is possible when using a variable capacitor. However, RC Oscillators are restricted to frequency
applications because at high frequency the reactance offered by the capacitor is very low so it acts as a short
circuit.
Number of RC stages help improve the frequency stability. The total phase shift introduced by the
feedback network is 180 degrees, if we are using N RC stages each RC section provide 180/N degree phase
shift. When 2 RC sections are cascaded, the frequency stability is low. For 3 sections cascaded the phase change
rate is high so there is improved frequency stability. However for 4 RC sections there is an good phase change
rate resulting in the most stable oscillator configuration. But 4 RC sections increases cost and makes circuit
complexity. Hence phase shift oscillators make use of 3 RC sections in which each section provides a phase
shift of 60 degree. The latter is generally used in high precision applications where cost is not much regarded
and only accuracy plays a major role.
WIEN BRIDGE OSCILLATOR:
Wien bridge oscillator is an audio frequency sine wave oscillator of high stability and simplicity. Before
that let us see what is oscillator? An oscillator is a circuit that produces periodic electric signals such as sine
wave or square wave. The application of oscillator includes sine wave generator, local oscillator for
synchronous receivers etc. Here we are discussing wein bridge oscillator using 741 op amp IC. It is a low
frequency oscillator. The op-amp used in this oscillator circuit is working as non-inverting amplifier mode.
Here the feedback network need not provide any phase shift. The circuit can be viewed as a wien bridge with a
series RC network in one arm and parallel RC network in the adjoining arm. Resistors Ri and Rf are connected
in the remaining two arms.
The feedback signal in this oscillator circuit is connected to the non-inverting input terminal so that the
op-amp works as a non-inverting amplifier. The condition of zero phase shift around the circuit is achieved by
balancing the bridge, zero phase shift is essential for sustained oscillations.
The frequency of oscillation is the resonant frequency of the balanced bridge and is given by the
expression fo = 1/2RC. At resonant frequency ( o), the inverting and non-inverting input voltages will be
equal and in-phase so that the negative feedback signal will be cancelled out by the positive feedback causing
the circuit to oscillate. From the analysis of the circuit, it can be seen that the feedback factor = 1/3 at the
frequency of oscillation. Therefore for sustained oscillation, the amplifier must have a gain of 3 so that the loop
52
TABULATION:
S.No
1.
2.
3.
Measurements
Practical
Theoretical
Practical
Theoretical
Amplitude
Time period
WEIN BRIDGE OSCILLATOR:

S.No
1.
2.
3.
Measurements
Amplitude
Time period
MODEL CALCULATION:
53
gain becomes unity. For an inverting amplifier the gain is set by the feedback resistor network Rf and Ri and is
given as the ratio -Rf/Ri.
DESIGN:
Frequency of oscillation (F):
Gain of the Op Amp inverting amplifier (G):
Attenuation offered by the feedback RC network is 1/29, so the gain of inverting amplifier should be 29
Use Ri=1.2 K
So, Rf=35K
Use 50K potentiometer and adjust its value to obtain output on CRO
WEIN BRIDGE OSCILLATOR:

The required frequency of oscillation fo=1 kHz
We have,
Take C=0.01F, then R=1.6k (Use 1.5k standard)

Gain of the amplifier section is given by,
Take Ri=1k, then Rf=2.2k (Use 4.7k Potentio meter for fine corrections)
54
VIVA-QUESTIONS:
1. Define Oscillator.
2. Mention the types of Oscillator.
3. State Barkhausen Criterion.
4. Infer the function of tank circuit.
5. How the Barkhausen criteria is satisfied with RC Phase shift Oscillator.
6. How the Barkhausen criteria is satisfied with Wien Bridge Oscillator.
7. Mention the requirements for producing sustained Oscillations.
8. List any two audio frequency oscillator.
9. Define Conversion time.
10. Define settling time.
11. Define stability.
12. How will you determine the stability of an Oscillator?
13. Mention the factors affecting sustained oscillations.
14. What are the problems associated with switch type phase detector.
15. Why do we need compensation in the feedback circuit.
55
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
56
CIRCUIT DIAGRAM:
4-BIT R/2R LADDER DAC:
DESIGN:
Output voltage, Vo
f b1
R R 21
b
2
22
b
3
23
b
4
24
Binary value=1000(given)
Output voltage=6v (given)
Reference resistor =10K
(given)
Reference Voltage, VR=10V (given)

Rf=12k
Resolution,
1 VR
2n R
1 10V
24 10k
V
12k
0.75
57
Ex. No:
DESIGN OF D-A AND A-D CONVERETER USING OP-AMP
DATE:
AIM:
To design R-2R ladder type and weighted resistor type DAC using op-amp.
To design and test a 4- bit Flash type A/D converter using op-amp.
APPARATUS REQUIRED:
S.No
Range
Quantity
1.
Dual RPS
0 - 30 V
2.
Op-Amp
IC 741
3.
Bread Board
,470
4.
Resistors
20K , 1K
10K
5.
DPDT(switch)
6.
Single RPS
0-30 V
7.
LED
THEORY:
In R-2R ladder type D to A converter, only two values of resistor is used (i.e. R and 2R). Hence it is
suitable for integrated circuit fabrication. The typical values of R are from 2.5K
to 10K . In this output
voltage is a weighted sum of digital inputs. Since the resistive ladder is a linear network, the principle of super
position can be used to find the total analog output voltage for a particular digital input by adding the output
voltages caused by the individual digital inputs.
Digital
systems
are
used
in
ever
more
applications,
because
of
their
increasingly
efficient, reliable, and economical operation with the development of the microprocessor, data
processing has become an integral part of various systems Data processing involves transfer
of data to and from the microcomputer via input/output devices.
Since digital systems such as
microcomputers use a binary system of ones and zeros, the data to be put into the microcomputer must be
converted
from
analog
to
digital
form.
On
the
other
hand,
digital-to-analog
converter is used when a binary output from a digital system must be converted to some
equivalent analog voltage or current.
The function of DAC is exactly opposite to that of an
ADC.
58
CIRCUIT DIAGRAM:
BINARY WEIGHTED RESISTOR DAC:
DESIGN:
I = I + I +.......+ In
1
0
2
V
V
V
I = R d + R d +...........+ nR dn
1
0
2
2
2R
2 R
2 R
V
-1
-2
-n
I = R (d 2 + d 2 +........+ dn 2 )
1
0
2
R
The output voltage,
R
f (d 2-1 + d 2-2 +........+ d 2-n )
V =I R =V
n
R R
1
0
0 f
2
TABULATION:
WEIGHTED RESISTOR:
S.No
Theoretical voltage (mv)
Practical Voltage (mv)
Theoretical voltage (mv)
Practical Voltage (mv)
R-2R LADDER:
S.No
59
A DAC in its simplest form uses an op-amp and either binary weighted resistors or R2R ladder resistors.
In binary-weighted resistor op-amp is connected in the inverting mode, it can also be
connected in the non-inverting mode.
Since the number of inputs used is four, the converter is called a 4-bit
binary digital converter.
A-D CONVERTER:
The analog to digital converter is normally required at the input of a digital system for the measurement
or control of analog quantities. In A/D converters, the input is an analog voltage and the output is a digital code.
A/D converters are more complex and time consuming than D/A converters.
A/D converters can be designed with or without the use of D/A converters as part of their circuitry. The
commonly used types of A/D converters incorporating D/A converters are (a) Successive- approximation
converter and (b) Counting or digital ramp converter.
PROCEDURE:
D-A CONVERTER:
3. The power supply is switched on.
4. Reference voltage is set as 10V.
5. Binary values are applied according to the binary input values.
6. The output voltage is noted down.
7. The output voltage obtained is compared with the given output voltage.
A-D CONVERTER:
1. Make the connections as per the circuit diagram
2. Switch on the power supply
3. The variable terminal of the potentiometer is given to the analog input channel 2.
4. To select the analog input channel 2, the channel select switch position is as follows
SW1
SW2
SW3
5. The Start of Conversion (SOC) button is pressed once to start the conversion.
60
CIRCUIT DIAGRAM:
A-D CONVERTER:
TABULATION:
S.No
Analog Input in (Volts)
B3
Digital Output
B2
B1
B0
61
6. The digital output for the corresponding analog input is displayed on LEDs D 0 throughD7.
7. The address latch enable (ALE) button is also pressed once, so as to enable the digital data to be sent
to the output
8. The End of Conversion (EOC) is indicated by the LED 10
9. The above procedure is repeated for different values of analog voltages.
62
MODEL GRAPH:
VIVA QUESTIONS:
1. Mention any two specifications of a DAC.
2. Name any two types of ADC.
3. In a binary ladder network of a DAC, the value of the smaller resistance is 10 k .What is the resistance
value of the other set?
4. What output voltage would be produced by a DAC whose output range is 0 to 10V and whose input binary
number is 10 (for a 2 bit DAC)?
5. What is the range value for resistor (R) in DAC?
6. What is meant by the word resolution in reference to an ADC or a DAC? Why is resolution important to us,
and how may it be calculated for any particular circuit knowing the number of binary bits?
7. The practical use of binary-weighted digital-to-analog converters is limited to:
8. The difference between analog voltage represented by two adjacent digital codes, or the analog step size is
__________
9. The primary disadvantage of the flash analog-to digital converter (ADC) is __________
10. A binary-weighted digital-to-analog converter has a feedback resistor, R f, of 12 k . If 50 A of current is
through the resistor, the voltage out of the circuit is:
11. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted
digital-to-analog DAC converter?
12. The resolution of a 05 V 6-bit digital-to-analog converter (DAC) is:
13. In a flash analog-to-digital converter, the output of each comparator is connected to an input of a:
14. Which is not an analog-to-digital (ADC) conversion error?
15. Sample-and-hold circuits in analog-to digital converters (ADCs) are designed for________
63
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
64
PIN DIAGRAM OF IC555:
Ground
VCC
Trigger
Discharge
5555
Output
Threshold
Control Voltage
Reset
CIRCUIT DIAGRAM:
Vcc
+5 V
RA
6.8k
8
7
D
3
RB
3.3k
VO
5555
2
6
1
0. 1 F
0.01 F
MODEL GRAPH:
Vc
VUT
VUT
t(ms)
VO
high
tlow
t(ms)
65
Ex. No:
DESIGN OF
MONOSTABLE AND ASTABLE MULTIVIBRATORS USING IC555
DATE:
AIM:
To design and test an Astable and Monostable Multivibrators using 555 timer with duty cycle ratio.
APPARATUS REQUIRED:
S.No
1.

555 TIMER
Range
--
Quantity
1
2.
Resistors
3.3K, 6.8k
3.
Capacitors
0.1 F,0.01 F
4.
Diode
IN4001
5.
CRO
--
6.
Power supply
15 V
7.
Probe
--
8.
Bread Board
--
THEORY:
ASTABLE MULTIVIBRATORS USING 555:
The 555 timer connected as an Astable Multivibrators. Initially, when the output is high. Capacitor C
starts charging towards Vcc through R A and RB. As soon as capacitor voltage equals 2/3 V cc upper comparator
(UC) triggers the flip flop and the output switches low. Now capacitor C starts discharging through R B and
transistor Q1.
When the voltage across C equals 1/3 Vcc lower comparator (LC), output triggers the flip-flop and the
output goes high. Then the cycle repeats.
The capacitor is periodically charged and discharged between 2/3 V cc and 1/3 Vcc respectively. The time
during which the capacitor charges form 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by
Tc
0.69(RA+RB) C
(1)
Where RA and R B are in Ohms and C is in farads. Similarly the time during which the capacitor
discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by
Td
0.69 RB C
(2)
66
CIRCUIT DIAGRAM:
Vcc
+5 V
0.01 F
RA
10k
8
7
3
VO
555
2
Trigger i/p
6
1
0. 1 F
0.01 F
MODEL DIAGRAM:
67
The total period of the output waveform is

T = T c + T d = 0.69 (RA + 2RB) C
(3)
The frequency of oscillation

fo = 1 / T =1.45 / (RA+2RB)C
(4)
Eqn (4) shows that fo is independent of supply voltage Vcc

The duty cycle is the ratio of the time td during which the output is low to the total time period T. This
definition is applicable to 555 A stable Multivibrators only: conventionally the duty cycle ratio is defined as the
ratio as the time during which the output is high to the total time period.
Duty cycle
= td T
RB + RA+ 2RB
Obtain 50% duty cycle a diode should be connected across R B and RA must be a combination of a fixed
resistor and a potentiometer. So that the potentiometer can be adjusted for the exact square waves
MONOSTABLE MULTIVIBRATORS USING 555
Monostable Multivibrators has one stable state and other is a quasi-stable state. The circuit is useful for
generating single output pulse at adjustable time duration in response to a triggering signal. The width of the
output pulse depends only on external components, resistor and a capacitor.
The stable state is the output low and quasi stable state is the output high. In the stable state transistor
Q1 is on and capacitor C is shorted out to ground. However upon application of a negative trigger pulse to
pin2, Q1 is turned off which releases the short circuit across the external capacitor C and drives the output
high. The capacitor C now starts charging up towards V cc through RA. However when the voltage across C
equal 2/3 Vcc the upper comparator output switches form low to high which in turn drives the output to its low
state via the output of the flip flop. At the same time the output of the flip flop turns Q1 on and hence C
rapidly discharges through the transistor. The output remains low until a trigger is again applied. Then the cycle
repeats. The pulse width of the trigger input must be smaller than the expected pulse width of the output. The
trigger pulse must be of negative going signal with amplitude larger than 1/3 Vcc. The width of the output pulse
is given by,
T = 1.1 RAC
DESIGN:
Design an Astable Multivibrators for a frequency of ______KHz with a duty cycle ratio of
D = 50%
68
TABULATION:
MONOSTABLE MULTIVIBRATOR:
S.No
Measurements
Input
Output
Input
Output
Amplitude
1.
Time period
2.
3.
ASTABLE MULTIVIBRATOR:
S.No
Measurements
Amplitude
1.
Time period
2.
3.
69
fo = 1/T
= 1.45 / (RA+2RB)C
Choosing C = 1 F
RA = 560k
D = RB / RA +2RB= 0.5 [50%]
RB = ______
DESIGN:
Given a pulse width of duration of 100 s
Let C = 0.01 mfd
F = _________KHz
Here,
T= 1.1 RAC
So, RA =
PROCEDURE:
1. Rig-up the circuit of 555 Astable Multivibrators as shown in fig with the designed value of components.
2. Switch on the power supply to CRO and the circuit.
3. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across the timing
capacitor. Set suitable voltage sensitively and time-base on the CRO.
4. Observe the waveforms on the CRO and draw to scale on a graph sheet. Measure the voltage levels at
which the capacitor starts charging and discharging, output high and low timings and frequency.
5. Switch off the power supply. Connect a diode across R B as shown in dashed lines in fig to make the
Astable with 50 % duty cycle ratio. Switch on the power supply. Observe the output waveform. Draw to
scale on a graph sheet.
70
VIVA-QUESTIONS:
1. What are the features of 555 timers?
2. What are the applications of 555 timers?
3. Define duty cycle ratio.
4. What are the applications of Monostable Multivibrators?
5. What is meant by quasi stable state?
6. What should be the amplitude of trigger pulse?
7. What is other name for A stable Multivibrators?
8. How an Op-amp is used to generate square wave?
9. What are the changes to be done in a symmetric square wave generator to generate asymmetric square
wave?
10. What are the basic elements of 555 Timer?
11. What is the function of pin2 in IC555?
12. List down the applications of a stable Multivibrator in IC555.
13. Write down the design equations of duty cycle and frequency of oscillations for a stable circuit.
71
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
72
PIN DIAGRAM: (IC 565 & IC7490)
FREQUENCY MULTIPLIER:
73
Ex. No:
DESIGN OF FREQUENCY MULTIPLIER AND DIVIDER CIRCUIT USING

PHASE LOCKED LOOP(PLL)
DATE:
AIM:
To construct and verify the output of the frequency multiplier and divider application circuits using PLL (IC565).
APPARATUS REQUIRED:
S.NO
APPARATUS NAME
RANGE
QUANTITY
1.
RPS
(0-30) Volts
2.
Signal generator
1MHz
3.
CRO
20MHz
4.
Resistors
20K ,2K ,4.7K ,10K
5.
PLL and Counter
IC565,IC7490
6.
Capacitors
0.01F, 0.001F, 10F
7.
Transistor
2N2222
Each Two
THEORY :
In the frequency multiplier using PLL565, a divided by N network is inserted between the VCO output and the
phase comparator input. Since the output of the comparator is locked to the input frequency fin, the VCO is running at a
multiple of the input frequency. Therefore in the locked state the VCO output frequency fo is given by,
fo= N*fin
FREQUENCY MULTIPLIER:
The block diagram of a frequency multiplier (or synthesizer) is shown in figure. In this circuit, a
frequency divider is inserted between the output of the VCO and the phase comparator (PC) so that the loop
signal to the PC is at frequency fOUT while the output of VCO is N fOUT. This output is a multiple of the input
frequency as long as the loop is in lock. The desired amount of multiplication can be obtained by selecting a
proper divide- by N network where N is an integer. Figure shows this function performed by a 7490 configured
as a divide-by-4 circuit.
In this case the input Vin at frequency /in is compared with the output frequency fOUT at pin 5. An output
at N fOUT (4 fOUT in this case) is connected through an inverter circuit to give an input at pin 14 of the 7490,
which varies between 0 and + 5 V. Using the output at pin 9, which is one-fourth of that at the input to the 7490,
the signal at pin 4 of the PLL is four times the input frequency as long as the loop remains in lock. Since the
VCO can be adjusted over a limited range from its centre frequency, it may become necessary to change the CO
frequency whenever the divider value is changed. For verification of the circuit operation,
74
TABULATION:
Vin=
S.No.
fin (Hz)
Multiple Factor
fo (Hz)
Designed
Obtained
MODELGAPH:
75
one must determine the input frequency range and then adjust the free running f OUT of the VCO by
means of R1 and C1 so that the output frequency of the 7490 divider is midway within the predetermined input
frequency range. The output of VCO should now be equal to 4 fin.
PROCEDURE:
1. The connections are given as per the circuit diagram.

2. The circuit uses a 4- bit binary counter 7490 used as a divide-by-5 circuit.
3. Measure the free running frequency of VCO at pin 4, with the input signal Vi set equal to zero. Compare
it with the calculated value = 0.25 / (RT CT).
4. Now apply the input signal of 1 VPP square wave at 500 Hz to pin 2.
5. Vary the VCO frequency by adjusting the 20k potentiometer till the PLL is locked. Measure the output
frequency. It should be 5 times the input frequency.
6. Repeat steps 4,5 for input frequency of 1 kHz and 1.5 kHz.
76
VIVA QUESTIONS:
1. List the basic building blocks of a PLL.
2. Define Capture range.
3. Define lock range.
4. Define pull in time.
5. Which is greater Capture range or pull in time?
6. What is the major difference between digital and analog PLLs?
7. List the application of PLL.
8. What is the range of modulating input voltage applied to a VCC?
9. What is meant by VCO? What is the need of it in PLL?
10. Why the low pass filter circuit is need in the PLL?
11. Define accuracy of converter.
12. Define resolution.
13. What are the factors which might determine the choice of either a synchronous or asynchronous FSK
demodulator?
14. Mention the merits and demerits of PLL.
15. Mention the applications of PLL in communication areas.
77
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
78
CIRCUIT DIAGRAM OF HALF WAVE RECTIFIER:
MODEL GRAPH:
TABULATION:
Input
S.No.
Output
Amplitude
Time period
Amplitude
Time period
( No. of div x
Volts per div )
(No. of div x Time

per div )
( No. of div x Volts

per div )
(No. of div x Time

per div )
1.
2.
79
Ex. No:
DESIGN OF HALF WAVE AND FULL WAVE RECTIFIERS USING OP-AMP
DATE:
AIM:
To construct and study the working of half wave and full wave precision rectifiers using op-amp IC.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
7.
8.
9.

CRO
Dual RPS
Op-Amp
Bread Board
Function Generator
Resistors
Diode
Range
30 MHz
0 30 V
IC741
3 MHz
10K,4.7K
IN4007
Quantity
1
1
3 Nos
1
1
Each 6
2 Nos
THEORY:
DEISGN:
All the resistances are chosen as 10 Ohms and this condition make output voltage is equal to the input
voltage.
Matched diodes are used to obtain equal response in both positive and negative side signal transition. If
matched are not used for full wave rectifier the positive halves of the rectified wave will not be equal. Precision
rectifier rectifies voltages of the order of millivolts much lower than the cut in voltage of diodes. All the
resistances are chosen in kilo ohm range so that the AFO is not loaded and much greater than the output
resistance of AFO (50 ohm).
Resistances used in the design are 1Kohm and 10Kohms .The maximum voltages across the resistance will
be supply voltage. Hence wattage of resistance is V2 / R. V2 /R= 225 / 10K which is so much lower than 1/8W or
1/4W.So resistances with 5% tolerance, carbon film resistor with 1/8W or 1/4W is used.
HALF WAVE RECTIFIER:
There are several different types of precision rectifier In its simplest form, a half wave precision rectifier
is implemented using an opamp, and includes the diode in the feedback loop. This effectively cancels the
forward voltage drop of the diode, so very low level signals (well below the diode's forward voltage) can still be
rectified with minimal error.
80
CIRCUIT DIAGARM OF FULL WAVE RECTIFIER:
MODEL GRAPH:
TABULATION:
Input
S.No.
Output
Amplitude
Time period
Amplitude
Time period
( No. of div x
Volts per div )
(No. of div x Time

per div )
( No. of div x Volts

per div )
(No. of div x Time per

div )
1.
2.
81
We need to examine the circuit closely. This knowledge applies to all subsequent circuits, and explains
the reason for the apparent complexity. For a low frequency positive input signal, 100% negative feedback is
applied when the diode conducts. The forward voltage is effectively removed by the feedback, and the inverting
input follows the positive half of the input signal almost perfectly. When the input signal becomes negative, the
opamp has no feedback at all, so the output pin of the opamp swings negative as far as it can. Assuming 15V
supplies, that means perhaps -14V on the opamp output.
When the input signal becomes positive again, the opamp's output voltage will take a finite time to
swing back to zero, then to forward bias the diode and produce an output. This time is determined by the
opamp's slew rate, and even a very fast opamp will be limited to low frequencies - especially for low input
levels. The test voltage for the waveforms shown was 20mV at 1kHz. Although the circuit does work very well,
it is limited to relatively low frequencies (less than 10kHz) and only becomes acceptably linear above 10mV or
so (opamp dependent).
FULL WAVE RECTIFIER:
The standard full wave version of the precision rectifier. This circuit is very common, and is pretty much
the textbook version. It has been around for a very long time now, the tolerance of all resistance is designed to
obtain good performance, and all four resistors should be 1% or better. Note that the diodes have been reversed
to obtain a positive rectified signal. The second stage inverts the signal polarity. To obtain improved high
frequency response, the resistor values should be reduced.
This circuit is sensitive to source impedance, so it is important to ensure that it is driven from a low
impedance, such as an opamp buffer stage. Use of high speed diodes, lower resistance values and faster
opamps is recommended if you need greater sensitivity and/ or higher frequencies.
PROCEDURE:
1.
2.
3.
4.
5.
Connections are given as per the circuit diagram.

First the sine wave input is given from the function generator and it is given to the circuit.
The output of the half wave rectifier and full wave rectifier is noted with the help of CRO.
The above steps are repeated for the various values of input sine wave.
The characteristics if obtained by plotting a graph between time period and amplitude.
82
VIVA-QUESTIONS:
1. What is the PIV of Half wave rectifier?
2. What is the efficiency of half wave rectifier?
3. What is the rectifier?
4. What is the difference between the half wave rectifier and full wave Rectifier?
5. What is the o/p frequency of Bridge Rectifier?
6. What are the ripples?
7. What is the function of the filters?
8. What is TUF?
9. What is the average value of o/p voltage for HWR?
10. What is the peak factor?
11. Define regulation of the full wave rectifier?
12. Define peak inverse voltage (PIV)? And write its value for Full-wave rectifier?
13. If one of the diode is changed in its polarities what wave form would you get?
14. Does the process of rectification alter the frequency of the waveform?
15. What is ripple factor of the Full-wave rectifier?
83
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
84
CIRCUIT DIAGRAM FOR LOW VOLTAGE REGULATION USING IC 723:
TABULAR COLUMN:
Load Regulation (Vin = 10V)
S.No
RL in K
Output Voltage (VO) in

Volts
Line Regulation (RL = 5K)

Input Voltage
(Vin) in Volts
Output Voltage
(VO) in Volts
MODEL GRAPH:
85
Ex. No:
DESIGN OF VOLTAGE REGULATOR USING IC LM 723
DATE:
AIM:
To construct and test the performance of low voltage and high voltage regulation using IC LM 723.
APPARATUS REQUIRED:
S. No
Component Name
Range
Quantity
1.
Regulator IC
LM723
2.
Dual Power Supply
0-30 V
3.
Resistor
1.5k,2.2k,5k,6.5k
4.
Capacitor
0.01f
5.
Voltmeter
0-30V
6.
Breadboard
THEORY:
Initially the output voltage is high capacitor starts charging towards V C through RA and RB. As soon as
capacitor higher than flip-flop and output switches low. Now capacitor starts discharging through RB and
transistor Q1. When the voltage across C equal to V EVCC, lower than comparator output triggers the flip-flop
and discharged between (2/3)*VCC and VEVCC. The time duration which the capacitor charges V EVCC to
(2/3)*VCC is equal to the time output. With the advent of micro electronics, it is to incorporate the complete
circuit. This gives low cost high reliability, reduction in size and excellent performance. Examples of
monolithic regulators are 78XX / 79XX and 723 general purpose regulators.
Line Regulation is defined as the % change in output voltage for a change in input voltage. It is usually
expressed in milli-volts or as a % of the output voltage.
Load Regulation is defined as the % change in output voltage for a change in load current and is also
expressed in milli-volts or as a % of the output voltage.
86
CIRCUIT DIAGRAM FOR HIGH VOLTAGE REGULATION USING IC 723:
TABULAR COLUMN:
Load Regulation (Vin = 10V)
S.No
RL in K
Output Voltage (VO) in

Volts
Line Regulation (RL = 5K)

Input Voltage
(Vin) in Volts
Output Voltage
(VO) in Volts
MODEL GRAPH:
87
PROCEDURE:
1. Make the connections as per the circuit diagram.
2. Set the input voltage Vin and calculate the output voltage by varying load resistance for load regulation.
3. Set the load resistance RL=5K and calculate the output voltage by varying input voltage for line
regulation.
4. Plot the graph between Vout versus load resistance for load regulation and Vout versus Vin for line
regulation.
88
VIVA QUESTIONS:
1. Define line regulation.
2. Define load regulation.
3. What is a voltage regulator?
4. List down the characteristics of voltage regulator.
5. What are the basic elements of voltage regulator?
6. What are the types of voltage regulator?
7. State the advantages of IC voltage regulator.
8. Which are the packages in which IC723 is available?
9. List the important features of IC723.
10. Name the protection circuits used for voltage regulators.
11. What are all the limitations of linear voltage regulator?
12. Define current limiting of transistor.
13. List the positive and negative voltage regulator ranges.
14. Mention the applications of LM723.
15. List the characteristics of LM 723.
89
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
90
CIRCUIT DIAGRAM OF VCO:
MODEL WAVEFORM:
91
Ex. No: 15
STUDY OF VCO APPLICATIONS
DATE:
AIM:
To observe the applications of VCO-IC 566.
To generate the frequency modulated wave by using IC 566.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.

IC 566
Resistors
Capacitors
Dual power supply
CRO
Function generator
Range
10k,1.5k
1f,100pf
0-30 V
-
Quantity
1
Each 2
Each 1
1
1
1
THEORY:
The VCO is a free running Multivibrator and operates at a set frequency f o called free running
frequency. This frequency is determined by an external timing capacitor and an external resistor. It can also
be shifted to either side by applying a d.c control voltage vc to an appropriate terminal of the IC. The frequency
deviation is directly proportional to the dc control voltage and hence it is called a voltage controlled oscillator
or, in short, VCO.
The output frequency of the VCO can be changed either by R1, C1 or the voltage VC at the modulating
input terminal (pin 5). The voltage V C can be varied by connecting a R1 R2 circuit. The components R1 and
C1 are first selected so that VCO output frequency lies in the centre of the operating frequency range.
DESIGN:
1. Maximum deviation time period =T.
2. fmin = 1/T. where fmin can be obtained from the FM wave
3. Maximum deviation, f= fo - f min
4. Modulation index = f/f m
5. Band width BW = 2(+1) fm = 2 (f+fm)
6. Free running frequency, fo = 2(VCC -Vc) / R1C1VCC
92
VIVA-QUESTIONS:
1. What is VCO?
2. Why VCO is called voltage to frequency converter.
3. List the features of VCO.
4. Give the applications of VCO.
5. What is companding?
6. Write down the frequency conversion equation for VCO.
7. Can we design the VCO using op-amp?
8. Give the function of pin5 in VCO.
9. What are the basic blocks present in VCO?
10. Mention the merits and demerits of VCO.
93
PROCEDURE:
1.
2.
3.
4.
The circuit is connected as per the circuit diagram shown in Fig

Observe the modulating signal on CRO and measure the amplitude and frequency of the signal.
Without giving modulating signal, take output at pin 4, we get the carrier wave.
Measure the maximum frequency deviation of each step and evaluate the modulating Index.
mf = = f/fm
RESULT:
Marks Allocation
Details
Marks Allotted
Preparation
20
Conducting
20
15
Results
Basic understanding
15
Viva-Voice
15
Record
10
Total
100
status
Marks
Awarded
94

40 Ei 4p2-Lic Lab Manual

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

40 Ei 4p2-Lic Lab Manual

Uploaded by

Copyright:

Available Formats

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

CIRCUIT DIAGRAM OF NON-INVERTING AMPLIFIER:

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

To design, construct and test an Inverting Amplifier for a given gain.

Name of the Apparatus

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF COMMON MODE CONFIGURATION:

CIRCUIT DIAGRAM OF DIFFERENTIAL MODE CONFIGURATION:

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

DESIGN A NON-INVERTING AMPLIFIER WITH CLOSED LOOP GAIN - 3:

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

PIN DIAGRAM OF OP-AMP:

ACL= 1+(-RF/ R1)

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF NON-INVERITNG SUMMER:

DESIGN OF AN NON-INVERTING SUMMER:

When R1= R2= R3= R= Rf/2

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

DESIGN OF ADDER,SUBTRACTOR,COMPARATOR & ZEROCROSSING

Name of the Apparatus

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF INVERITNG SUMMER:

DESIGN OF AN INVERTING SUMMER:

When R1= R2= R3= 3Rf

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF SUBTRACTOR:

Similarly the output V02 due to V2 alone,

/*KSRCT DEPARTMENT OF EIE*/

Obtained Output Voltage

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF NON-INVERITNG& INVERITNG COMPARATOR:

OUTPUT WAVEFORMS OF NON INVERTING COMPARATOR:

OUTPUT WAVEFORMS OF INVERTING COMPARATOR:

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF ZERO CROSSING DETECTOR:

OUTPUT WAVEFORM OF ZERO CROSSING DETECTOR:

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

CIRCUIT DIAGRAM OF INTEGRATOR:

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

DESIGN OF DIFFERENTIATOR & INTEGRATOR USING OP-AMP

Name of the Apparatus

out of phase with the input signal. A

/*KSRCT DEPARTMENT OF EIE*/

/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/*KSRCT DEPARTMENT OF EIE*/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/

/KSRCT DEPARTMENT OF EIE/