Frequently Asked Questions

September 2011

New SMPTE 2022-5/-6 Intellectual Property Core features Forward Error

Correction - Speeds Development of 10 Gbps Video over IP Networks
1. What is Xilinx announcing?
At IBC 2011, Xilinx is announcing the availability of a new SMPTE 2022-5/-6 intellectual
property core that helps broadcast equipment makers speed the development of systems
that can meet the growing demand for transporting uncompressed, full-bandwidth
professional video over IP networks.
The SMPTE 2022-5/-6 intellectual property core includes Forward Error Correction
(FEC) and is part of Xilinxs Broadcast Real-Time Video Engine Targeted Design
Platform. FEC protects the video stream during transport of high-quality video over IP
networks. FEC is where the transmitter adds systematically generated redundant data to
its video. This carefully designed redundancy allows the receiver to detect and correct a
limited number of packet errors occurring anywhere in the video without the need to ask
the transmitter for additional video data. These errors, the form of lost video packets, are
caused by a variety of reasons, from thermal noise to storage system defects and
transmission noise introduced by the environment. FEC gives the receiver an ability to
correct these errors without needing a reverse channel to request retransmission of data.
In real time systems, the latency is too great to request a retransmission.
The ability of Xilinx FPGAs to bridge the broadcast and the communications industries by
performing highly integrated real-time video processing will help broadcasters reduce
costs. Now that video can be reliably delivered over 10 Gbps Ethernet (10 GbE),
broadcasters can replace some of the portable infrastructures supporting outside live
broadcasts, as well as enabling remote production from existing fixed studio set ups,
dramatically reducing both capital expenditure and operating expenses.
2. What is SMPTE 2022?
The SMPTE 2022 video networking standard defines a transport protocol for the carriage
of real-time, non-piecewise constant, variable bit rate (VBR) MPEG-2 Transport Streams
over IP networks.

IBC 2011 Frequently Asked Questions

3. What is SMPTE 2022-5?

SMPTE 2022-5 adds the FEC capability on top of the encapsulation protocol defined in
SMPTE 2022-6.
4. What is SMPTE 2022-6?
SMPTE 2022-6 is the protocol of how to map raw SD/HD/3G SDI video stream into an
Ethernet packet.
5. Why is this news significant for system designers?

Xilinx provides system designers the ability to design high-bandwidth systems for the
transport of uncompressed high-resolution video, multiple HD and 3D streams and higher
frame rates in SMPTE 2022 Ethernet IP packet formats. This results in quick adoption and
deployment of 10 GbE video over IP for wide area networks such as city-to-city or from
stadium-to-studio. System designers can also find a reduction in expenses as FPGAs
reduce costs for SMPTE 2022 systems through single chip integration, 3G-SDI-to-10 GbE
bridges with FEC, along with other video, audio and data processing functions. There is a
2x density advantage in system bandwidth when you move to the 28nm Kintex- 7
FPGAs, as well as lower BOM costs through greater integration. Additionally, system
designers benefit from reduced power due to higher SERDES speeds and the ability to use
a single SERDES for 10 Gbps data rather than the 4x 2.5 Gbps (XAUI) in previous FPGA
generations.
6. Whats a SERDES?

Xilinx FPGAs have high-speed serial transceivers for interfacing to other components at
very high bit rates over a single link. The SERDES is the serializer/deserializer which
takes parallel data inside the FPGA fabric and serializes it at a much higher rate (for
instance 20-bit wide HD-SDI video data at 74.25 MHz in the fabric is put in a single 1.5
Gbps serial SDI stream using the SERDES). This means you can use a single 1.5 Gbps
link rather than 20 separate parallel SDI I/O on the device, reducing board complexity and
saving power. The reverse is also true you can get slower speed parallel streams from a
single transceiver so you dont have to clock the FPGA fabric as fast and thereby lower
cost and power.
7. What end applications are best suited for the SMPTE 2022-5/-6 intellectual property
core?
Implementations of SMPTE 2022 interfacing could take the form of standalone piece of
equipment, or could be built into existing products such as contribution encoders, IRDs,
broadcast routers, production switchers or even cameras. Anywhere where SDI coax is
used, particularly in multichannel designs, could benefit from the SMPTE 2022
intellectual property core.

IBC 2011 Frequently Asked Questions

8. What is behind the convergence of the broadcast and telecommunications industries?

Were living in a world where phone and cable companies buy TV networks and cell
phones carry TV signals. Meanwhile, demand for TV on mobile devices, tablets and smart
TVs is changing how end-users interact with digital broadcast entertainment. With ever
increasing bandwidth availability on IP networks, both telecoms operators and
broadcasters are now able to adopt existing and commoditized Ethernet and IP-related
technologies to transport video around, even in high definition. The digitization of content
is also accelerating this convergence, particularly with HDD storage now much cheaper
than tape and resulting in the move to file-based workflows to improve efficiency and
reduce expense.
9. Is the SMPTE 2022-5/-6 intellectual property core different from what Xilinx
announced at NAB earlier this year?
Yes, Xilinx has now added the SMPTE 2022-5 capability. The SMPTE 2022-5 standard
brings forward error correction to protect the high-quality video stream as its transported
over an IP network. At NAB, Xilinx announced the SMPTE 2022 intellectual property
core supporting the -6 portion of the standard which enables video over the 10 Gbps
Ethernet network, but to reliably transport the video without implementing FEC
functionality, redundant 10 GbE links are needed.
10. Why wasnt broadcast file-based FPGA hardware deployed ten years ago?
At the time, FPGA hardware technology was available and used to accelerate video
processing systems, but the sizes of the video files were large and the cost of HDD was
too expensive compared to much cheaper video tape. This crossover point occurred
around 2006. Improved H.264 compression techniques have helped push the file based
HDD storage costs even lower. Now with 10 GbE, the bandwidth is available to
accommodate file-based workflows for uncompressed video.
11. How do FPGAs compare to custom chip or off-the-shelf solutions in bridging
broadcast and communications domains?
The inherent flexibility of FPGAs as compared with ASICs (Applications Specific
Integrated Circuits) and ASSPs (Application Specific Standard Products) means that
equipment can quickly be adapted to changing standards and have longer life in the field
after installation. Also, the relatively limited volumes associated with most broadcast
applications dont often justify the ever-increasing costs in developing a standard product
or ASIC such that the ROI diminishes in each generation of product. With FPGAs we can
amortize our R&D costs over all the markets Xilinx serves with the same product families.

IBC 2011 Frequently Asked Questions

12. What is Xilinx demonstrating at IBC 2011?

Xilinx is demonstrating several key elements of its broadcast platform at IBC, Hall 10
Stand #10.D25 including:
Implement and Adapt to Emerging Network Technologies
Xilinx will demonstrate the SMPTE 2022-5/-6 intellectual property core, which enables
the adoption of lower cost Ethernet for transporting uncompressed video, support for up to
6x HD-SDI or 3x 3G-SDI video interfaces with excellent jitter performance.
Remove External Voltage-Controlled Crystal Oscillators (VCXOs) for SDI Reference
Clocks
Debuting at IBC, attendees can see a demonstration of how customers can remove VCXO
components from their multichannel SDI designs through FPGA integration, resulting in a
significant bill of materials reduction (up to $20 per video output channel).
Lowering Power and Heat in Broadcast Applications with 7 Series FPGAs
By demonstrating SDI support on the Kintex-7 FPGA, Xilinx shows how cost and power
can be reduced by up to 50 percent without sacrificing performance compared to previous
generation FPGAs. The industrys first 28nm FPGA enables smooth migration of designs
from previous generation Virtex-6 FPGAs and across 7 series FPGAs.
IP Cores for Real-Time 1080p60 & 4K Video Processing
Xilinxs Real Time Video Engine Targeted Design Platform running on Virtex-6 FPGAs
and Spartan-6 FPGAs illustrates the use of the Targeted Design Platforms for
prototyping and implementing video processing chains in broadcast equipment.
Reduce Bandwidth and Storage Requirements Without Sacrificing Video Quality
Xilinx Alliance Member Vanguard Software Solutions will also exhibit its H.264/AVC-I
& AVC-Ultra Video Codec core, which will show broadcast equipment manufacturers
how to quickly and easily integrate AVC-I Class50 & Class100 and AVC-Ultra (up to 300
Mbps) into their broadcast systems, which ultimately leads to lower cost of using harddisk drives over tape by enabling smaller file sizes which further drives the need for
SMPTE 2022-5/6.

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