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CMOS RF Modeling for GHz Communication ICs
Jia-Jiunn Ou, Xiaodong Jin, Ingrid Ma, Chenming Hu, and Paul R. Gray
Department of Electrical Engineering & Computer Sciences
University of California, Berkeley, CA 94720
Introduction
With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process [ I ] . A
major barrier to the realization of robust commercial CMOS
RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies.
The conventional microwave table-lookup-based approach
requires a large database obtained from numerous device
measurements and computationally intense simulations for
accurate results. This method becomes prohibitively complex
when used to simulate highly integrated CMOS communication systems; hence, a compact model, valid for a broad range
of bias conditions and operating frequencies is desirable.
BSIM3v3 has been widely accepted as a standard CMOS
model for low frequency applications. Recent work has demonstrated the capability of modeling CMOS devices at high
frequencies by utilizing a complicated substrate resistance
network and extensive modification to the BSIM3v3 source
code [2]. This paper first describes a unified device model
realized with a lumped resistance network suitable for simulations of both R F and baseband analog circuits; then verifies
the accuracy of the model to measured data on both device
and circuit levels.
BSIM3v3 RF Model
The new BSIM3v3 RF model is realized with the addition
of three resistors R,, Rs+, and Rsubr to the existing
BSIM3v3.1 model (shown in Fig. I). R, models both the
physical gate resistance as well as the non-quasi-static (NQS)
effect. Rsubd and R,,,, are the lumped substrate resistances
between the source/dram junctions and the substrate contacts.
The values of R,,bd and Rsubs may not be equal as they are
functions of the transistor layout (illustrated in Fig. 2).
To demonstrate the accuracy of the model, s-parameters of
the BSIM3v3 RF model, BSIM3v3 model, and measured data
of a 0.35pm NMOS device are plotted in Fig. 3. The
improvement can be clearly seen from the 822 but hardly from
S l l . A better picture and more physical insight may be
obtained by separating the terminal impedance into the real
and imaginary parts with the following six parameters,
94
Cfi = -imagblz)/ 0 ,
Parameter Extraction
Acknowledgment
This work is supported by National Semiconductor Fellowship and SRC 97-SJ-417. The authors would like to thank
SGS-Thomson and TSMC for wafer fabrication and G. Zhang
for assistance on model extraction.
References
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