THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2009
1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

1 Part C
Keypad Encoding

Lab Weighting:

0%

Delivery mode:

Lecture

Online
 Lab

Other

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use of Xilinx ISE and Modelsim in the implementation of digital
system
2. VHDL programming

Recommended
prior knowledge
and skills3:

Course Staff
Lucien Ngalamou
Marcus George

Position/Role
Lecturer
Instructor

Estimated total
study hours1:

E-mail

lucien.ngalamou@sta.uwi.tt
marcus.george@sta.uwi.tt

Phone


Office

Office
Hours

room 202
room 203

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Understand the process of keypad encoding
2. Understand the concept of deboncing of keys of a keypad
3. Understand the operation of load + store registers and their use in digital
systems.
4. Design and implement a keypad encoder in VHDL to meet a required
specification.
5. Perform on-board testing on the keypad encoder using a time-multiplexing
display and the Spartan 3 Toolkit.

Cognitive
Level
C
C
C
Ap
An

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:
3.1. Required Reading Resources
3.2. Recommended Reading Resources
3.3. Other Resources
3.4. Pre-Lab Exercise

Lab 1c: Keypad Encoding

4.

IN-LAB

Allotted Completion 3 hours

Time:
1 Computer
Required lab
1 Spartan 3 Toolkit
Equipment:
1 keypad + 40-pin ribbon cable circuit(completely wired)
4.1. In-Lab Procedure

4.1.1 Description
Consider figure 1 which consists of a keypad encoder, a key-code register, and a time
multiplexing display. The functionalities of the different elements are given as follows:
RESET

reset

clk
12

Keypad Encoder

keys

34 Keypad

keypress

keycode

data_in
clk

clk

Frequency Divider clock1

16-bit Keycode Register

reset

reset
data_out

16

display_value

clk

RESET

4-digit Time Multiplexor

reset

seg

anode

Figure 1: Datapath block diagram of Keypad Encoder system

RESET

Lab 1c: Keypad Encoding

The Keypad encoder has 13 inputs and 4 outputs that represent the code, keycode of the
key being pressed and a detector "Keypress" which is set to one once a key is pressed. It
consists of a debounce element and of a combinational encoder as shown in figure 2. The
debounce element eliminates contact bounces that may occur when a key is pressed. The
VHDL code of a 1-bit debounce element is given, you will have to customize it using the
concept of package in order to build a 12-bit debounce module.

The key-code register is a special 16-bit shift-left parallel load register. When a key is
pressed its rightmost 4 bits are loaded with the new value and its content is shifted left by 4
bits. This register accommodates four successive keys. Its internal organization is made of a
counter that re-initializes the process once four keys are pressed successively. Its VHDL
code is given. In Your lab report will have to explain in your own words its functionality,
together with a Modelsim timing diagram of its simulation.

The frequency divider takes as input a 50 MHz clock signal a produces a 1 kHz signal
(division by 50,000).

The time-multiplexing decoder recognizes only digits 0 to 9 and generates their equivalent 7segment codes at its outputs.

The reset signal may have to be buffered using the IBUF component, the output of IBUF is
then used as the real reset signal.

The internal structure of the keypad encoder is given in figure 2 below

Lab 1c: Keypad Encoding

Figure 2: Internal structure of the Keypad Encoder

Table 1 below shows the data format that is recognized by the keypad encoder:

Table 1: Keypad Character Code

Lab 1c: Keypad Encoding

4.1.2 Lab Exercises

At the beginning of your coding process, you must have a good understanding of the design in
terms of its interface (entity) and architecture. Figure 3.6 gives you a block diagram of the system.
Your report contain have the complete VHDL code of all the modules you have implemented and
their relevant simulation results. The pre-lab is compulsory and must be added to your report.
1. Analyze and write a VHDL model of the KeyPad Encoder, use for this purpose the basic
debounce code that is posted on the course web site. Use Moldelsim to simulate its
behavior. Keys * and # are not considered to be valid codes (the decoder outputs 0000).
2. Write the VHDL code of the16-bit keycode register.
3. Write the VHDL code of the frequency divider.
4. Write a VHDL package that contains the above modules as components.
5. Write a final VHDL code of the design and simulate it.
6. Implement and test your design on the pegasus board. You should create an
implementation constraint file for the design using table 2 and the Pegaus Manual.
7. Tabulate all on-board test and include in report.

Lab 1c: Keypad Encoding

Design Port

FPGA Pin to be mapped to

clk
reset
keys(0)
keys(1)
keys(2)
keys(3)
keys(4)
keys(5)
keys(6)
keys(7)
keys(8)
keys(9)
keys(10)
keys(11)
anode(0)
anode(1)
anode(2)
anode(3)
seg(0)
seg(1)
seg(2)
seg(3)
seg(4)
seg(5)
seg(6)

T9
any available pushbutton
D11
R10
C12
T7
D12
R7
E11
N6
B16
M6
R3
C15
D14
G14
F14
E13
E14
G13
N15
P15
R16
F13
N16

Table 2: Pin Configuration for the Keypad Encoder system

Proceed to post-lab exercise.

Lab 1c: Keypad Encoding

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:
Deliverables:

End of Lab 1c: Keypad Encoding

Lab 1c: Keypad Encoding