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Introduction
The document describes the verification environment of the Power Domains (PDs) in the
PD architecture. By switching ON and OFF different Power Domains, behavior of modules
present in different domains is validated using the ARM assembly test cases.
With increasing complexities in power architecture and complex power domain partitioning,
it is becoming imperative to drive functional and physical verification of these complex
power logic hand in hand. However, despite relentless efforts of verification engineers, some
issues may still skip through and make their way to silicon. To avoid silicon failures because
of low power issues, engineers need to find state of the art methodologies to manage
unexpected low power issues.
CPF (Common Power Format), a standard format that captures the power intent of the
design is used by the verification engineers to catch low power related issues of the design.
As shown in Fig 1(a), the design without CPF has only logical connectivity. But as soon as
CPF is introduced as shown in Fig 1(b), power connectivity of design also comes in to the
picture. All low power design must comply with the low power specifications defined inside
the CPF and hence should use it as part of their design cycle.

Need for Dynamic low power verification

Low power dynamic low power checks help to verify the functionality of all the power-management elements. To achieve
that, it uses a set of stimuli on:

DUT (Design under Test), that captures logical functionality of design

CPF (Common power Format), that captures power intent of the design
Stimulus is a combination of signals prepared on the basis of the power intent and the functionality for the DUT. According
to the stimulus provided, some part of the RTL is switched off, while keeping some part at always on state. The simulator
forces Xs, on the signals coming from shut-off domains to always-on domains in order to simulate their off state. If the
desired functionality is not corrupted because of any of these Xs, the design is considered to be compliant from low power
perspective,
But there are certain issues that cannot be caught using this method. These issues if left unattended can cause silicon
failure. Let us discuss few of such scenarios in detail.

This paper describes a verification technique for certain layout design rules, like deep n-well biasing, well implant, and parasitic
effects for mixed-signal SOCs with multiple power domains. The technique analyzes the netlist and layout simultaneously and is
superior to LVS methodology. Traditional LVS methodology is not effective, either because some of these checks cannot be
performed without putting in additional layout features, or they are not conducive to debugging. To explain our algorithm, we show
examples of a deep N-well biasing check, and a parasitic junction diode check that is needed due to multiple power domains. The
verification technique and the algorithm presented in this paper were successfully used to verify 28nm and 20nm SOC designs with
many power domains and internal derived supplies. All the errors reported were tagged with schematic and layout cross-references,
along with the offending features, making it easier to identify and qualify the circuitry and signals for errors in question