College of Engineering and Applied Science

Department of Electrical Engineering and Computer Systems

EECE 2070L
Lab 8 Common Emitter Stiff Bias Configuration
Objective: To design and construct a stiff biased Common Emitter amplifier. Examine its
biasing and ac characteristics and its ac operation.
Pre-work:
1. Design a stiff biased Common Emitter amplifier, as seen in Figure 1, with a Q-point of 2
mA. Use standard components in your design.
2. Draw the AC Hybrid Pi model of the Circuit and calculate Zin, ZOut, Av, GdB, and AI.
3. Using the Circuit from Figure 1, add enough un-bypassed resistance to limit the GdB =
40 (AV -100)
Simulation: (For the report)
1. Simulate the circuit designed for Figure 1.
a. Include screen shots for the measurements taken in lab, in the report
b. Include a Bode Plot from 100 Hz to 100 MHz
2. Simulate the circuit designed for Figure 2.
Procedure:
1. Construct the Common Emitter amplifier you designed and simulated in the pre-work as
seen in Figure 1.
XSC1
Ext Trig
+
_
A
+ _

Rb1

15 V
Vcc

B
+ _

Vout

Rc

Q1
2N3904

1F
Cc

1F
Cb
20mVpk
10kHz
0
Vin

Rb2
Re

1F
Ce

Figure 1: Stiff Bias Common Emitter Amplifier

1
EECE 2070L Summer 2016

College of Engineering and Applied Science

Department of Electrical Engineering and Computer Systems

2. Using the oscilloscope (DC coupled, CH1 to VIn, CH2 to VC) observe and record:
a. VIn vs VC (Screen shot measure Vpp)
b. VIn vs VOut (Screen shot measure Vpp, Phase 12)
i. Vout MidBand =
Note the difference between the screen shots and the phase shift between VIn and VOut.
3. Measuring the corner frequencies. (Screen Shots Measure Vpp, Frequency)
a. Lower the frequency until VOut = 0.707 x VOut Mid band. This is the low corner
frequency of the bode plot f1 =
b. Raise the frequency until VOut = 0.707 x VOut Mid band. This is the high corner
frequency of the bode plot f2 =
4. Set the Frequency to 10 kHz. Increase Vin until clipping of VOut occurs. (Screen Shots)
a. Record VOut just starting to clip.
b. Record VOut Max (No Clipping) =
c. Place Ch2 probe on VC, using the horizontal cursors, determine the bias level by
placing cursor a at Vpmax and cursor b at Vpmin.
5. Modify the circuit by inserting a 1.5k test resistor between Vin and the amplifier. With
the circuit connected, adjust the function generator to 50mVp.
XSC1
Ext Trig
+
_
A
+ _

Rb1

15 V
Vcc

B
+ _

Q1
2N3904
1F
Cb
10mVpk
10kHz
0
Vin

Vout

Rc

1F
Cc

R test

Rb2
Re

100F
Ce

Figure 2: Impedance Measurement Test

6. The input and output impedance of your amplifier can be experimentally determined by
understanding that Zi is the Thevenin equivalent impedance at the input and then using
the voltage divider rule to solve for it shown in Figure 3. Use Channel 2 on your scope to
determine Vzi.

2
EECE 2070L Summer 2016

College of Engineering and Applied Science

Department of Electrical Engineering and Computer Systems
XSC1
Ext Trig
+
_
A
+ _

B
+ _

R test
50mVpk
10kHz
0
Vin

Zi

Figure 3: Thevenin Equivalent Test Circuit

Find your actual Zi by solving the equation:

=

50

(1)

1.5+

Show your work below:

7. Fill in the table and include it in the report.

Analysis Method
Calculated
Simulated
Prototype

IC

AV

ZIn

ZOut

3
EECE 2070L Summer 2016

College of Engineering and Applied Science

Department of Electrical Engineering and Computer Systems

8. Add RE1 to the circuit as seen in Figure 2. Note that it is not bypassed by CE, record the
input and output waveforms to include in your report. (Screenshot, Vpp, Phase 12)
Avact =
XSC1
Ext Trig
+
_
A
+ _

Rb1

15 V
Vcc

B
+ _

Vout

Rc

Q1
2N3904

1F
Cc

1F
Cb
R e1
20mVpk
10kHz
0
Vin

Rb2
R e2

100F
Ce

Figure 4: Stiff Bias Common Emitter Amplifier with Gain Control

Analysis:
1. Compare calculated, simulated and measured Values. Discuss % error and potential
sources of error for anything greater than 10%.
2. Compare the simulated bode plot vs the measured corner frequencies
Conclusion:

1. Thoroughly explain how the amplifier works. Include explanations of why the output
wave is inverted compared to the input wave, why clipping occurs at Vo amplitude
somewhat below Vcc and somewhat higher than ground.
2. Explain in detail how adding an unbypassed portion of Re controls the gain. What
advantages might this technique provide?
3. Anything else deemed pertinent.

4
EECE 2070L Summer 2016