Advanced Electronics Digital PDF

ELECTRONICS
DIGITAL
K. F.
CATHEY
R. D.
MITCHELL
R.
W.
D. A.
TINNELL
YEAGER
DELMAR PUBLISHERS, MOUNTAINVIEW AVENUE, ALBANY. NEW YORK

A DIVISION OF LITTON EDUCATIONAL PUBLISHING,
INC.
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Division of Litton Educational Publishing, Inc.
Copyright
1972
By Technical Education Research Centers,
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is
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Inc.
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Health, Education, and
The opinions expressed
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do
the
not necessarily reflect the position or policy of
endorsement
U.S. Office of Education, and no official
by the U.S. Office of Education should be
inferred.
Foreword
The marriage of
electronics
and technology
New
technical personnel in today's industries.
with combination
devices of
optical
many
must
new demands
for
occupations have emerged
who work
Increasingly, technicians
kinds
many
with systems and
mechanical, hydraulic, pneumatic, thermal, and
be competent also
skills is especially significant
in
electronics. This need for
who
for the youngster
is
combination
preparing for a career
technology.
in industrial
This manual
for students
is
one of
who want
The most
pations.
creating
requirements well beyond the capability of
skill
technical specialists.
is
a series of closely related publications designed
the broadest possible introduction to technical occu-
manuals
effective use of these
is
as
combination textbook-
laboratory guides for a full-time, post-secondary school study program that

provides parallel and concurrent courses
in electronics,
mechanics, physics,
mathematics, technical writing, and electromechanical applications.
unique feature of the manuals
in this series is
technical laboratory study with mathematics
topic
is
the close correlation of
and physics concepts.
studied by use of practical examples using
modern
Each
industrial applica-
The reinforcement obtained from multiple applications of the concepts

shown to be extremely effective, especially for students with widely
diverse educational backgrounds. Experience has shown that typical junior
tions.
has been
college or technical school students can
make
satisfactory progress in a well-
coordinated program using these manuals as the primary instructional material.
School administrators
manuals to support a
programs
in
such
fields as:
or quality assurance.
will
common
be interested
first-year
in
the potential
of these
core of studies for two-year
instrumentation, automation, mechanical design,
This form of technical core program has the advantage
of reducing instructional costs without the corresponding decrease in holding
power so frequently found
in
general core programs.
This manual, along with the others

of research and development
Inc.,
(TERC),
in
the series,
is
the result of six years
by the Technical Education Research Centers,
a national nonprofit, public service corporation with head-
quarters in Cambridge, Massachusetts.
It
has undergone a
number of
revisions
as a direct result of experience gained with students in technical schools
community
and
colleges throughout the country.
Maurice W. Roney
Hi
The Electromechanical Series
TERC
is
engaged
cal Technology.
in
an on-going educational program
The following
titles
in
Electromechani-
have been developed for this program:
INTRODUCTORY
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ELECTROMECHAN ISMS/DEVICES
ELECTRONICS/AMPLIFIERS
ELECTRONICS/ELECTRICITY
MECHANISMS/DRIVES
MECHANISMS/LINKAGES
UNIFIED PHYSICS/FLUIDS
UNIFIED PHYSICS/OPTICS
ADVANCED
ELECTROMECHAN ISMS/AUTOMATIC CONTROLS
ELECTROMECHAN ISM S/SERVOMECH AN ISMS
ELECTROMECHAN ISMS/FABRICATION
ELECTROMECHAN ISMS/TRANSDUCERS
ELECTRONICS/COMMUNICATIONS
ELECTRONICS/DIGITAL
MECHANISMS/MACHINES
MECHANISMS/MATERIALS
For further information regarding the
its
EMT
program or for assistance
in
implementation, contact:
Technical Education Research Centers, Inc.
44
Brattle Street
Cambridge, Massachusetts 02138
iv
Preface
Technology, by
its
very nature,
provide meaningful experience
a laboratory-oriented activity.
is
portion of any technology program
is
vitally important.
in digital circuit
The topics included provide exposure

flip-flops
and other
The sequence
is
intended to
modern technology.
basic principles of digital logic, logic gates,
to:
of presentation chosen
may choose
by no means
is
to use the materials
Some
exercises or to supplement
some of them to
in
instructors
better
meet
inflexible.
expected that
It is
other than the given sequence.
volume were selected primarily
particular topics chosen for inclusion in this
convenience and economy of materials.
The
Electronics/Digital
analysis for students of
circuits, as well as to basic digital systems.
individual instructors
The
As such, the laboratory
may wish
in a
of the
many
of the
their local needs.
materials are presented in an action oriented format combining
features normally found
for
some
to omit
textbook with those usually associated with laboratory manual.
Each experiment contains:

1.
An INTRODUCTION which
identifies the topic to be
examined and often includes
a rationale for doing the exercise.

2.
A DISCUSSION
which presents the background, theory, or techniques needed to
carry out the exercise.

3.
A MATERIALS
experiment.
list
which
not normally included

4.
A PROCEDURE
experiment.
that
all
identifies
all
of the items needed
in
the laboratory
(Items usually supplied by the student such as pencil and paper are
In
in
which
the
lists.)
presents
step-by-step
for
instructions
performing the
most instances the measurements are done before calculations so
of the students can at least finish making the measurements before the
laboratory period ends.

5.
An ANALYSIS GUIDE which
offers suggestions as to
approach interpretation of the data

6.
PROBLEMS
covered
in
in
how
the student might
order to draw conclusions from
it.
are included for the purpose of reviewing and reinforcing the points
the exercise.
The problems may be
of the numerical solution type or
simply questions about the exercise.
Students should be encouraged to study the text material, perform the experiment,
work the review problems, and submit
a technical report
pattern, the student can acquire an understanding of,
that will be extremely valuable
These materials on
technical
skill
topic.
Following this
with, basic digital circuits
on the job.
digital electronics
students by the
and
on each
TERC EMT
comprise one of a
staff at
direction of D.S. Phillips and R.W. Tinnell.
The
Oklahoma
volumes prepared for
State University, under the
principal authors of these materials
K.F. Cathey, R.D. Mitchell, R.W. Tinnell and D.A. Yeager.
series of
were
An
Instructor's
was responsible for
Data Guide
available for use with this volume. Mr.
Kenneth
F.
Cathey
and compiling the instructor's data book for them.

made valuable contributions in the form of criticisms,
testing the materials
Other members of the

corrections,
is
TERC
staff
and suggestions.
hoped that this volume as well as the other volumes in this series, the
of
instructor's data books, and the other supplementary materials will make the study
technology interesting and rewarding for both students and teachers.
It
is
sincerely
THE TERC EMT STAFF
vi
Contents
experiment 00001
BINARY NUMBER SYSTEM
experiment 00010
BOOLEAN ALGEBRA
experiment 0001
OSCI LLOSCOPE
experiment 00100
WAVEFORM MEASUREMENTS
BASIC WAVEFORMS
19
26
experiment 01011
TRANSISTOR SWITCHING
DESIGN OF THE TRANSISTOR SWITCH
DIODE CLIPPERS
TRANSISTOR CLIPPERS AND CLAMPS
DIODE LOGIC GATES
RESISTOR-TRANSISTOR LOGIC (RTL) CI RCUITS ....
Dl RECT COUPLED TRANSISTOR LOGIC (DCTL) GATES
experiment 01 100
INHIBITORS
106
experiment 01 101
FUNDAMENTALS OF MULTIVIBRATORS
115
experiment 01 110
BISTABLE MULTIVIBRATORS
121
experiment 01
MULTIVIBRATOR TRIGGER CI RCUITS

INTEGRATED CIRCUIT LOGICAL FLIP-FLOPS
BLOCKI NG OSCI LLATORS
TWO-DIODE STORAGE COUNTER
BASIC COUNTERS
127
experiment 00101
experiment 00110
experiment 001
1 1
experiment 01000
experiment 01001
experiment 01010
1 1 1
experiment 10000
experiment 10001
experiment 10010
experiment 10011
experiment 10100
experiment 10101
experiment 10110
experiment 10111
experiment 11000
experiment 11001
experiment 11010
experiment 11011
experiment 11100
experiment 11101
experiment 11110
37
47
59
67
76
85
95
133
140
148
156
RING COUNTER
SHIFT REGISTERS
165
DIODE MATRIX CI RCUITS

PARITY CHECKING CI RCUITS
INTRODUCTION TO DIGITAL TEMPERATURE CONTROL
184
172
TEMPERATURE CONTROL CLOCK

MANUAL TEMPERATURE CONTROL
TEMPERATURE CONTROL COUNTERS
AUTOMATIC TEMPERATURE CONTROL
COMPUTER PROBLEM SOLUTIONS
SUMMARY OF LOGIC OPERATIONS
vii
192
.
199
203
210
215
221
230
233
The author and
editorial staff at
Delmar Publishers
are interested in
continually improving the quality of this instructional material. The reader

is
invited to submit constructive criticism
and questions.
reviewed jointly by the author and source editor.
will
Send comments
Editor-in-Chief
Box 5087
Albany,
Responses
New York 12205
be
to:
experiment
III! III/
00001
I
N UM B E R
BINA R Y
YS TEM
INTRODUCTION. In order to facilitate high-speed calculations in digital computers, new

In this experiment we will examine the Binary Number
machine languages can be used.
System and perform some arithmetic operations using this system of numbers.
DISCUSSION. Binary arithmetic is the "malanguage" of many computers.
A
The number 524 can be read five huntwo tens, and four units. It could also
chine
dreds,
good knowledge of computer fundamentals

can open many rewarding career opportunities.
A digital computer can operate at very high
be expressed:
speeds.
uses basically only
It
524=
5 X 10 2 +
(10 =
These two conditions can

be translated to the characters 0 and 1, which
"off" and "on".
are
the
System.
two digits of the Binary Number

The computer works with these two
and all information to be
the machine must be converted
binary numbers,
used inside
numbers. You will need to know

machine language to understand com-
into binary
this
puter operations.
Since the machines we are discussing are

made up of devices that respond to only two
states, we need to develop a number system
to match.
That is to say, our usual number
system will not work with such a machine
because it employs ten digits.
in
the system are
binations of these digits.
think
465
of
as
being
It
We
don't usually
made up of four
NOT
a basic digit in the system.
In
system (or any worthwhile number
sys-
is
tem),
number
is
said
4X
10
1)
(1.1)
524=5X 100+2X
10 +
4X
524 = 500+20 + 4
524 = 524
The base of the number system is the
number which, when raised to the zeroth
power gives the lowest position value, and
when raised to the first power, it is the
second
position,
N=
R n dn +
+ R1
d.,
We
etc.
can
the
write
any number system
general equation for
+ R3d
as:
R2 d2
3+
+ Rd
Q
(1.2)
made up of com-
hundreds (10 times 10), six tens (10 times 1),

and five units (10 times 0.1). The number
10 is called the base of the decimal system.
this
10 1 +
So
We all know that our everyday number

system has only ten digits and that all other
numbers
2X
two conditions,
to
have position.
mean zero hundreds, seven

tens and one unit, while 710 means seven
hundreds, one ten, and zero units.
The
where:
N=
the
number
d n = the digit
in
that position
R = the radix (base of the system)

Substituting:
This makes 071
position of
the digits determines the mag-
nitude of the number.
5654 = 5 X 10 3 +
6X
10 2 +
5654 = 5000 + 600 + 50 +4
5654 = 5654
5X
10 1
+4X10
EXPERIMENT 0000 1
The
So much for the number system we are

It can be difficult and timefamiliar with.
The binary system has only two

binary
Let's test the
1.
N = 27
see
that
we
0 system probably
base
N=
binary then
1
X8 + 0X4+ X2+
in
decimal
X 2 3 + OX 2 2 +
8+OX 4+
16 + 8 + 0+2+
X 16+
X2 +
1
X 2+
X 2
N = 27
can
isn't
For instructional purposes these numbers

have been expressed in the familiar decimal
system. We can convert to binary notation in
order to take advantage of the simpler digits.
1-2
Figure
not very useful. Consequently the binary (base 2) system is the

simplest usable system. It contains only two
these
digits but can express any number with
system too
If
1.
X 24 +
N=
N=
1
= 0 as
very useful because 0 = 1 and 0
is
system
does 0 to any power. The base 1
similar to a base zero system. It has only one
digit since multiplying one by itself any
number of times produces only one. Thus,
this
or,
2)
system against our general equation to see

produces different numbers in each poit
2 = 1 and 2 1 = 2, etc., which
sition.
Why couldn't the
satisfies the definition.
Again, applying the rule
equation (dg, d-p d 2 c^)
N= 16+8 + 0+2+
if
base be 0?
0 or
N = 11011 in
N= 1 X 16+
digits,
(base
digits in this
are either
consuming for a computer to handle a tencomdigit number system in its millions of

many
add
to
putations due to its ability
numbers with fewer digits. For this reason
the Binary Number System is often employed.
0 and
ELECTRONICS/DIGITAL
BINA R Y NUMBER SYSTEM
is
expressed
shows the decimal
binary
in
digits
code.
From equation 1.3 for the

number system, we have evolved
base
two
digits.
N=
comparison of the base 2 and base 10

systems (see Fig. 1-1) may be helpful.
2d.|
+ 1d 0
X 2 3 + 0 X 22 +
^
(1.3)
the particular position
Base 2
2 =
10 1 = 10
Tens
21 = 2
Twos
102 = 100
Hundreds
22 = 4
Fours
103 = 1000
Thousands
23 = 8
Eights
Base Ten
Units
2 4 = 16Sixteens
104 = 10,000 Ten Thousands

Fig. 1- 1
will notice that
Units
is
Base 10
10 =
X 2 +
1
each of the multipliers

for the powered numbers in the equation are
either 0 or 1. These digits tell whether or not
You
system and can be simplified to
+ 8d + 4d 2 +
3
the decimal number 27 expressed in

the binary form. By further inspection the
binary form of the number 27 can be reached.
which
The binary system has only two digits

and all numbers are constructed with them.
The general definition (1.2) applies to the
N=
X 24 +
Base
Two Comparison
is
filled in
the binary
ELECTRONICS/DIGITAL
EXPERIMENT 00001
Decimal
Binary
(1
11 (1
Fig.
appear
it
other
2)
words,
X 2 +
OX
2)
2)
+0X
0X
21
X 22 +
0X
21 +
(1
2)
2)
+0X
2)
110(1 X 2 2 +
X 21
X 21 +
111
(1
X 22 +
1000
(1
X 23 + 0 X 22 + 0 X 2 + 0 X
2)
1001
(1
X 23 + 0 X 2 2 + 0 X 2 1 +
2)
2)
1
Decimal Digits Expressed in Binary
1-2
when the ones
says, "Yes, this position
100(1 X 2 2 +
101
In
10(1 X 2
system.
BINA Ft Y NUMBER SYSTEM
is
Listing the remainders
filled for
left
number." Therefore, the binary notation

number 27 is 11011. It has 1
power 2 plus 1 power 2 3 , plus 0 power 2 2
plus 1 power 2 1
plus 1 power 2 or "yes,
this
to right
we
of (25)
l0 is(11001) 2
for the decimal

4
from bottom to
top,
have 11001; the binary form

.
Conversion of the decimal system to any
yes, no, yes, yes."
number system requires only division by the

base of that number system, keeping track of
This corresponds well with
the "on", "off" capability of devices
from
the remainders, and reading the answer from
which computers are made.

We can get decimal numbers from binary
numbers but how do we get binary numbers
from decimal numbers?
The procedure is
the
last
Now we
number evenly, or have a remainder of

The presence of the remainder determines
whether or not that power position is filled.
the
quite easy
can change numbers back and
will.
They
same way as positive powers. Let's go

back to the general equation for base 10 and
use negative exponents.
one.
we
at
numbers?
the
if
first.
But what about fractional

aren't too bad if we remember that negative powers work in much
and takes longer to explain than

to learn. It consists of successive divisions by
the base number. The base will either go into
forth
For instance,
remainder to the
desire to write the binary
form of (25)
iq (which
base 10), first divide the
is
read as twenty-five,
N = d 1 XR- 1 +d 2 X R- 2 + d 3 X
number by two:
Remainder
ntMMd
12+11
25 divided by 2== 12+
Then divide 12 by 2 = 6 + 0
R-
+ d X R" n
n
t
For binary, we have
f
N =
Up
3
2" 1
+ d X 2"2 + d X
2
3
2"
ELECTRONICS/DIGITAL
EXPERIMENT 00001
3
=1 X2- + 0X2" 2 + 0X21
(0.10010) 2
Then, if we pick a fractional number 0.621,

we can write the decimal form
6X
0.621 =
10" 1 +
2X
10- 2 +
10" 3
2" 4
(0.10010) 2 = 0.5 + 0.0625
0.621 - 0.6 + 0.02 + 0.001
(0.1
0010) 2 = (0.5625) 10
0.621 = 0.621
Similarly, a fractional binary
may be
number
(0.1
This process can be carried out to any

number of places required. When the answer
not accurate enough, the process may be
001 ) 2
written as
(0.1001)2=1 X2+
is
0X2- 2 +0X2"
carried out to
accuracy
1X2" 4
Now
=1
until the desired
achieved.
we
that
are
familiar
with
X^ + OX^ + OX^
tigate operations in the binary system.
order to understand the computer,
(0.1001)2=1
learn
how
dition,
(0.1001) 2 = (0.5625) 10
sion.
Then
Then
Then
Then
multiply
multiply
multiply
multiply
3062
0.26124
0.52248
0.04496
X 2
X 2 =
X 2 =
X 2 =
X 2 =
1.1
3062
0.261 24
the
0.52248
1.04496
0.8992
0+0=0
(1.4)
1+0=1
(1.5)
0+1
(1.6)
= 10
or
Read
Etc.
how
combinations. The combinations are:
to binary.
this
Binary addition has only four possible
Here is a method that can be used to

Suppose the
convert decimal to binary.
converted
to
be
is
0.56531
decimal number
0.
in
subtraction, multiplication, and diviWe will do some of these operations
with pencil and paper to illustrate

machine does them automatically.
Converting fractional binary numbers to decimal numbers is an easy process.
multiply 0.56531
makes computations
Binary arithmetic is concerned with the

same four basic operations found in decimal
These basic operations are adarithmetic.
0+ 0+0.0625
First,
it
In
we must
number system.
X-l+Oxl+OX-1+1
(0.1001) 2 = 0.5 +
the
from
Binary Number System and how to get
investo
one system to another, it is time
or
(0.1001) 2
is
more places
0+
carry
(1.7)
Down
Collecting the whole
top
down we
numbers from the
read the answer as (0.1 0010... 2
Since
would
the binary
be written in two
be
2,
system requires that it

places as 10. This means that the
must
be
carried to the next higher place for addition.
This can be checked by the previous
So
method.
= 10.
An example might
help.
ELECTRONICS/DIGITAL
EXPERIMENT 00001
Take the decimal number 13, written 001101

in binary and add the decimal 37, written
100101 in binary.
one from a binary two leaves a binary one,

To check this,
=
add binary 1 + 1
0 + carry or 10 or
just as in the decimal system.
(2)iq.
Let's try another
001101
+ 100101
110010
example:
11011001
10101011
00101110
001 0 is the binary form of 50.

+ 1 = 10, yields the first digit 0, carry the 1.
+ 0 + 0 = 1, yields the second digit 1, plus
1 1
1
1
The binary 11011001 corresponds to

1Q minus 10101011, or (171) 10 equals
or (46)
10 These numbers can be
verified by the technique described earlier.
(217)
nothing to carry.
1
= 10, yields the third
00101110
digit 0,
plus
to carry.
1
0=10,
yields the fourth digit 0, plus
There are some other methods for binary

but they will not be discussed
to carry.
subtraction
0+0=1,
yields the fifth digit
1,
plus
here.
nothing to carry.
0+1
yields the sixth digit
1,
1,
plus nothing
The next operation to be discussed
to carry.
Putting
the digits together,
all
Binary subtraction
is
The only
as in decimal.
we
get
that of binary multiplication.
10010.
simple operation.
is
zero
let's
minus one, which requires borrowing from
= 0
0=
101110011
1
or (53)
10
But
0-1
111
110101
110101
110101
0- 0 = 0
-
the computer
110101
can see that:
is
a quite
consider the following example:
the next higher position.
We
is
performs multiplication by repeated addition.

In order to examine how the system works,
the same operation

tricky thing
Actually,
It
1+borrow
(1.11)
There
of a
(Because the
two of the binary system
action again,
and
after borrowing,
(7)
is
10 =(371) 10
an easy
few simple
way
to add.
It
consists
rules.
is in
1.
2-1 =1).
Count the number of ones + carries.

If the resulting number is even,
A.
the
10=(2) 1Q
B.
-01 = <1>1Q
If
the
01 = (1)
10
sum
is
zero.
the resulting
sum
Count the
is
number
is
odd,
one.
One cannot be subtracted from zero so a one

must be borrowed from the next digit, making
ones to determine
how many ones are to be carried to
the next higher position.
Be sure
to count the carried ones in the
the binary 10 or
(2)
pairs.
1Q
2.
Subtracting a binary
pairs of
Binary division
By
simple as binary
as
is
Quotients other than one or
multiplication.
ELECTRONICS/DIGITAL
EXPERIMENT 00001
using your conversion,
that binary
110=
and (1100) 2 =
zero are impossible.
(6)
1
2)
you
will find
000) 2
10 (1001
,
q.
It is
(72) , 0
easy to see that
,
the divisor will not go into the dividend,

the divisor cannot be subtracted from the
if
10|
1100
1001000
dividend and leave a positive difference.
110
00110
110
MATERIALS
Pencil
00000
and paper
PROCEDURE
1.
Develop the positive integers of the Binary Number System through 100 and record them
in figure
2.
1-3A.
Convert the following binary numbers to their decimal equivalents and record them
in
figure 1-3B.
111011101, 11101101, 10110.1101, .11011, .10001

3.
Convert the following decimal numbers to binary and check by converting binary back
to decimal and record in figure 1-3C.
353, 557, 632, .725, .5625

4.
Add
the following groups of binary numbers and convert the answers.
Record
in figure
1-3D.
(a)
5.
1011011
10 1101Q
(b)
(c)
Subtract the following, convert the answers and record

(a)
6.
110111011
100111011
10110
Q1010
(b)
in figure
0000000110110111
0000001101101110
0011011011100000
1101101110000000
1-3D.
100110001101
010101110010
Multiply the following binary number. Convert the multiplier and multiplicand and check
your answer. Record
in figure
1-3E.
110110111
10111
X
7.
Divide the following binary numbers.
answer.
Record
Convert the divisor and dividend.
Check the
in figure 1-3E.
1001 11010001
you should develop some ideas about how the computer

to
handles these calculations. Explain how a computer can know that the number it is trying
a
subtract is smaller than the number to be subtracted from? Discuss why it is useful for
computer to use the Binary Number System. Show how a computer would perform a simple
ANALYSIS GUIDE.
In this exercise
multiplication problem.
EXPERIMENT 00001
ELECTRONICS/DIGITAL
Decimal
Binary
Decimal
Binary
Decimal
Binary
Decimal
26
51
76
27
52
77
28
53
78
29
54
79
30
55
80
31
56
81
32
57
82
33
58
83
34
59
84
10
35
60
85
11
36
61
86
12
37
62
87
13
38
63
88
14
39
64
89
15
40
65
90
16
41
66
91
17
42
67
92
18
43
68
93
19
44
69
94
20
45
70
95
21
46
71
96
22
47
72
97
23
48
73
98
24
49
74
99
25
50
75
100
(A)
Binary
Decimal
Decimal
111011101
353
11101101
557
10110.1101
632
.11011
0.725
.10001
0.5625
(B)
Binary
(C)
Fig. 1-3
The Data Tables
Binary
EXPERIMENT 00001
ELECTRONICS/DIGITAL
Decimal
Binary
4.(a)
4.(b)
4.(c)
5.(a)
5.(b)
(D)
Decimal
Binary
6.
7.
(E)
Fig. 1-3
The Data Tables (Cont.)
PROBLEMS
1.
What
is
the answer
in
binary numerals?
2.
Give the answer
in
1572
964
decimal.
001101
+ 100101
3.
110101 X 111-5-87 =
(liHlll! BOOLEAN ALGEBRA
experiment
00010
INTRODUCTION. When problems
logic are considered, some interesting mathematical

Boolean algebra is one of these mathematical forms. In
examine some of the shorthand notations of Boolean algebra and learn
of
forms can be developed for expression.
experiment we will
few Boolean theorems.
this
DISCUSSION. Some of the

logic are quite old.
by
Many were
He
Aristotle.
said
principles
first set
forth
1
(2.4)
0X0=0
1X0=0
0X1=0
(2.6)
1X1
(2.8)
Equation 2.4
may look
Remember that it is
a little suspicious to
you.
a law; also
that
statements.
Boolean algebra employs operations with

functions having two
value
while for logic multiplication, the laws are
In 1847,
false and never partly true or false.
George Boole, an English mathematician,
developed a shorthand notation for these
single
(2.3)
that there existed
statements that were either true or
certain
1+0=1
of
possible
(2.5)
(2.7)
discrete states.
For our purposes, Boolean algebra applies
0 and
to the binary digits of
to
simple
the
switch,
1.
When
applied
two values can
correspond to "open" and "closed".

convention, the open state
0 and the closed
is
For
usually labelled
Boolean algebra is
similar to ordinary algebra and arithmetic.
The distributive law applies and factoring and
expansion are permitted.
It
is
different
in
that
it is
state, 1.
mathematics
have two possible states.

true or false.
"closed,"
0 or
in
which variables
A statement
is
either
The switch is either "open" or

1.
What better language could
be chosen for a discussion of switch circuits?
Boolean algebra provides a convenient method
the
is
maximum
value
What
this law really says
"all"
still
nothing
this
in
finding a
circuit.
number of
It
provides a means of
circuits that will
perform
AND
OR
and
tiplication.
The
helps in understanding the meanings of
the laws.
AND
multiplication
can be substituted for the
sign
OR
while
stituted for the addition sign.
become
0 or 0 = 0
=
or 0 =
or
0 or
Oand 0 = 0
basic laws for logic addition
are
and 0 = 0
0+0
= 0
(2.1)
Oand
= 0
0+1
(2.2)
and
can be sub-
the laws of Boolean algebra and
a given switch function.
Only two operations are permitted in

logical algebra.
They are addition and mul-
the system.
nothing.
of expressing switching arrangements without
drawing the
in
that "all" plus
equals "all", just as nothing plus
is still
The words
stituted
is
remember
can
The
be sublaws then
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
EXPERIMENT 00010
+ 1=1 read
1X1 = reads
This makes the equation

"1 or 1 is still 1" while
For the first combination, A = 0, B = 0

The function f (A, B) = A + AB = ?
Substituting f (0, 0) = 0 + (0) (0) = 0
For the combination A = 0, B = 1
f(0, 1) = 0+(1)(0) = 0
almost universally used to

denote OR, the X and the dot () are both
occasionally used for AND.
plus sign
is
For the combination
(1,0)=
Functions
may
be evaluated
in
the usual
and
B,
we
all
of the possible
0,
B = 0
A=
0,
B =
A=
1,
B = 0
A=
1,
B=
this
is
true,
the
(A, B) =
(2.10)
The
real
that
Boolean
A + AB
value of Boolean notation is

laws of many physical
For our
it
manifests
as switching logic.
are closed.
A o
In figure 2-2
cf
Two Switches in
Series
C/To
-clfc
2-2
purposes,
switches each, figures 2-1 and 2-2. In figure

2-1 an output is possible only if both A and B
can have only four possible solutions. These

arise from the possible combinations given
Fig.
called the law of absorption.
Consider the electrical systems of two
(2.9)
Fig. 2- 1
is
follows the
it
systems.
function
itself
A+ AB = A
This theorem
Since
corresponds to the value substituted for A.

From this fact, we can observe that:
combinations:
A=
B= 0
+(1) (0) = 1
1,
Careful inspection of the answer column for

these expressions will reveal that the answer
Given two variables,
can write
A=
For the combination A = 1, B =

f(1,1) = 1 + (1)(1) =
However, due to their simplicity, all the

possible values may be determined. That is, a
Boolean function of two variables has only
way.
four possible choices.
as follows:
and 1 are also still one." This is the

meaning of these laws which directly relate
to AND and OR circuits in computer logic
It should be noted here that, while
design.
"1
the
and may be written
previously
Two Switches in
10
Parallel
an output
is
available
EXPERIMENT 00010 BOOLEAN ALGEBRA
ELECTRONICS/DIGITAL
PARALLEL SWITCHES
SERIES SWITCHES
Output
Open
Open
No
Open
Open
No
Closed
Closed
Yes
Closed
Closed
Yes
Open
Closed
No
Closed
Open
Yes
Closed
Open
No
Open
Closed
Yes
Fig.
if
Output
either
figure 2-3
or B
lists all
is
2-3
Possible Switch Combinations
The
table in
closed.
addition operations. This opens the possibility

of developing a machine which can
the possible combinations
do these
mathematical operations electronically using
for both sets of switches.
switches or transistors.
Substituting 0 for open (or on)
two
switching tables gives us
in
the
The dual of an
tables which
algebraic equation
correspond
equation obtained from the original by
addition.
changing
to Boolean multiplication and

These tables are shown in figure 2-4.
certain
pairs
of
symbols.
is
that
inter-
This
in our study of
Boolean algebra in that the dual of each law is
also a law, and each theorem based on the law
For
has a dual.
This saves much time.
=
example, the law 0 + 0
0 has as its dual
1X1 = 1, when 1 is substituted for 0 and X is
becomes important to us
This table illustrates an important fact.

Series
switches
multiplication
can
and
be
to
used
parallel
used to represent addition.
represent
switches can be
This
is
a very
substituted
important application of Boolean algebra for

us,
because
it
or transistor
multiplication
can be used to describe switch
When any theorem
for +.
Boolean algebra
is
proven,
its
dual
is
in
auto-
matically accepted.
Not only can

and addition be represented by
logic
circuits.
Many theorems can be developed for

Boolean algebra. When we restrict the pos-
switch combinations, but switch combinations
can be represented by the multiplication and
BOOLEAN ADDITION
BOOLEAN MULTIPLICATION
(Series Switches)
(Parallel
Switches)
AB
A+
Fig.
2-4
Boolean Multiplication and Addition
11
0 and 1,
itself which
to
number of variables
method of proof presents
sible
a
is
normally impossible in regular algebra because

may be
of the infinite number of values which
proof
is
consists
called the exhaustion
substitution
direct
of
possible combinations of 0 and
the
theorems can
quick
the
The use
A X A
can be proven
but actually
a dual of the addition
000
100
010
needs no
theorem.
Therefore, the proofs of the duals will not be

after this.
AX A
0+1
1X1
0X0 = 0
A+0 = A
(b)
AX
A
1
1+0=1
0+1
5 (Distributive Law)
(A + B) + C = A+(B + C);
+
AX(B + C) =
(2.15)
AXB AXC
(AXB)XC = AX(BXC)
(A + B) + C =
0 + 0= 0
001
0+1
110
1+0=1
101
011
1
1
+
+
+
1
1
=
=
=
(b)
(B
1+0=1
0+1
0+1
=
=
1
1
0+1
6 (DeMorgan's Law)
(A + B) X (A + C) =
(AX B) + (AXC) =
(a)
(2.12)
+ C) =
0+ 0= 0
A+
1+0=1
1+0=1
111
2 (Identity Law)
(a)
0+ 0= 0
THEOREM NUMBER
THEOREM NUMBER
B +
1+0=1
(b)
(2.14)
A+ B = ?
0+0=0
(a)
ABC
shown
A+ B= B+A
AX B=BXA
it is
(Commutative and
THEOREM NUMBER
0+0=0
proof since
use a truth table and
below,
0+1
(A or A is A) (2.11)
(A and A are A)
A+A
as
of the possible combinations.
similarly,
(b)
we can
The dual theorem
(a)
Associative Laws)
many complex
of
reduction
THEOREM NUMBER
(a)
A+A=A
AX A=A
Its dual (b)
list all
of theorems
this
A+ =?
THEOREM NUMBER
equations to simpler forms, as well as the

perform
design of switch circuits which can
specific switching functions.
To prove
This can
be demonstrated
indeed
using switch circuits.
allows
1.
all
(2-13)
method and
of
Law)
switch circuits and
to
related
directly
be
THEOREM NUMBER 3 (Identity

A+1 =
AX 0=0
This method of
to the variables.
assigned
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
EXPERIMENT 00010
A+
AX
(B
C)
(B + C)
(2.16)
+ 0=
similar to the other theorems.

interesting to examine the switch net-
The proof
1+0=1
0 + 0=0
It
is
is
work equivalent
12
for
theorem
six
(a).
It will
EXPERIMENT 00010 BOOLEAN ALGEBRA
ELECTRONICS/DIGITAL
(A + B)
A +
(A + C)
Fig.
2-5
(B X
C)
Theorem Six
two networks are open and

the same conditions, and the two
"not zero."
be found that the
indicates
closed for
possibility
networks are equivalent.
is
equal to
we have
1.
Since the only other
in
binary
0,
or "not one"
is 1,
continue this to general terms,

Then, if A = 0, A = 1; or if A = 1,
THEOREM NUMBER
(a)
(b)
A+(AXB)
AX(A+B)
(Absorption
A
A
=
=
The
illustration
electrical
(2.17)
of
may
Fig.
2-6
is
representation. This combination
how
difficult
To
zero.
= Not A.
= 0.
of
this
is
When one
set
is "made," the other

is "not"
The following theorems are derived
from the "not" function.
an elec-
trical
is
contacts
made.
be proven by exhaustion
through a truth table.
A
A
Law)
single-pole double-throw switch.
This theorem
"not zero"
shows
networks may be reduced to
THEOREM NUMBER
8 (Double Negation)
simple networks
(A) =
Now we
reach
ordinary algebra.
function.
(2.18)
departure from our
This concept
The not function
is
is
Read not (not-A) =
the "not"
usually
by the symbol A read "A Bar" or

the symbol A' read "A Prime." In either case,
the symbol indicates "Not A." Zero Bar (0)
dicated
2-6
Theorem Seven
13
^0
Fig.
in-
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
EXPERIMENT 00010
Electrically, a switch that
was open, but has
Example:
returned to the closed position,
now been
illustrates this
Reduce
THEOREM NUMBER 9
A + A=
(a)
(b)
A X A= 0
(2.19)
A+A=
0+1 =
1+0=1
AB + C
Given:
theorem.
AB X
this
(A + B) C + AC + B =
Theorem 8 & 10 (b)
AC
Theorem 6
(b)
AC +
AC
C+
Theorem
+ B =
B) = ?
(BC +
Theorem
(2.20)
(a)
AC + BC
(a)
B =
1 1
(b)
C + B = Answer,Theorem
'Writing the next to last step
like 7 (a).
look
This theorem holds true for any number of

Its proof is similar to the others.
variables.
one
this
+ B =
to a simpler
work
AC
expression
to
C)
Theorem 10
form
THEOREM NUMBER 10
A + B + C) = A_- _ C_
(a)
(AX BXC) = A+B + C
(b)
You may want
AC+B =
(or
A X C + C + B
(a)'
makes
it
mce
the
Given the expression
following ones) out for yourself.
THEOREM NUMBER
A+
AX(A+B) = AXB
A+(AXB) = A+B
(a)
(b)
THEOREM NUMBER
(A X
(b)
B) +
AC
(2.21)
draw the switch diagram.
12
(A+B) X (A + C) X
= (A+ B) X (A + C)
(a)
B +
11
(AX
C)
(B
+ C)
(2.22)
+ (B X C)
<>
= (A X B) + (A X C)
Now
that
we have
seen several theorems,
These
time to examine their usage.
factor
terms,
expand
to
used
be
can
theorems
simpler
to
polynomials
and reduce complex
forms. When we remember that all Boolean
it
is
Fig.
2-7
The Example Circuit
expressions can really be switching combinations, the real worth of the system is realized.
Simplify algebraically:
which allows understanding

of highly complex switching circuits from the
It
gives us a tool
design
standpoint,
ability to
tems.
as well as providing the
A + B + AC =
Rearranging terms
Theorem 7 (a)
A + AC + B =
A + B = Answer
investigate existing switching sys-
simple example of each method
may
help you understand this useful tool.
14
by
BOOL EAN AL GEBRA
EXPERIMENT 00010
ELECTRONICS/DIGITAL
mathematical manipulation
Draw the network.
largely a matter
is
There are no easy rules for maniptheorems and expressions. As in

algebra, you can start by removing the parentheses (or bars), then study and compare the
of choice.
ulating the
theorem for application.
Remember,
in
our
field
sents a parallel circuit while
OR
AND
(+)
repre-
(X) repre-
sents a series circuit.

Fig.
2-8
The Simplified Circuit
Many times
Many more examples could be
in
given, but
relay,
these two should be enough to demonstrate

the worth of the system. In the highly com-
AND
plex switching circuitry of a digital computer,
is
or any other type) referred to as an

circuit.
While a set of parallel switches
referred to as an
OR
simplifications of this sort are a great help.
With a knowledge of the theorems, we can

solve almost any circuit for a workable
solution. You should realize that the solution
arrived at may not necessarily be the only
solution nor even the best.
the stage
at
This
is
MATERIALS
1
because
which we decide to stop the
0 SPST switches
3 SPDT switches
1
VOM
or
FEM
OR CIRCUIT o
+ B
AND CIRCUIT O-
A
Fig.
2-9
X B
the computer field you
will find a set of series switches (electronic,
OR A
OR AB
AND - OR Switch
15
Circuits
circuit.
EXPERIMENT 00010
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
PROCEDURE
SPST switches may be wired to aid
Prove theorem 3(b) using the truth table method.
draw the equivalent circuit.
you in understanding the theorem. Record the Proof and
2.
Prove theorem 6(b) and draw the equivalent circuit.
3.
Construct the experimental circuit
Fig. 2-
10
First
in figure
results.
2-10.
Fig. 2-
Experimental Circuit
Record your
1 1
Experimental Switching Circuit
4.
Write the Boolean expression for the experimental circuit.
5.
circuit
Using a truth table, verify the output of the experimental
6.
the equivalent circuit. Record

Simplify the expression using the theorems and construct
draw the simplified circuit.
the steps in the mathematical simplification and
7.
output as the experimental circuit in

Verify that the simplified circuit produces the same
figure 2-10. Record the truth table.
8.
Construct the switch circuit as shown
9.
Write the Boolean equation for this circuit.

a truth table for this
in figure 2-6.
in figure 2-1 1.
Record
it
in
the data table.
experimental circuit and record your
results.
10.
Develop
11.
verify your results by the

Simplify the circuit as much as you can mathematically and
truth table. Draw the simplified circuit.
12.
and make a truth table for

Using single-pole-double-throw switches, construct a circuit
Theorem 8. Record your circuit diagram and truth table results.
compare the
analyzing the data from this experiment, you should
approach. Do they agree?
Boolean algebra method of circuit description with the hardwire
ANALYSIS GUIDE.
Which method
In
easier?
is
Why?
PROBLEMS
1.
Simplify
2.
Draw
(AB + A)
C = output
the circuit diagram for the following expression.
wx + wz + wy +
3.
Check the
(a)
A+
Do
not simplify.
x'y'
table,
identity of each of the following expressions with a truth
A' =
(b)
A' = 0
(c)
16
(A')
EXPERIMENT 00010 BOOLEAN A L GEBRA
ELECTRONICS/DIGITAL
THEOREM
A X 0= 0
AX0=0
3(b)
THEOREM
A
6(b)
I
TRUTH TABLE FOR
A
B
Fig.
(A X B) + (A X C) =
AX
(B + C)
(A X
+ (A X C) =
AX
(B + C)
B)
BOOLEAN EXPRESSION
2-10
0
1
Fig.
2-10
SIMPLIFIED EXPRESSION
x
Fig. 2-
12
The Data Tables

17
Fig.
2-10
EXPERIMENT 00010
ELECTRONICS/DIGITAL
BOOLEAN ALGEBRA
Fig. 2-11
Rhni FAN FOl JATION
SIMPL IFIED EQUATION
Fig. 2-11
THEOREM
BOOLEAN EXPRESSION
A
|
Fig.
2-12

18
OSCILLOSCOPE WAVEFORM
ME AS UREMENTS
00011
experiment
INTRODUCTION. The most

experiment we
will set
important tool for waveform analysis is the oscilloscope. In this

up an oscilloscope and make some measurements of waveform voltage.
DISCUSSION. An
oscilloscope
more than
kind of voltmeter. Instead
a special
of a meter
movement with
a pointer,
the uses of this
we
confine
will
our consideration to the ones most necessary
has a
it
all
highly versatile instrument,
(CRT) with an electron
ray tube
cathode
no single exercise can cover
really little
is
for analyzing a
wave shape.
beam. The deflection elements cause the beam
much
to deflect in
deflects
cases
its
the same
The
pointer.
way
What are the parameters which are important when considering waveforms? AC am-
voltmeter
deflection in both
DC
plitude and
proportional to the voltage applied.
is
are probably the first
level
considerations but period and frequency are
Another
scope
able
is
applied voltage.
rapid
is
to the rise time, duration, and polarity can be
determined to establish the type of wave.
oscillo-
These are only the most obvious considerations
changes
By thinking of the
in
scope spot as the end of the voltmeter pointer,
we can visualize the
but they do provide us with a starting place.
trace as a two-dimensional
display of the horizontal
and
order to save time and reduce wasted
In
vertical voltages
effort, a technician often
applied to the oscilloscope deflection circuits.

In less
regard
the
beam
the fact that the electron
follow very
to
The shape with
also very important.
feature of the oscillo-
special
adopts a more-or-less
standard oscilloscope setup procedure.
expensive oscilloscopes these two inputs
following
(horizontal and vertical) are often the only
suggested as a general pattern and
is
minor modification for
require
ones available (sometimes the cathode of the
will
CRT is also accessible
instruments.
for intensity modulation
The more expensive laboratory

models have these plus many other features.
of the trace.)
2.
Turn power switch to

If
The
special
off.
appropriate, plug in the desired
plug-in unit.
laboratory-type instrument
often
is
the only suitable tool for any serious

analysis.
Most of these units have
DC
3.
wave
inputs,
4. Set the
calibrated vertical attenuators, horizontal time
bases and trigger circuits, to
Among
voltage,
name
AC
amplitude, pulse duration,
quency, period,
rise
5.
DC
its
settings.
time base (sweep)
internal
generator to
few items.
the things they will measure are:
Set the intensity, focus, gain and
sync controls to their lowest
calibrated position.
Set the sweep selector switch to the

off or external position.
6. Set the horizontal
fre-
time, phase, and wave
tion
shape.
controls
to
and
vertical posi-
their
mid-range
positions.
7.
The subject of this laboratory exercise

covers the measurement aspects that will be
primarily useful in waveform analysis. Since
Check the power

that
8.
it is
plug to insure
in.
Turn the power switch to the on

position.
19
line
properly plugged
approximately one
Allow
9.
ELECTRONICS/DIGITAL
WAVEFORM MEASUREMENTS
EXPERIMENT 00011
minute
17.
Make any
necessary focus, astigma-
and intensity adjustments to
warm-up time before making
AC
tism
measurements and five minutes

fore making DC measurements.
be-
obtain an easily visible

18.
until
screen.
tion of the vertical amplifiers, which

is
normally be used to avoid
damaging the
CRT
19.
screen.
usually in the plug-in unit).
Note the type of probe to be used,
X10, X1, X100,

20. Set the vertical
In the event that no spot appears
with a maximum setting of the
intensity control,
it
is
intensity
should
wave calibrator for

one volt output. (Watch out for
the volts, millivolt selector.)
22. Adjust the sweep (variable time base)

for approximately one cycle for
ONCE MORE, the

be
turned
every
down
23. Position the

ient
with the electron beam.

.
Adjust the focus control for a sharp,
brightness.
proper positioning of the spot. It

should be at the left center of the
n the event that overshoot or under-
of the probe compensation
sation
sweep oscilloscopes,
mode
automatic position.
is
may be
Improper probe compen-
required.
screen.
illustrated in figure 3-2.
25. With the probe ungrounded, touch-
control to the
ing the tip with
Set the trigger
your finger should

trace
the
slope control to the positive position.
produce a variation
(Instrumentswithout triggered sweep
amplitude dominated by 60 Hz hum.

If the probe is grounded with the
should be set to internal sweep.)

15. Set
the
position
sweep
magnifier
to
sometimes convenient
it
clean
horizontal line should appear.
and the horizontal display
Reposition the trace so that
in
controls set as described, a
X1
selector to normal sweep.

16.
shoot (positive or negative sloping

waveform tops) occurs, adjustment
13. Adjust the positioning controls for
set the trigger
The amplitude of
viewing.
ance.
24.
triggered
waveform for conven-
waveform leading edges. Figure 3-1

shows the proper wave-form appear-
Turn up the screen illumination control and adjust it to the desired
14. For
horizontal deflec-
the square wave should be exactly

one cm with no overshoot on the
well-defined spot.
12.
two cm of
tion.
before repositioning the deflection

controls to avoid damaging the screen
1 1
amp. attenuator to
21. Set the square
probably be-
vertical position controls should
produce the spot.
etc.
the one volt/cm position.
cause the spot has been deflected off

the screen. Resetting the horizontal
and
(including calibra-
and calibration
intensity setting
that produces a clearly visible spot
should
probe should
be checked for correct compensation
the spot appears on the
The lowest
using an oscilloscope with a
built-in calibrator, the
10. Carefully advance the intensity control
When
line.
line
starts
on the zero
set
It is
this
axis (center-line) of
This gives the waveform
at the left edge of the screen grad-
the screen.
uation.
a zero reference.
20
to
EXPERIMENT 0001 1
ELECTRONICS/DIGITAL
Fig. 3-1
Properly Displayed Square Wave
WA VEFORM MEASUREMENTS
One Volt
Calibration
Probe Properly Adjusted
(A)
(B)
Fig.
3-2
(A) Overcompensated Probe

(B)
Undercompensated Probe
21
The foregoing steps are somewhat lengthy

to
and read, but,
list
take
in fact,
time to
little
modified to fit the particular instrument you will

be using. You should practice setting up your
actually perform.
ELECTRONICS/DIGITAL
EXPERIMENT 0001 1
They may have
scope until you can do
it
to be
ment with
a calibrated
desirable.
For that reason thisdiscussion will
First
we
is
With most instruto be measured is
for measurement.
signal
input
an
accept
to
ready
ments the normal signal
applied to the vertical amplifier.
The
CRT
instruments
atory
the
trace.
vertical
quency.)
steps in
1.
amplitude measurement
voltage
(in
2.
In labor-
most
5.
is
is
be measured to
Adjust the sweep rate (time/cm) until
number
of divisions be-
Due
to
it is
recommended
that
be used. Normally, the fastest reasonable sweep rate will be best for easy
calculations.
6.
The horizontal and

controls
may be
waveform
7.
controlled by a front
calibrated in frequency
time base
signal to
the extreme edges of the screen not
achieved by comparing the incoming

wave period to the internal sweep time of the
instrument. Some oscilloscopes have a time
knob
Apply the
of the sweep,
is
this case the
without overdriving
nonlinearity at the beginning and end
frequency measurements with the

oscilloscope are based on time measurements.
panel
signal
be measured can be viewed.
All
units.
operation
tween the points on the waveform to
that of
wave shape can be found.
is
in
Set the vertical attenuator to a deflection factor which will display the
a convenient
any part of the particular
base generator which
Place the oscilloscope
tively.
the frequency of the wave. Using a laboratory

instrument with a calibrated horizontal time
This
convenient to use the following
sweep trigger slope and mode

to Internal, + and Automatic, respec-
any part of the wave
Another useful measurement
fre-
4. Set the
shape can be determined.
base, the period of
for determining the width
the vertical input.
and
applyingthe multiplication factor to the input

attenuator (Don't forget the probe attenuation), the voltage of
to measure
the vertical amplifier.
cases,
CRT
It is
expected
3.
on the face of the
graduations
work
is
By counting the
measurement).
how
according to your setup procedure.
provided with calibrated attenuators for precise
consider
will
making time measurements.
voltage
amplifier
most
and frequency (pulse repetition rate or
of the input signal produces a corresponding

vertical deflection of the
is
This measurement becomes impor-
tant in digital
oscilloscope
sweep control
be limited to this type of oscilloscope.
duration.
After the setup steps are completed, the
instru-
In pulse or digital
quickly without
directions.
work, an
duration.
In
as
vertical position
used to position the
needed for measurement.
Count the number of centimeters

between the points on the waveform
to be measured (figure 3-3).
such that the period-
sure the sweep variable control
to-frequency calibrations are automatic.
Make
is
in
the calibrated position before taking

In
any oscilloscope,
if
the reading.
the time period for
one complete cycle can be determined, the

frequency can be calculated.
since frequency
is
This
is
8.
The time duration between the two

points can be determined by equation
possible
3.1.
the reciprocal of the time
22
EXPERIMENT 0001 1
ELECTRONICS/DIGITAL
cm
-*
Fig.
Time Duration
3-3
nor zonta distance (cm) X horizontal sweep

Time Duration =
'
setting
(3.1)
magnification
cm
Horizontal distance = 5
For example:
This
(figure 3-3)
sider
is
that of rise time.
wave and pulses
Horizontal sweep speed
= 0.1 ms/cm
instantaneous
Sweep normal
a finite
(magnification
measurement we wish to con-
last
rise times.
In practice,
amount of time
is
and have
however,
required for the
voltage to rise to the top of the waveform.
1)
Simply, then, the
rise
time could be considered
the time required for the voltage to reach
Substituting in 3.1,
maximum.
TD
In theory, square
are perfectly square
= -
give a
= 0.5 milliseconds
To
its
eliminate the corners and to
more constant
value, rise time
is
defined
as the time required for the voltage to rise from
10% to 90% of its total excursion.

shown in figure 3-4.
Once the time duration is found, only one

more calculation is required to obtain fre-
Rise time
is
quency.
Frequency =
Time Duration
90%
(3.2)
To continue the example,

RISE TIME = 0.05
f
=
0.5
ms
PRACTICAL SQUARE WAVE
This procedure covers the major considerations
for
frequency.
measuring time
duration
and
10%
One other major measurement
should be considered
MICROSECOND
= 2000 Hz
in
foundation for pulse and
order to have a good

digital
work.
Fig.
23
3-4
Rise Time
With
sweep,
rise
ELECTRONICS/DIGITAL
EXPERIMENT 0001 1
good scope that has
scope
a calibrated
time can be easily measured.
is
being used to check the
time of
scope must have a
signal generator, the
It
rise
much
faster rise time than the generator.
can be read directly from the screen using the

method discussed for time duration measure-
The only difference is in the positioning

of the waveform so as to be able to read the
time duration between the 10% and 90%
ments.
As
rise
time of an
about 1/3 of the period at the

high frequency cutoff. This says that a scope
with a pass band of 4 Hz has a rise time in the
amplifier
points.
There are a few points
rough measure, the
is
Four megahertz have a
vicinity of 0.08 us.
relative to rise
period of 0.25 microseconds; therefore, the

rise time of a four megahertz scope is about
measurements that are worth remembering. The instrument used to measure rise
time
time must have considerably better characterThat is, if a

istics than the unit under test.
1/3
X 0.25 ms or 0.08 microseconds
MATERIALS
1
Oscilloscope with probe
Function generator
DC power
VOM
supply (0-40V)
or
FEM
PROCEDURE
1
Set up the scope using the procedure outlined
in
the discussion.
2.
discussion.
Calibrate the probe using the procedure outlined in the
3.
Set the
4.
Measure the
5.
Repeat steps three and four for one volt differentials to 15
6.
Apply
7.
Read the amplitude of the
8.
Repeat steps 6 and 7
9.
Apply
DC power
DC
supply to approximately 10 volts.
voltage with the oscilloscope and with the multimeter

volts.
IV peak to peak 100 Hz sine wave to the oscilloscope
30 Hz
sine
in
signal
vertical amplifier.
with the scope and with the multimeter.
IV steps up to five
wave to the scope
volts.
input.
cycle.
10.
Read and record the time duration of one-half
11.
Repeat steps 9 and 10 for 60, 100, 200, 500, 1000 Hz.
12.
Determine the frequency of each wave using your period measurements.
13.
Apply
4.
15.
100 Hz pulse or square wave to the scope.
Determine the
rise
time of the
signal.
Repeat 13 and 14 for 500 Hz and
kHz.
24
EXPERIMENT 0001 1
ELECTRONICS/DIGITAL
ANALYSIS GUIDE.
In
analyzing these data you should compare the accuracy obtained using the
AC and DC voltage measurement. Discuss

behind
the
of
use
a calibrated horizontal sweep as a basis for measuring period and
the reasoning
oscilloscope to that obtained with the multimeter for
frequency.
DC
10
Volts
11
12
13
14
60
100
200
500
15
Power Supply Reading

(Multimeter)
Oscilloscope Reading
Audio Generator Hz
30
1000
Time Duration 1/2 Cycle

Frequency
AC
Volts
Multimeter Reading
100 Hz
Frequency
Rise
500 Hz
kHz
Time
Fig.
3-5
The Data Tables
PROBLEMS
1.
Why
is it
necessary to have a faster
than the instrument under test?
rise
If
time on the scope used to make the measurement
this
is
not so, what does the
rise
time measured
correspond to?
2.
What
3.
is
the period of a
certain
kHz waveform?
waveform has
horizontal sweep control
What
is
a horizontal deflection of
is
the time duration of the entire cycle? What
25
is
cm
for one complete cycle. The

The sweep magnification is off.
the frequency of the waveform?
set to 0.1 millisecond/cm.
BASIC WAVEF0R
QQIOO
ent
information to the individual

are used in logic circuits to transmit
and the,r
the basic waveforms will be exam.ned
In this experiment some of
INTRODUCTION. Waveforms
,ogic devices.
characteristics considered.
DISCUSSION. Logic
dous importance to
devices are of tremen-
The complex com-
us.
in space
puters of this age allow us to travel
do our ordinary household

thought of
chores. These devices are usually
and it is true that
as being largely electronic,
However, it is
electronics plays a major role.
well
as
as
like
is
principles,
basic
all
logic
all
electronic.
spans the
enters the
realm of physical science and even
in human
mind
area of philosophy and the
Logic
encounter.
mediums.
variety of
to
a mistake to believe that
Logic,
mind the
vehicle for our study, keeping in
to a
applicable
fact that the principles are
a tool
is
used by the
Basic to the study of logic

are used to
the study
code or
tell
what to do by changing
which
the magnitude, shape, frequency, etc.,
the
circuits
logic
includes the
changing of direction or
level
of a current or voltage.
first
human mind.
and most basic computer, the
They
of waveforms.
is
Fortunately,
highly
and
sophisticated
for the
very useful tools have been developed
For our purposes we can

application
some
to
areas
specific
of
study
narrow the
common
of the
of these
physical sciences.
true that
(in fact, at
most of the language
of light which,
seen
rapid
development
in
sentation of a voltage
of
the
changes
any physical form deals with
parameters of the
field
is
will
etc.
been
methods,
in
this
area,
the
language,
will use electronics as
at
given
rate.
The number of times
in
it
one
a given time period (usually
termed the frequency. The units

and are
of frequency are cycles per second
The time taken to
expressed in Hertz.
is
produce each cycle
and techniques are well-defined.
For this reason we
itself
defined as a cycle.
second)
water, copper,
Because electricity and electronics have

operating
repeat
interest the pattern of
this
cycles
passage of information.
oil,
repre-
waveform on the screen
most cases of
to
air,
happens the waveform is said to be

developed the
periodic. From this concept is
combination
idea of frequency. Each repetitive
When
of application
corresponding to voltage, current, and power

transmission. These parameters are combined
produce waveforms and pulses in the
medium used for the

The medium can be
will
calibrated as to
produce
cathode ray tube. Other devices such as
its
In
in
oscil-
are also
the mechanical strip chart recorders
the same.
used, but the basic principle is
the non-
electronic areas of logic as well.
Logic
when properly
time and amplitude,
the
in
present time, the application of logic) is
few years
the electronic field, but the past
have
the cathode ray
is
This instrument produces a dot
loscope.
These areas are electronics,

is
mechanics, hydraulics and pneumatics. It
The most
waveforms.
electrical
is
called the period.
units of period are seconds.
the
26
The
The
relationship
EXPERIMENT 00100
ELECTRONICS/DIGITAL
between the frequency and period of
form
wave-
they have on circuits and devices.

present
is
BASIC WA VEFORMS
we
For the
be primarily concerned with
will
periodic waveforms.
'=4
(4.1)
Sinusoidal variations are found through-
They produce the
out the physical sciences.
where
= frequency
T=
the time
in
in
Hertz
wave pattern
familiar
seconds for one
which
from graphing the trigonometric
result
complete cycle.
sine function. Sinusoidal
here
This expression will be used over and

over
in
we examine wave
particularly useful when an
various forms as
analysis.
It
is
employed for wave analysis.

horizontal
scale
on most scopes is directly
The
calibrated in time (or frequency) units. The
period of the wave can be found by observing
the time duration for one complete cycle.
oscillosocpe
is
Taking the reciprocal of time duration (or

period) will yield the frequency.
as a
generally speaking, of
We
Periodic waveforms are easily displayed

a
the
laboratory- type
pattern
positioned
is
and
traced repeatedly,
only one cycle
is
two complete
shown, there
that inaccuracy will develop
while
the
returned to
electron
its
beam
can be
is
is
danger
the
lost
scope
is
starting point.
little
are,
interest in digital
with
largely
nonsinusoidal waves.
These waves are those
of voltage or current
whose changes
are not
sine functions.
There are two methods for analysis of

nonsinusoidal
The
waves.
first
is
math-
method in which any periodic waveform can be expressed as a combination of a

ematical
number of pure
sine
waves of different amplitudes, frequency and
The time period of the periodic nonwave will be a whole number
phase.
sinusoidal
multiple of the time period of each of
component
sine
cycles.
due to time
in
it
time base
a horizontal
that will display at least

If
it
Normally
measured.
good practice to use
Since
oscilloscope.
They
be dealing
will
DC component and
on
waves are mentioned
point only.
starting
circuits.
"sine waves"
called
sine
its
These component
waves.
waves are called harmonics of the given
The
wave with the lowest

The ratio
of the frequency of a harmonic to the frequency of the fundamental is the number of
frequency.
frequency
is
sine
called the fundamental.
the harmonic.
For instance,
if
fundamental
cause these waves, by definition,
200 Hz is given, the third

600 Hz and the fifth is 1 kHz.
The mathematical process by which these
component waves are determined is called
at a cyclic rate.
Fourier Analysis.
frequency
Aperiodic waves are not readily displayed
harmonic
on the ordinary laboratory oscilloscope be-
do not occur
They must be displayed on
some type of recording oscillograph. Some

of these waveforms occur only when the
circuit
is
monic
Variations of this
type are called transients.
Sometimes we
Notice that the
first har-
the same as the fundamental (200 Hz).
The Fourier system has
turned on or off or when a dramatic
change of state occurs.
is
of
is
all
of the advantages
of a mathematical representation.
Equations
can be written whose graphical representation
produces the amplitude spectra of the wave-
are
very interested in these because of the effect
form.
27
a square
wave
is
J
+
+|
[sin cot
sin
cot
+^
sin
5 cot +
7T
(2i^T)
1)wt
sin
= voltage amplitude at any
cot
3
sin
cot cos
cot cos
sin
cot
cot
(4.4)
where d =
(ff)
(duty cycle)
harmonics are present and a DC component

none of the waveforms fall
is present because
cycle is
below the horizontal axis. The duty
All
is
always odd
go
cot cos
N = term number
1) = harmonic number which
(2N -
'
time
(4 2)
where
2 cot cos 2 cot
+
sin(2N
sin
= + (sin cot cos cot +

7T
e =
for a rectangular
The general equation

pulse waveform is
general trigonometric equation for
The
ELECTRONICS/DIGITAL
BASIC WA VE FORMS
EXPERIMENT 00100
= angular velocity of the
the percentage of time the overall
fundamental
maximum
wave
is
at
its
value.
have
All of these equations theoretically
Several
be
can
things
determined by
a wave.
observing the general equation for
square
From equation 4.2 we can tell that this
(the 1, 3,
wave contains only odd harmonics
component
DC
no
Also there is
5, etc.).
because this equation
is
symmetrical about
value for
the horizontal axis (the average
the amplitude,
e,
zero).
is
many terms but
infinitely
more than 10 to 20
sine
describe a waveform.
application,
in
waves are required to

The higher-numbered
harmonics become small enough to be negafter
ligible
require
waveforms may
Pulse
that.
more harmonics to be adequately
depending on the duty cycle.

required
That is, the number of harmonics
cycle.
duty
to the
is inversely proportional
represented,
a
Observe the following equation for
This rule
is
important for short duty cycles
only.
sawtooth wave:
After the sine wave, which
covered
=
[sin cot -
sin
From equation
sin
cot
+ ^
sin
3 cot +
is
in
AC
circuit
courses,
prominent basic waveform
is
is
normally
the
most
the square wave.
square waves
Let's continue our discussion of
method of analysis. In this

as
second method the wave is considered
The
variations made up of small segments.
using a second
(4.3)
cot
4.3
we can determine
that
of as
segments themselves can be thought
shapes
These
being one of four basic shapes.
all
are
harmonics
the harmonics are present (odd
-). The
have + signs and even harmonics have
wave
no
symmetrical
the
sine,
waveforms.
and exponential
truly square wave is made up
step,
ramp,
of a series of step voltages.
about the horizontal
sudden
axis.
28
change from
step voltage
is
one constant voltage
to another.
level
we
Theoretically,
to
like
think of this change as instantaneous.
Any
some
finite
change
however,
does,
require
This length of time
length of time.
BASIC WA VEFORMS
EXPERIMENT 00100
ELECTRONICS/DIGITAL
is
usually
compared with the time of the

level. This sudden change
very short
preceding constant
be
can
from
of
amplitude
the
shows
or
positive
constant
the
difference of the
4-1
the
either
in
direction
step
negative
defined
is
The
level.
two constant
the
as
Figure
levels.
waveform.
a square
Square Waveform
Fig. 4- 1
The period of the square wave
in
figure 4-1.
voltage
square wave has a stepped
constant
(at
the time
is
for
level)
time
duration
which
period.
This brings up the idea of a rec-
tangular
pulse
equal
is
pulse
waveform can be calculated by
the
one-half
to
Pulse "on" time v inn
+
o
Duty
Cycle io/\
X 100
(%) i
pulse
waveform
that
it
the
made up
The only
segments.
relationship
of
the
made up
equal
time
to
maximum
in
is
the "off"
The square wave can be described
as a
type of rectangular pulse having a
50%
in
special
to
duty cycle.
con-
the
50%
When
ratio,
the duty cycle falls below
the waveform
rectangular wave.
its
defined as a
is
rectangular
wave whose pulse width
step function
amplitude) that
wave
is
any
less
than ten times
< 10 (pulse duration)
(4.5)
is
pulse duration.
time (step function
drops to zero), the square wave

case
is
duration
(4.4)
of square pulses which
"on" time (when the
suddenly moves to
wave
Pu se period
function
the square waveform
If
sidered to be
is
of step
practical difference
the period.
have an
rectangular
similar to a square
is
also
is
waveform.
is
Period
a special
of the general rectangular pulse wave-
form.
The duty
cycle of any rectangular
-^PERIOD
PULSE
OFF
DURATION
TIME
This relationship
is
PULSE
DURATION
Fig.
4-2
Pulse
and Rectangular Waveform
29
demonstrated
in figure 4-2.
From
ELECTRONICS/DIGITAL
BASIC WA VEFORMS
EXPERIMENT 00100
figure 4-2
it
is
important to learn
zero
equal to the
The
that the total pulse period
is
This
pulse duration plus the pulse off time.
can be expressed as
maximum
base line to the

trailing
edge
is
amplitude.
portion of the curve after
the pulse has dwelt through the pulse duration

(T ) and falls to the previous zero or reference
level.
T = T d + T0
p
(4.6)
4-3
Figure
represents
perfect pulse waveform.
where
= pulse period
Td =
TQ
more
pulse
reveals
= pulse off time
edges
are
some
require
and
Pulse
will
examine them
in
For this reason
some
detail.
We
we
wave shape
is
much
you
The
fall
time
is
of time required for the pulse
will notice that
to
the average of the voltage variations during

the pulse duration time. Figure 4-4 shows that
be defined that apply
and square waves.
figure 4-3,
rise
drop from 90% of the average

The average amplitude
amplitude to 10%.
is
pulse waveforms including both rec-
tangular
length
that
shorter than
curve
Some terms must

all
but
(These time periods occasionally go
fall.
of the average amplitude.
that of a square wave.
to
changes,
of time to
length of time required for the curve to rise

from 10% of the average amplitude to 90%
have
already noticed the relationship between pulse

period and the pulse duration. The duration
of a pulse
amount
trailing
by other descriptive names such as build-up

time and decay time.) The rise time is that
waveforms are extremely impor-
tant to the study of logic.
instantaneous
small
and
leading
that the
not
theoretically
Examination of this
practical pulse.
pulse duration
Figure 4-4 represents
the top of the pulse
Referring to
contains
the part of the
curve labeled leading edge extends from the
the
fall
some
is
not actually
variations.
EDGE
LEADING
EDGE
4-3
Pulse
30
rise
Waveform
but
time and
time are not necessarily equal.
TRAILING
Fig.
The
flat,
BASIC WA VEFORMS
EXPERIMENT 00100
ELECTRONICS/DIGITAL
AVERAGE
AMPLITUDE
FALL TIME
RISE TIME
Fig.
Two
4-4
Practical Pulse
The
other terms are important to the
relationship for the duty cycle
is
study of pulses. These are the pulse repetition
frequency and the pulse repetition

difference
rate.
between these two terms
whether or not the pulses

periodic.
The term PRF
frequency)
is
in
The
lies
Duty Cycle = (T d (PRF) (100)
in
question are
This equation can also be written as
(pulse repetition
used to designate the occurrence
*
o
Cycle =
% Duty
o/ r>
of pulses at a periodic rate within a given time.

Pulses that are not periodic are designated
term PRR. This term gives the average

number of pulses during a given length of
The
relationship of the
to total pulse period
is
given
PRF
in
(or
Pulse Duration
- r-r
-=.
Pulse Period
In cases
where the pulse
smaller than the total
PRR)
*
Duty
y Cyc
y
/->
i-n
Pu
is
se off
In
pulse repetition frequency
in
Q
4.9
handy when using
making measurements.
approaching the
discussion
of
tri-
and sawtooth waveforms, another

wave shape must be described. This
It is
wave shape is the ramp waveform.
angular
pulses/sec
basic
in
time
especially
the oscilloscope for
pulse period
50 times
Pulse on time v inn

=
X 100
jrr-
This equation
(4.6)
Tp =
at least
can be written
PRF =
is
period, equation 4.8
equation 4.6.
o/
where
i
(4.8)
v
X inn
100
by
the
time.
(4.7)
seconds
31
EXPERIMENT 00100
straight
that starts at zero
line
any
(or
positive or negative voltage) and has a slope
that
is
ELECTRONICS/DIGITAL
BASIC WA VE FORMS
other than horizontal or vertical.
increases or decreases at a constant rate.
It
When
not equal while the amplitude remains

constant, the resulting wave is a sawtooth. It
is
repeated at a constant rate, the
it
sequence
result
is
is
shown
is
a triangular wave.
triangular
wave
usually
(the
fall
for the
desirable
negative
time) to be as short as possible.
actually approaches a step.
time does, however, occur.
sawtooth waveform.
in figure 4-5.
where the slopes and time
are
ramp is followed by a negative

a
ramp of the same absolute slope and this
positive
cases
In
duration for the positive and negative ramps
finite fall
Figure 4-6 shows
sawtooth
Practical
is
over 10
One other wave shape remains
to com-
waves often have a

times the
plete
ramp
Thus
fall
our
This basic
rise
time that
time.
of
discussion
waveform
is
basic
waveforms.
called an exponential
The exponential waveform gets

name from the equation that represents it.
waveform.
its
An example
of an exponential function
is
the
voltage equation
RISE TIME
Fig.
The
4-5
rise
Triangular
time and the
Wave
fall
e=
Ee
t/T
time of a
The graph of
wave afe equal. Triangular waves

may be pulse types which do not change
triangular
this equation
decreasing curve of
waves can
is
a constantly
negative slope.
from a
Expo-
resistance-
direction or alternate in direction with the
nential
average value of amplitude for one period
capacitance time constant.
equal to zero.
either positively increasing or negatively de-
Fig.
4-6
Sawtooth Wave
32
result
The curves can be
EXPERIMENT 00100 BASIC WA VE FORMS
ELECTRONICS/DIGITAL
Fig.
4-7
Integrated Square Wave
creasing exponentials. Figure 4-7

of a
wave made up of
and
is
wave
is
form
in
an amplifier
tends to differentiate the
circuit
Such
a case
is
Some
circuit.
coupling
shown
4-9.
other waveforms appear
selected examples are
They
are
shown
trapezoidal
Staricase
many
and
in
figure
staircase
waveforms are used
extensively in digital applications for counting.
(B)
4-9
in
For the most

waveforms are made up of different
waveforms.
in figure 4-8.
Fig.
Wave
combinations of the four basic waveforms.
form occurs when a
this
signal.
part these
the result of attenuation of the high
frequency harmonics
Differentiated Square
different types of equipment.
This type
The reverse of
4-8
Many
an example
this type of basic
an integrated square wave.

is
Fig.
(A)
Trapezoidal Wave
(B)
Staircase
33
Wave
ELECTRONICS/DIGITAL
BASIC WA VEFORMS
EXPERIMENT 00100
MATERIALS
Oscilloscope
1
1
Function generator capable of pulse waves
mF capacitor
1H inductor
0.1
PROCEDURE
Set up the oscilloscope for waveform viewing.
1.
Be very sure to use
a properly calibrated
probe.
2.
with a
Adjust the function generator to produce a waveform
3.
Measure and record the time duration.
4.
Measure and record the period and frequency.
5.
Calculate and record the duty cycle.
6.
Measure and record the
your
rise
time of the leading edge.
50% duty
cycle.
(The lab instructor should verify
results.)
7.
8.
Identify the
fall
trailing edge.
time of the
wave shape and sketch
it.
(Sketches from the oscilloscope must have
horizontal and vertical scales shown.)

Place a 0.1 juF capacitor
in figure
signal generator to
from the output of the
ground as shown
4-10.
'"
J_
SIGNAL
GENERATOR
O
Fig.
4-10
The Experimental Circuit
10.
1 1
rise
time of the leading edge.
2.
fall
time of the
3.
4.
Replace the
5.
16.
1
7.
dentif y the
Identify the
waveform and sketch

0.
fif capacitor
its
with a
waveform and sketch
its
trailing edge.
appearance.
H inductor.
shape.
Then remove the
inductor.
approximately 1 0 Msec pulse duration.

Set the function generator for 1 0 kHz pulses with
Compare this value as read on the generator dials with that from the scope.
34
EXPERIMENT 00100 BASIC WAVEFORMS
ELECTRONICS/DIGITAL
Measure and record the PRF.
18.
Compare
this value with that indicated
by the function
generator.
Sketch the waveform.
19.
Waveform
Period
Freq
Period
Freq
Set
Set
Read
Read
Td
50% DC
0.1 ixF
CAP
Parallel
Inductor
Parallel
10 KC Pulse
Td = 10 /usee
Sketch of
First
Waveform
Sketch of
Second Waveform
Fig.
4-11
The Data Tables
35
% DC
Tr
TF
Identity
of
Wave
ELECTRONICS/DIGITAL
EXPERIMENT 00100 BASIC WA VEFORMS
Sketch of
Third Waveform
Sketch of
Fourth Waveform
Fig.
4-11
The Data Tables (Cont'd)
you should consider the properties of the different

waveform and make some comments about
waveforms. Consider the effect of capacitance on a
waveform.
comparisons. Similarly discuss the effect of the inductor on the
ANALYSIS GUIDE.
In analyzing these data
the rise time
PROBLEMS
1.
A certain
2.
What kind
3.
waveform has
of
a period of 4.14 ms.
What
is its
frequency?
wave contains only odd harmonics of the fundamental frequency?
certain pulse has a period of
ms and
a duration of 0.15 ms.
What
is its
duty cycle?
4.
time of 1.0 ms.

narrow pulse has an "on" time of 1.5 us and an "off"
the
% duty cycle
in this case?
36
What
is
experiment
INTRODUCTION. With
circuits
00101
the development of solid-state electronic devices,
have also been developed.
In this
experiment we
will investigate
high-speed logic
the characteristics of a
transistor as a large signal switch for use in electronic logic circuits.
DISCUSSION.
Basically, there are
of bipolar transistors.
They
two types
are the
This equation holds for either
PNP and
type transistors.
The schematic of each of these

types is shown in figure 5-1. It is easy to tell
the types apart if we remember that the
emitter arrow always points toward the N
material. The three transistor currents are the
NPN
types.
is
The
NPN
from one to the other.
reversed
That
flows into the

flows out.
PNP
device while the
E current
current directions.
In the
NPN
type, Iq and
and the base current lg.
current flows
In a transistor the
by
both
'e-'c
(5.1]
in.
PNP and NPN
tion of flow
,
and
Iq.
Equation 5.1
Transistor
Symbol
t'.
5-2
Transistor Current
37
There are
These currents also affect
JFig.
the
valid for
which affect the values of
<6
PNP and NPN
is
transistors but the direc-
must be appropriate.
a\so leakage currents
lg
Fig. 5- 1
is,
Figure 5-2 demonstrates these
lg flow out of the transistor while
PNP
assuming electron flow, the Iq and lg current
collector current Iq, the emitter current lg,
three currents are related
or
direction of the current
ELECTRONICS/DIGITAL
EXPERIMENT 00101
-OOUT
CEO
IN
Fig.
5-3
PNP Common
Emitter Configuration
Another leakage current from
because of the relationship given in equation

Perhaps the most important of these
5.1.
leakage currents
from collector to
is
to emitter, called
\qqq, the leakage current
is
is
base.
tends to increase Iqq.

controlled, thermal
Under these conditions the Iqq

conform to the diode
(I
CB q) that flows must
the device
junction.
PN
'CEO
amount
-
emitter-base junction causes extra heat which
applied to the collector-base
characteristics of this
can also occur
larger than Iq B q by an
approximately equal to the current gain of

The extra current through the
the device.
The emitter-base junction is normally

A
forward biased as shown in figure 5-3.
reverse bias
usually
IcEO
collector
may
point from
5-4
PN Junction
Diode Characteristics
38
is
not
Base bias
prevent the
changing significantly
-E
Fig.
condition
be destroyed.
changes.
in figure 5-4.
this
runaway can occur, and
frequently added to
junction, as indicated
If
is
operating
when
Iq
Bq
EXPERIMENT 00101
ELECTRONICS/DIGITAL
IN
'cc
Fig.
5-5
Common
Base Configuration
The value
Three different configurations (or connecting

either
the
5-5.
of a^
usually very near unity.
is
methods) are frequently used with
The
type of transistor.
first
of these
The
shown in
is
common-base connection shown in figure

The same circuit can be used for a PNP
transistor
by reversing the battery
common-emitter
figure 5-6
is
configuration
second frequently-
encountered arrangement.
polarities.
For static conditions, the current am-
The
static current amplification factor
can be determined
plification factor
by the expression
a = 7TT|
(j3
is
ing the collector current
determined by divid-
by the base current.
(5.2)
CO
'c
(5.4)
On the other hand, the dynamic current

amplification factor a^
is
given by
For the dynamic condition,
(5.3)
(5.5)
-OOUT
IN
o-
V B8
'cc
1
Fig.
5-6
Grounded Emitter Configuration
39
ELECTRONICS/DIGITAL
EXPERIMENT 00101
-O OUT
O
IN
'cc
BB
5-7
Fig.
handy relationship
(3f e
This relationship
Common
The
Co/lector Configuration
Characteristic curves can be determined
between a fe and
exists
each of the three basic transistor con-
for
is
The curves
figurations.
for the
common-
base and common-emitter are the most useful.
The CB input
(5.6)
versus
characteristic
with
having a
gain, 0,
is
usually higher,
when
value of 20 to 200, which causes the
power gain to be
is
relatively high (the highest
l^
known.
third configuration
fication factor can be
is
the
common
The current
arrangement.
from
ampli-
both
in
in finding
is
value
its
is
determined by
and
known.
when
(5.7)
the
V^g
when V^g
Ijr
these values cor-
cases,
shown
V EB
finding
Vq B
The
The
figure 5-8.
in
projected
perpendicularly
axis to the curve and then from the
curve to the axis of the unknown.
Al.
Al
In
method used
known
collector
known, or
is
respond to constant values of
of the three, CB, CE, CC).
The
is
a plot of
The value of
fixed.
input characteristics curve
The current
is
give
value
for
value
is
is
Points B and X' give a value for
V EB
(Points
V EB when
given.)
Notice that the current amplification factor

for
j3f e
the
common
or one more than the amplification
1,
collector
configuration
is
allows the
common emitter
common collector
to have a
higher current gain than a cor-
responding
common
factor of a
since
afe
<
j3
fe
the
circuit.
configuration
emitter circuit.
common
This
<
i
And
collector con-
figuration has the highest current gain of the
At the same
three configurations.
has the
configuration
because of
its
atively lower
low
power
lowest
voltage
resistance gain
gain.
Its
time, this
and
gain
rel-
voltage gain
V EB VOLTS
is
usually approximately equal to one.
Fig.
40
5-8
Input Characteristic Curve for
CB
EXPERIMENT 00101
ELECTRONICS/DIGITAL
<
<
on
V EB VOLTS
V CB VOLTS
Fig.
base
is
5-9
V^g
when two elements
istic curve for a CE circuit.

This is not the
only curve that can be drawn to show the
input characteristics, but it is one of the
are
known, the third can be found. For instance,

if
VQg
is
given as
volts
mA, then projecting

the
V CB
and lg
most
useful.
given as A'
a line perpendicular to
axis out to the
locates point Q.
is
CE
Figure 5-10 shows the input character-
versus \q for fixed values
appear as a family),
Input Characteristics of
of the other values.
Using these curves (which usually
lg.
10
from point Q to the Iq axis locates point X.

The reverse procedure would identify either
Characteristics
The output characteristics of a common

circuit are shown in figure 5-9. This curve
plotted with
of
CB Output
Fig. 5-
= A'
E
mA
Figure 5-11 shows the curve that would
line
normally be obtained with a transistor curve
Projecting perpendicularly
tracer. In this family, the lg curves are parallel,
U3
K
_l
O
>
LU
m
>
V CE VOLTS
Fig. 5- 1 1
Curve Tracer Input Characteristics of
41
CE
ELECTRONICS/DIGITAL
EXPERIMENT 00101
<
E
=
B
0mA
V CE VOLTS
Fig. 5-
tend slightly upward, and become closer at

the top. This family is similar to the family
shown
figure 5-12,
in
CE
Output Characteristics of
12
suitable
is
chosen,
it
can be used to
calculate the load resistance.
but the nonlinearity

Hi _
has been omitted for simplicity.
V
_cc_
i
Cmax
These characteristic curves are very important
the
in
The DC load
circuits.
the normal
of
design
manner.
constructed
line is
If
switching
logic
in
certain parameters
are required, these are used as starting points.

is predetermined, this
For instance, if
V cc
becomes the
resistance
is
intercept.
When
the load
intercept
predetermined, the
can be calculated from
-Ycc
'C
The
max
intercept
satisfies this
R,
is
the value of
equation.
R L can be
c which
selected by
of
using the assigned (or chosen) value
load
of
family
a
for
as the end point
Figure 5-13 demonstrates this
V cc
lines.
method. When
Fig. 5-
42
13
Choosing Iq with the Load Line
EXPERIMENT 00101
ELECTRONICS/DIGITAL
"OFF" REGION
5-14
Fig.
Load
lines for
ON and OFF
switching transistor ap-
contains
plications are not so critical as are those for
class
spends most of
its
time
in
the
ON
These regions are shown
regions.
This
transistor
and
while
OFF
this
in figure
This region
is
flowing,
past cutoff.
transistor
The
the
develops
if
Because
in this
it
region,
our load
is
DC power supplies
VOMsor FEMs
PNP
Transistor socket
transistor,
kft,
33
2W
kft,
no problem usually
collector dissipation curve.
off).
active region
(0-40V)
type 2N1305 or equivalent
resistor
1/4W
resistor
2 Sheets of linear graph paper
PROCEDURE
1.
Connect the
circuit
shown
in
fall.
figure 5-15.
43
Be careful about the
only operating
line crosses
MATERIALS
2
curves
where a
very briefly
current
where
area
class A amplifier would

The switching transistor only crosses
region when it is changing from one state
is
to the other.
is
base
the
operate.
ON region often called saturation,

= 0
the OFF region falls below
B
The
5-14.
(no
The
amplifier operation.
Regions of a Transistor
polarities.
the
maximum
ELECTRONICS/DIGITAL
EXPERIMENT 00101
DC POWER
SUPPLY
Fig. 5-
2.
3.
Set the base current
First
zero.
current (l c ) for a series

Holding the base current constant, measure and record collector
to 12 values from zero through
of values of collector-emitter voltages (V CE ). Pick 10
20
4.
B to
The
15
volts for
V CE
and 140 ^xamps.

Repeat step 3 holding the base current constant at 40, 60, 80, 100, 120
run.
data
Be certain the base current remains constant during each
5.
On
6.
Disassemble the
7.
Assemble the
a single sheet of
graph paper, plot the curves.
circuit.
circuit
shown
in
figure 5-16.
VARIABLE DC
POWER SUPPLY
Fig.
5-16
volt to the collector
8.
Apply -1 .0
9.

holding
The Second Experimental Circuit
V CE
V BE
CE ).
values for
0, 10, 20, 30, 40, 60, 80, 120,
constant at -1.0 volts.
10.
Repeat step 8 for
11.
On
V CE
values of -5.0, -10.0, -20.0 volts.
of the device.
a sheet of graph paper, plot the input characteristics
44
160Mamps,
EXPERIMENT 00101
ELECTRONICS/DIGITAL
40
60
80
100
120
140
'c
'c
'c
'c
'c
B /xA
Vqe
volts
o
2
4
6
8
10
12
14
16
18
20
VCE
l
B Ma
-1.0V
-5.0V
-10.0V
-20.0V
V BE
V BE
vBe
V BE
0
10
20
30
40
60
80
120
160
Fig.
5-17
The Data Tables
45
ANALYSIS GUIDE.
should be paid to the conclusions

In analyzing these data, careful attention
to switching circuits.
the transistor characteristics as they apply
drawn regarding
The graphs should show the saturation region and
that can be
discussion?
If
yes,
ELECTRONICS/DIGITAL
EXPERIMENT 00101
how?
If
no,
cutoff.
Did your curves resemble those
in
why?
PROBLEMS
1.
Select a suitable
V cc
and draw
load line so that the transistor will operate
DC
the proper region for switching.

2.
Calculate the value of
3.
Given
V cc = 12V
RL
in
problem
1.
and R L = 10k, find c using your curves.

l
46
in
the
experiment
INTRODUCTION.
DESIGN OF THE TRANSISTOR

SWITCH
00110
Transistor characteristics are the same
However, when the device
application.
is
taken into account that are usually disregarded in class
examine some of the parameters
DISCUSSION.
In
operating point
is
Care
point for
maximum
is
the
regardless of
less)
some considerations must be
operation.
In this
experiment we
shall
for a transistor switch.
the
amplifier
tion
selected near the center of
the active region.

this
class
(more or
to be used as a switch,
This
is
Iqq
biased.
taken to choose
linearity.
and the emitter-base junction are reverse
It
the collector leakage current.
is
flows across the collector-base junction and
must be canceled by
not
which
an important consideration in switching ap-
is
a reverse bias lg
OFF'
equal to the Iqq.
plications.
When
In a
normal switching
circuit,
the operat-
operating
must approach
transistor
fall at one
The upper extreme
ing point for the transistor will
nearly
extreme of the load
operating point to
of Iq
is
line.
termed the saturation region, and the
lower limit of Iq
as
region,
which are used repeatedly
The
logic circuits.
operating
saturation
first
is
in
these regions
When
defined
ON
given
it
in
is
is
is
ing
point that
To
said to
resistance
actually
the
is
to
input
signal;
ON
is
is
discussion
must be
is
a tube, transistor, or even a
resistance
application and
is
is
The
ON
ratio of the
important to any switch
very important
when
eval-
uating transistors to be used as switches.

is
It
practical to expect switching transistors to
ON
resistances of under 10012 and
resistances higher than
OFF
two
OFF
10 million ohms. The
resistance values can be determined
by
cut off with no
means that the device
normally conducting
to
when it is open and a very low

when closed. This is true whether
switch
OFF
have
further specify these conditions:

is
minimum
beyond
mechanical contacter.
possibly can under
the cutoff region.
means that the device
may be
saturation
high resistance
The other possible

is OFF. When
termed OFF, it has an operat-
is in
edge of the
that a reliable and efficient switch
so
conditions.
is
just at the
but rather well into the
The point of the foregoing
the
condition for a transistor switch

the transistor
short circuit as
do not want the
provide reliable switching.
the
that the transistor
is
conducting as hard as
the
What
or "normally on."
happens physically
when
the device
operated, the steady-state condition

be
condition, the
discussions of
point of the transistor

region.
fall
ON
For this reason, lg
region.
increased
Two terms arise dealing with
We
possible.
saturation
called the cutoff region.
is
in its
when no
is
input signal
(6.1)
applied.
In the off condition the transistor

act as
much
To achieve
like
this,
should
(6.2)
an open circuit as possible.
both the collector-base junc-
47
ELECTRONICS/DIGITAL
TRANSISTOR SWITCH
EXPERIMENT 00110
INPUT
Fig. 6- 1
Circuit
Fixed Bias Transistor
to many things
These changes are due
temperature. Fixed
cluding shifts in ambient
demonstrate and easy to
bias is easy to
is a good
For these reasons, it
calculate.
discussion. The value of
starting point for our
in-
Ohm's Law
value
the
of the point
coordinates
determined by the
the saturation
where the load line crosses
corresponds
The OFF resistance
boundary.
0
the point where B =
to the coordinates of
This is the
intersect.
and the load line
boundary of the cutoff region.
ON
The
resistance
is
the fixed bias resistor
is
(6.3)
the transistor as a
In order to operate
switch,
we must
Figure 6-1
learn to bias
shows
transistor switch.
it
appropriately.
fixed bias
a circuit for a
The
f ixed bias circuit
least effective.
simplest and often the
is
the
It .s
Its mam
seldom used.
compensate for changes in
that it does not
which will cause a
transistor parameters
fault
actually very
is
the
corresponding shift
in
the operating point.
In this
caseV BE and B
l
are the values of the
point.
zero signal base operating
operating
the
The problem of holding
overcome by
point fixed is somewhat
ing
some
apply-
in figure 6-2.
self-bias, as illustrated
'cc
Fig. 6- 2
Cirucit
Self Biased Transistor
48
ELECTRONICS/DIGITAL
EXPERIMENT 001 10
Rg
&3
Fig.
Voltage Divider Bias Transistor Circuit
supplies a varying bias to provide
Q-point
resistor
Rg
lector
operating
signal
Of Stabilized Bias
Equation 6.6 is used to choose the

other base resistor R B1# where the voltage
drop across Rg2 is subtracted from the col-
bias
can be found using the values as
ordinates of the zero
the
some
The value of the
stability.
TRANSISTOR SWI TCH
supply and divided by a current
equal to the
point.
sum
of
x and the base current of
the operating point with zero signal.
This
system overcomes the inadequacies of the two
The voltage divider bias method provides

even more Q-point stability.
This method
is shown in figure 6-3 and is sometimes called
"Voltage divider"
stabilized bias.
name
an unfortunate
In
transistor
we
applications,
no
is
bias.
different.
Rg2
bias resistor
is
at
probably
usually
in
providing bias currents
the collector-base junction
the emitter-base junction.

region
for this arrangement.
concerned with current

situation
is
previous systems
(transistor
as well as to
In the saturation
ON), the base voltage
greater than the collector voltage,
are
and
is
this
produces forward bias on the collector-base
Actually, this
junction.
The base-emitter
chosen by
Figure 6-4 represents the principal current flow paths associated with the transistor,
Rg2
Vgg
is
signal
(6.5)
the base-emitter voltage at the zero
point,
and
is
a value
chosen to be
equal to or larger than the base current at the
cc
zero signal point.
_
p
"B1
V CE- V RB2
i
(6.6)
Fig.
'z
49
6-4 Current
Flow in
the Transistor Switch
ELECTRONICS/DIGITAL
TRANSISTOR SWITCH
EXPERIMENT 001 10
STORAGE TIME
DELAY TIME
FALL TIME
RISE TIME
&5
Fig.
remembering
that
any
in
time.
The B
to the base of the device.
pulse
Thus,
effective start of the transistor turnoff.
The
pure square wave of current to the base.
Vq^ waveform shows what
is
represented actually by a time delay
It is
between removal of the lg current and the
Let's apply a pulse (see figure 6-5)
transistor.
resulting
B Vqe Waveforms
the device
said to have stored the lg pulse
is
for a short period of time.
happens
Important are the
to the collector voltage.
delay time (time required to reach 10%) at the
beginning of the
V CE wave
time (between
and 90%) points on the
10%
and the
leading edge of the curve,
(between
90% and 10%) on
One other time

This
is
for
trailing
the
90%
delay
curve
point.
edge and
to
This
when the
fall
is
The
is
storage time
100%
When
is
base material.
on to off
ment
carriers to
is
start
until the extra carriers are
in
the transistor
storage time
the
is
is
time
is
method of
to use
reducing
to clamp the transistor so that
In
extremely high speed switching
applications, the device
tor-
rise
does not go very far into the saturation
region.
may
be operated only
to the extreme points of the active region on
flow into the
The switch cannot
tech-
much improveresponse. One common
base overdrive, and a
a transistor goes into
saturation, the collector-base junction
ward biased, allowing
in
However,
any waveform.
technique for shortening
to the
operated
would be impossible to exactly
it
niques do exist which allow
is
the time required
from
devices,
reproduce
often a significant time
transistor
saturation region.
all
the trailing edge.
needs explanation.
period
the storage time.
on the
time
fall
not nor-
is
mally a truly faithful reproduction of the lg

Because of nonlinearities within
waveform.
the rise
activities of the transistor,
internal
The output waveform Vq^
caused by the
from
removed
from the base region to the collector. The

time required to do this is called the storage
the loadline.
This type of operation
complex and
gives the
given value of
Vqq. Such operation
full-driven operation.
50
is
quite
lowest output for a

is
called
EXPERIMENT 001 10
ELECTRONICS/DIGITAL
Fig.
A
is
6-6
Base Overdrive Circuit
circuit for the base overdrive operation
shown
in figure 6-6.
This circuit provides a
and thus speeds up the
Vg^
known.
figure
differentiated burst of current at the start of

the pulse
TRANSISTOR SWITCH
6-7.
determine
can be found as illustrated
Once Vg^
is
in
known we can
Rg by
rise time.
good system if we can determine

Rg, R|_, and Cg.
This seems a
values for
One method
is
RB
V BE
required for lg
the
it
AV
on can be determined
with the input characteristic curve.

either be given or
(6.7,
of calculating these values
to utilize the transistor characteristic curves.
The
-if'B on
Ig
on
is
the difference between the
value of the input pulse and the
will
maximum
Vg E
can be found by use of
output characteristic curves
if
Vqq
AV
is
V inmax- V BEon
V EB V0LTS
Fig.
&7
Determining
51
Vgg
<*8)
Since
desired
the
capacitor
overdrive current,
through
CB
will
ELECTRONICS/DIGITAL
TRANSISTOR SWI TCH
EXPERIMENT 00110
to
is
supply the
the current
equal the
B on
equation for
It
'CB
_l Bon
is
also
is
possible
At
the desired turn-on time.
Solving this
(6 10)
-
to
When Rg
experimentally.
(6.9)
determine
is
in
the
Cg
circuit,
placed
different values of capacitance can be
across
At
yields
'Bon At
cB =
"av
CB
current.
C B AV
Cg
until
it
the
required
rise
time
is
obtained.
MATERIALS
- 10 meg)
2 Resistance substitution boxes (15ft
equivalent
or
Transistor type 2N 1 305
1
1
Transistor socket
DC power
Set of characteristic curves for
2N1305
supplies (0-40V)
transistor
Function generator
Capacitor substitution box
PROCEDURE
1.
required R L for
Using the transistor curves, calculate the
2.
Construct the circuit shown
V cC
6V and c = 4 mA.
l
in figure 6-8.
2N1305
R,
=?
OSCILLO-
SCOPE
6 VDC
rum
IV
Fig.
Apply
2V
6-8
The
First Experimental Circuit
peak-to-peak square wave to the base.
Record the period, frequency, and
pulse period of the input.

4.
Observe the output on the scope.
5.
appropriate parts: delay time,

the wave shape carefully and label the
duration, storage time, and fall time,
Draw
52
rise
time, pulse
EXPERIMENT 001 10
ELECTRONICS/DIGITAL
6.
Measure and record each of the times
7.
Calculate
8.
Wire the
Rg
Rg
step 5.
for a base overdrive circuit for the experimental circuit.
into the experimental circuit as
Fig.
9.
in
TRANSISTOR SWITCH
&9
shown
in figure 6-9.
Observe the output with the scope.
Record the
rise
time,
fall
time and pulse duration.
Carefully sketch the waveform.
10.
Observe point
and
fall
11.
Calculate
12.
Install
13.
Cg
in
the circuit of figure 6-9 with the oscilloscope. Measure and record
rise
for base overdrive of this circuit.
the appropriate Cg.
Change the capacitance to

calculated Cg.
ANALYSIS GUIDE.
the
time. Carefully sketch the waveform.
Repeat steps 9 and 10.
a value three steps
above and then three steps below the
Repeat steps 7 and 10 for each of these two new values.
In analyzing these data,
you should examine the parameters measured
experiment and discuss their importance to switching applications.
values with the values arrived at experimentally
and empirical methods.
The
in
Contrast the calculated
and comment on the accuracy of the calculation
saturation and cutoff regions for this circuit should be identified
on the characteristic curve.
53
EXPERIMENT 001 10
TRANSISTOR SWITCH
CALCULATIONS R L
Waveform
RB
CALCULATIONS
Fig.
6-10
The Data Tables
54
ELECTRONICS/DIGITAL
ELECTRONICS/DIGITAL
FIRST
EXPERIMENT 001 10
DELAY
RISE
PULSE
STORAGE
FALL
TIME
TIME
DURATION
TIME
TIME
CKT
OUTPUT Rg
POINT X Rg
m
rUIT
UUITPI
1
R P
r>gL.g
POINT X
R BCB
OUTPUT
Steps
(Three
Above
CB )
POINT X
(Three Steps
Above Cg)
OUTPUT
Steps
CB
(Three
Below
POINTX
(Three Steps
Below C)
Output Waveform
with
Rg
in
TRANSISTOR SWITCH
the
circuit
Fig.
&10
55
EXPERIMENT 001 10
Waveform
Point
TRANSISTOR SWITCH
at
with
Rfj in the
Circuit
C R CALCULATIONS
Output Waveform
with
CB
in
the
Circuit
Fig. 6-
10
56
ELECTRONICS/DIGITAL
EXPERIMENT 001 10
ELECTRONICS/DIGITAL
Waveform
Point
Cg
the
in
at
with
Circuit
Output Waveform
C Three
Steps Above Cg
with
Waveform
Point
at
with
Three Steps
Above Cg
Fig.
& 10
57
TRANSISTOR SWITCH
EXPERIMENT 00110
ELECTRONICS/DIGITAL
TRA NSISTOR SWI TCH
Output Waveform
With C Three
Steps Below
Waveform
Point
Cg
at
With
C Three Steps
Below Cg
Fig.
6-10
PROBLEMS
1.
Calculate saturation
for a transistor operated with
V cc
= 30V and the R|_
= 180CK2.
2.
Draw the
equivalent circuit for a transistor
reasons for thinking

3.
Draw the
it
is
the saturation region.
in
the cutoff region.
Explain your
to be reasonable.
equivalent circuit for a transistor
think your circuit
in
reasonable.
58
Explain
why you
experiment
INTRODUCTION. The
we
diode
(fill
frequently encountered
is
examine some of the ways that
will
DIODE CLIPPERS
I I
this device
is
In this
logic circuits.
in
experiment
used to perform the job of adjusting and
polarizing an input signal.
DISCUSSION. Diodes and transistors are both
half cycle of the input
used to "sort out" pulses for input to digital
positioned as
These devices can be used
in
dif-
ferent circuit configurations to polarize
and
They can
also
circuits.
set
the level of input pulses.
E jn =
help shape a waveform by "trimming" off
unwanted spikes and
first
to
circuit
we
you as a half-wave
series clipper
going
circuit
passed
if
will
look at
is
is
rectifier.
shown
the diode
in
is
(7.1)
be written for the
the
simple
reverse
diode be
Using
diode.
is
(R
(7.2)
resistance
of the
diode.
It
is
is
is
It
is
also desirable that the reverse resistance of the
where
of the diode be relatively large.
ratio
Ohm's Law, we can write an equation for the

Ej
important that the front-to-back resistance
figure 7-1.
D-j.
jn
reversed) will be
by the forward biased diode

parameters
+R f
are the same as before, but

Ej
n and R|_
f
the reverse current of the diode while R r
much
circuit
(R L
negative half cycle.
Only the positive going pulses (or the negative
transients.
This circuit should be familiar
series clipper.
wave with the diode
is
equation can
similar
The
shown
the peak
much
larger
larger than the
(R r
than R|_ and also R|_ be
forward resistance of the
R L R
).
amplitude of the square wave input voltage,

If
is
the forward
diode current,
forward diode resistance, and R|_

resistance.
The equation
Rf
is
The
the
is
the load
for the
positive
circuit
in figure 7-1
only for clipping pulses at the zero
some other
in
Fig. 7- 1
shown
Series
Diode Clipper
59
clipping level
is
is
used
level.
If
desired, the ad-
EXPERIMENT 00111
ELECTRONICS/DIGITAL
DIODE CLIPPERS
2V
Fig.
dition of a series bias voltage
is
Forward Biased Diode Clipper
7-2
necessary.
Actually, the diode
By
input voltage
choosing the voltage properly, various levels

can be selected. Figure 7-2 shows a forward
bias applied to the previous circuit.
configuration, the output will be
The two-volt
original
5V
bias battery voltage
With
7V
is
is
forward biased when the
greater than
-2V and
until
it
reaches +5V. In the second case (figure 7-3),

the diode is reverse biased at 2 volts. This 2
this
must be overcome for the diode to reach

the original OV bias level. Thus, 2 volts of
volts
clipped.
adds to the
the E jn value are required to reach the zero

level and the output is the 3V that are left.
clipped output.
In the circuit of figure 7-3, the opposite
effect
is
achieved by reverse biasing the diode
with two volts.
have seen the effect of a series diode.

would happen if the diode were in
We
The output then becomes 3

What
volts clipped.
parallel with
In the case of figure 7-2, the negative
2V
circuit.
R L?
Figure 7-4 shows such a
series current-limiting
resistor
often added to protect the diode from
causes the forward current to increase.
w6
10V-
out
O
2V
Fig.
3V
7-3
Reverse Biased Diode Clipper
60
ov-
L__r
is
exces-
DIODE CL IPPERS
EXPERIMENT 00111
ELECTRONICS/DIGITAL
r-AA/\r
OV
Fig.
sive
7-4
current during the conduction.
Unbiased Shunt Diode Clipper

forward resistance of the diode should be the
During
smallest of
conduction (positive half cycle of Ej n the

forward resistance of the diode must be very
)
much smaller than the value of

is
R|_.
If
much
R|_ will
the
resistance
of
produce E Q as
As with the
clipper
half cycle to
biased
resistance
rr
is
are
of ohms.
to
series
both
be
the shunt
clipper,
forward and
produce different clipping

does
reverse
levels.
the series
The current through
circuit in that the clipping occurs
during the
a negative pulse.
conduction time of the diode because the bias
diode should be
In
alters the
7-5
The reverse
resistance of the diode should be by far the
The load
highest resistance in the circuit.
The series
resistance is the next largest.
relationships
can
This happens just as
of these circuits, the resistance
design
many thousands
in
the
greater than
differences between these
The
this
During the negative half cycle, the
ground.
reverse
short the positive
all.
values should be
the case, the diode leg of the circuit will
effectively
TTTJ
important.
much lower than
R[_,
it
conduction of the diode.
shows
action
this
shunt clipper.
in
The output
reverse
will
input.
and the
will
The
be the
positive portion of the
full
be equal
to
the
Reverse Biased Shunt Diode Clipper
61
waveform
positive value of the
-E.
7-5
biased
amplitude of the negative half cycle of the
,0V
Fig.
Figure
ELECTRONICS/DIGITAL
DIODE CLIPPERS
EXPERIMENT 001 1 1
AAAr
- ov-
in
li_t
<
^" V Bias
Bias
The Forward Biased Shunt Diode Clipper
7-6
Fig.
This happens because the diode
bias voltage.
conducts any time the input voltage
is
through the major portion of the input voltage
greater
The forward resistance

of the diode must be much smaller than R
S'
and R|_ must be much greater than R
The
s
than the reverse
forward
conduction
E
in"
Rs
(7.3)
the positive half cycle of E

jr)
equal to the bias voltage.
It
the
action,
useful.
the double shunt
It is
This circuit
used
is
shunt clipper actually reduces the
clipping action.
in
many
Figure 7-7 shows
The
sine
wave
The more severe the clipping

the more nearly square the output.
Both diodes are reverse biased.
discussion that the addition of reverse
bias to the
is
diodes.
is
can be seen from
as
"squared" by the clipping action of
is
is
R|_.
typical double shunt circuit.
input
is
which
magnitude than Vgj
square wave generators.
Rf
During this half cycle, the output voltage
this
clipper that
in
Ej
one other type of shunt diode
is
diode clipper.
if
appear across
There
through the diode during
V Bias
V jn
will
then
is
'f
where the
negative and greater
bias.
current
Only that portion of
cycle.
These biases
are equal
when
When
conducts, the output wave
D-\
the square wave
is
symmetric.
will rise
V B -|. When D2
conducts, the output voltage will go negative,
to the bias voltage value of
Forward biasing of
cuit
is
shown
a shunt clipper
in figure 7-6.
This configuration
increases the clipping action.
ward
bias
the
diode,
we
cir-
When we
to the value of
half cycle of
for-
allow conduction
AW
T
7-7
half cycle of Ej
Ik
'B1
Fig.
Vg2- So
E jn
Double Shunt Diode Clipper
62
D-j clips
and D2
the positive
clips the negative
EXPERIMENT 00111
ELECTRONICS/DIGITAL
DIODE CL IPPERS
MATERIALS
Diode,
1N645
or equivalent
2 Resistance substitution boxes (152 - 10 meg)
DC power
supply (0-40V)
Oscilloscope
Function generator
Breadboard with terminals
PROCEDURE
1.
Assemble the
circuit
shown
in
figure 7-8.
INPUT
10V
100
11
p-p
Fig.
The
7-8
First
kn
kHz, 10 Vp.p square wave to the input terminals of the clipper.
2.
Apply
3.
Connect the oscilloscope across R|_ and sketch the output waveform.
the amplitude, period, and zero reference level.
4.
Add
10V
the
2V
bias as
shown
in
Be sure to record
figure 7-9.
= 100
kn
in
2V
Fig.
5.
As
7-9
before, measure, record,

and sketch the waveform across R|_ with
square wave signal applied.

6.
Reverse the leads to the
2V
bias supply.
63
p p
kHz input
EXPERIMENT 001 1 1
DIODE CLIPPERS
ELECTRONICS/DIGITAL
7.
Measure, record, and sketch waveform data as before.
8.
Disassemble the circuit and construct the circuit shown
in
figure 7-10.
tookn
7-10
Fig.
Apply
9.
a 5
Vp_p,
The Third Experimental Circuit
kHz square wave
signal across the input.
10.
Measure, record and sketch the waveform across
11.
Add
the
2V
bias
shown
in
figure 7-11.
3.3
With the 5 Vp.p,
12.
1
R[_.
kn
Fig.
7-11
kHz
pulses applied, measure, record, and sketch the
The Fourth Experimental Circuit
waveform across
R|_.
Reverse the polarity of the bias supply.
3.
Repeat step
14.
ANALYSIS GUIDE.
2.
In analyzing
your
you should explain how the
results,
the individual waveforms were achieved.
The
levels of clipping in
action of the series and shunt clipper should be
explained using your data.
PROBLEMS
1.
2.
Calculate the forward diode current
the Fourth Experimental Circuit, Step 12.
certain diode has a reverse resistance of 10
ohms. Select R s and R|_ for

3.
in
Draw
double shunt clipper.
total voltage
megohms.
Its
forward resistance
is
10
forward bias clipper biased at -3V.

If
V Bjas
=
1
swing of E QUt ?
64
+2V and V Bias 2 = -3V, what
will
be the
ELECTRONICS/DIGITAL
EXPERIMENT 00111
DIODE CL IPPERS
First Circuit
Amplitude
=
1
Period
till
1
1
Hit
MM
Mil'
H-M-
M M Mil
MM
Output Waveform
(Show zero reference level)
Second Circuit
Amplitude
MM
MM MM MM
III!
Ml
Ml MM' MM MM
Ppriod
Output Waveform
(Show zero
reference level)
Third Circuit
Amplitude
Period
nn MM MM MM
II
III!
Mil
MM MM MM
Output Waveform
Fig. 7-
12
The Data Tables
65
EXPERIMENT 001 1 1
DIODE CL IPPERS
ELECTRONICS/DIGITAL
I
Fourth Circuit
Amplitude
H-H
Period
MM
III
ii
1
I
MM MM MM
Output Waveform
Fig.
7-12
66
-H-H-
01000
experiment
INTRODUCTION. Most semiconductor

transistor, like
we
is
devices can be used
wave and pulse
a transistor
used for clipping, and what
is
is
selection.
In this
The
experiment
meant by clamping and how
it
achieved.
A method
DISCUSSION.
many
waves
in
a sine
wave.
for obtaining square
practical systems
This can be done
is
experiment
we
will
look at
overdriving.
to "square"
in several
both transistors and diodes.
with
is
ways
of
In this
how
can
this
The
the
large
sinewave
reaches
its
in
first circuit
we
transistor clipper, its
shall
consider
schematic
is
shown
is
(but not
(or minimum) signal

waveform is said to be
load
resistance
and the
in
parameters for the transistor clipper. Equation
This circuit takes advantage of
the transistor
almost
saturation voltage are the only really critical
8.1 will yield the value of the load resistance.
cutoff characteristics of the transistor.
Actually
The
called
the input signal
and when the transistor
maximum
"clipped."
is
if
amplitude, the sides
be
will
capability the voltage
figure 8-1.
the
In this case
sufficiently
quite) perpendicular,
be done.
in
the diode, can be used for clipping and clamping waveforms.
examine how
will
TRANSISTOR CLIPPERS
AND CLAMPS
driven into both
and cutoff, which in a

would be called distortion
saturation
class
design
due to
V CC
L=i C max
AAAr
6
Q
'cc
Fig. 8- 1
The Transistor Clipper
67
(8.1)
This equation
Vqq
line.
\q
rent.
This
load line
voltage
drawn from
is
Vqq
load
saturation collector cur-
illustrated in figure 8-2
is
DC
used to lay out the
the collector supply voltage.
is
maximum
the
is
is
ELECTRONICS/DIGITAL
CLIPPERS AND CLAMPS
EXPERIMENT 01000
to Iq
where the
the collector supply
The
maximum.
lg
gAT
(base current for saturation) can be found
where the saturation knee of the characteristic
The input
can be found by
curve intersects the load
voltage for saturation
E in
SAT"
line.
R b'b SAT
(8.2)
Actually of more importance from the design
standpoint
is
Rg which
the value of the base resistor
also appears in equation 8.2.
Ig
Fig.
8-2
Clipper
Load Line
for saturation can be taken from the characteristic
curve once the load
line
is
drawn.
The
The
task then is to balance the E jn for saturation

against the Rg to swing the base waveform
from cutoff to
saturation.
of 8.2 will give the
and delay times are determined
from the time required

reach the saturation
The transposition
form for
rise
resistance
selecting Rg.
for the base current to
usually
will
The base
level.
be
emitter
negligible
when
compared to Rg, so the base current becomes
in
b"
(8.3)
The input voltage

The desired action of
this
circuit
across
is
simply on and off at the frequency of the

input sinewave, that
of the
is,
an output square wave
same frequency.
At the
signal at the base, the transistor
collector
is
at
its
fall
start
is
for saturation
(equation 8.3).
The
is
the voltage
rise
time (and
time) can be determined using the ex-
pression
with no
off and the
supply voltage.
Rg
(8.4)
rB
E in
After
SAT
V max
sin
2 *
(8.5)
fx
applying the signal, the negative half cycle
Both the load
drives the transistor to saturation, decreasing
the
output voltage value to almost zero.
resistor
During the positive half of the input cycle the

reverse- biased
input
is
mains
off.
When
and the output
fall
have an
the
rise
The base current required
times.
saturation
re-
and the base
resistor
influence on
is
transistor is on and the voltage

n g A y, the
at the collector goes almost to zero.
of
Ej
input
voltage
required
base saturation current.
68
for
established by the load resistor,
while the base resistance determines the
the input signal reaches
and
to
level
produce the
EXPERIMENT 01000
ELECTRONICS/DIGITAL
CLIPPERS AND CLAMPS
Bias
'CC
BE
Fig.
The
effect of the input frequency
cause a decrease in rise
and
increase in frequency.
The end
trend
fall
in transistor
may seem
how
with
However,
long
when you
operations that a computer must
very fast action
The
is
short
when the
junction
is
to
carriers
worsens as the device
the turn-off
best
way
is
transistor
In
from going deep
order to do this
diode clamp.
we can
This clamp
up the base
to
region.
will
With few
remove, the device
OFF
once the
is
signal
is
is
re-
considerably
will
more
clearly
demonstrate the diode collector clamp
idea.
In
Vqq
the
this circuit the supply voltage
is
= Vgj + The forward drop of the diode

as
(8.6)
base
which says that the
in
This con-
Vqq q N
voltage will
never decrease below the value of the diode
driven further
forward drop added to
its
own
bias voltage.
This gives us a method for setting the col-
to prevent the
The object is to
vent the base-collector from becoming
ward biased.
This means that the
into saturation.
voltage must be chosen such that the con-
lector
sensible that the

is
The
never become
majority
In other words,
It is
to prevent this
operating
region.
reduced.
time becomes a function of the
degree of saturation.
fill
carriers
moved and the turnoff time
collector-
must be removed
and further into saturation.
will
ON
Examination of figure 8-3
into
order to turn the transistor off.

dition
active
of time,
biased,
pass
pre-
allowed to go
is
Anytime the
forward
are allowed
These
device
the
junction
ready to switch
indeed required.
deep into saturation.
region.
majority
turn-off time of a transistor switch
increased
carriers
periods
inside
not tend to
consider the millions of
relatively
in
be able to hold the
just
setting this level properly
forward biased and the majority carriers
so con-
make
beyond
drop
to
By
level.
collector-base
takes to switch.
it
will
point
fre-
switching
base
we
switch applications.
we would be
voltage
determined
strange that with a device as
rapid as the transistor
is
collector
to
limit of this
The problem of switching time
quently arises
cerned
is
times with an
the value of the transistor switching
is
time.
It
Diode Collector Clamp
8-3
use
will
what
is
clamp
voltage.
ducting collector-emitter drop
called
not allow the
larger
69
is
prefor-
bias
always much
than the base-emitter voltage.
The
ELECTRONICS/DIGITAL
CLIPPERS AND CLAMPS
EXPERIMENT 01000
-o _v cc
xr
'1<
8-4
Fig.
diode
is
Practical
problems develop with this circuit although it is better than a saturated

switch. First of all, the recovery time of the
Several
emitter voltage decreases to the diode bias

voltage
At
level.
point
that
the
C1
Diode Collector Clamp
except when the collector-
at cutoff
diode
limiting factor.
The
circuit can
conducts and decreases the collector-emitter
diode
voltage to the value of the diode bias plus the
never be faster than the diode recovery plus
Eq E q N
than E BE
larger
is
must be dissipated by the
much
Then
still
at
portion
V CE ON
V Bias
(8 7)
v DiodeFD" V CE ON
(88)
V Diode FD
lector
shown
is
collector clamping level

divider
in figure
is
This
Ri and
8-4.
level
is
VC 1
When no
output
signal
rises
to
is
R-l
circuit.
1
(8.9)
as
potential
it
R s ).
is
go
70
our
simple
collector
Vq E
is
the signal-diode
to
is
Th
back
This circuit
figure 8-5.
when employing
base over
the output square wave
supplied by the overdrive
begins to decrease toward zero
reaches the value of E in (the drop across
The diode
change
Vq<j.
in
To improve
drive.
present at the base, the
the clamp
in
particularly useful
the value
+ R2
\q
the extra
to accomplish this
used
is
saturation,
V CC R
value and
and thereby control
clamp shown
by the voltage
set
approach
The
of
One way
clamp.
practical circuit for diode col-
clamping
transistor.
diverted through the diode.
is
control
A more
maximum
its
disadvantages
the
V Bias
that
Other techniques exist for the design of

nonsaturated switches that, in part, overcome
'
or
is
wastes current and this current
circuit
the
of the diode bias voltage can be determined by

selecting voltages so that
The second drawback
circuit recovery.
The proper value
forward drop of the diode.
is
in
will
the bias.
around
the
conduct because of
This will
overdrive
let
the
part of \q
circuit
and
the
EXPERIMENT 01000
ELECTRONICS/DIGITAL
8-5
Fig.
transistor (a sort of
bypass
This
Since the diode
oppose the incoming \q and prevent it

from rising beyond that instantaneous value.
lg will
The collector current Iq
equal to the
The current through the load
bypass,
in
put,
|3flg.
across
V clamp
V CE
we
resistor
is
has
can use
-o
has
drop across diode (8.10)
slightly
modified version of figure 8-5
all
the same parts as the previous one
been
placed with
8-6
characteristic
Double Diode Clamp

71
silicon
diode.
diode was chosen here because of
A/NAr
Fig.
not seriously
except that the base series overdrive resistor
(desired)
V forward
does
employing two diodes. Such a double diode

clamp is shown in figure 8-6.
This circuit
silicon
time
Another approach for collector clamping
not directly across the out-
/3f
the
The clamp voltage is set by the value

R s in conjunction with Ej n In order
choose the clamping voltage,
is
recovery
its
affect the circuit.
be more-or-less constant and equal to
will
to
is
the transistor plus the excess lg
of
Back Clamp
Single Diode
relief valve).
CLIPPERS AND CLAMPS
voltage
drop
(from
A
its
0.5V to
CLIPPERS AND CLAMPS
EXPERIMENT 01000
0.7V)
in
circuit
forward
the
the diode
The diode
type and
In
always forward
is
at the collector
D-j
is
direction.
is
ELECTRONICS/DIGITAL
and the base-emitter voltage
this
is
biased.
germanium
^BE
= F rward Drop D + Clamp Voltage

2
reverse biased until the collector-
(8.13)
emitter voltage tries to drop below the clamping voltage.

a
point, D-j conducts with
At that
forward drop of approximately 0.2

base
excess
This
opposes
current
V CE
Iq
and
Vg^
greater than
Vq^. With the
prevents any further drop of

transistor conducting,
The transistor cannot enter the saturation

region when the conducting value of Vq^ \%
volts.
we can observe
can be determined
at the time.
that the forward drop of
plus the clamping voltage
by
Substituting,
must always
be
greater than the value of the forward drop of
V CE
= Forward Dr P
D 1 + Clamp
D2
Voltage
plus the
clamp voltage.
The
trick here
is
that the equation

(8.11)
With the transistor
VgQ
off,
= Forward Drop
V Bq
V D1
is
has
D2 + Voltage Across Di
VD
voltage.
With the transistor on
we
V Clamp > V D2 + V Clamp
implications obscured by the fact that
its
both
V D2
and
Since
insured that
are opposing the clamping
we chose D 2
its
as a silicon diode,
forward drop would oppose
the clamp voltage in the base circuit and
V BC
= Forward Dr P
D 2 + Forward Dro P D 1
makes the
always
conducting value
this
Vq^
> V BC-
(8.12)
MATERIALS
1
Oscilloscope
VOM
Function generator
Diode type IN 305 or any other
germanium type
1 kft resistor 1/2W
DC power
Transistor type
Output
supply (0-40V)
2N 1 305
or equivalent
FEM
or
characteristic curve for the transistor
3 Resistance substitution boxes (15fi- 10 meg

suitable selection of resistors)
1
Transistor socket
Breadboard
6.8 kft resistor
1/2W
PROCEDURE
1.
Calculate
V cc
2.
R B and R L
for a transistor clipper with a
= 200 juA and

= 6V. (Choose
c = 4 mA.)
B
I
in figure 8-7.
72
2N1305
transistor operating
at
CLIPPERS AND CLAMPS
EXPERIMENT 01000
ELECTRONICS/DIGITAL
2N1305
e
out
O
'CC
Fig.
8-7
The First Experimental Circuit
3.
From
4.
Observe and record the output waveform.
5.
6.
Measure and record
7.
Calculate the rise time for the leading and trailing edges.
8.
Disassemble the circuit.
9.
Calculate the values of R|_, Ri and
10.
the function generator, apply a
Assemble the
ej
circuit
rise
10V peak
sine
time of the leading and
wave
at
kHz.
trailing edges.
n and lg.
shown
R2
for a practical diode collector clamp.
in figure 8-8.
OUTPUT
11
0 v cc
AA/V
-10V
J2N1305
ru
C1
6.8
kn
GND
Fig.
8-8
73
EXPERIMENT 01000
CLIPPERS AND CLAMPS
RB
V CC
RL
ELECTRONICS/DIGITAL
E in
tTE
tLE
Calculated
Measure
Output
Resistor
Clipper
r2
Ri
v cc
Calculated
Measure
Output
Diode
Emitter
Clamp
Fig.
8-9
The Data Tables
74
V C1
E in
EXPERIMENT 01000
ELECTRONICS/DIGITAL
V
kHz square wave
11.
Apply
12.
Observe the output on an oscilloscope.
.
p p
CL IPPERS AND CLAMPS
at the input terminals.
Record the waveform. Record the amplitude of
the square wave.

13.
Measure and record Vq-|.
ANALYSIS GUIDE. The
purpose of this experiment has been to become familiar with clipping

clamping
in
transistor
circuits.
You should discuss how this is done in a variety of circuits.
and
Why is it done? Which of the circuits that you investigated was the best? Why do you think so?
Could the transistor circuit
in
figure 8-1 be used with a square
wave input?
PROBLEMS
1.
Given a collector clamp with a silicon diode and
a bias
voltage of 3 volts,
what
is
the
clamp voltage Vq^?

2.
3.
Given a single diode back clamp with an \q required at 6 mA and the current through
the load resistor 3 mA, how much current will pass through the diode?
We
wish to build a double diode clamp.
transistor conducting
drop of 0.2V.
We
is
1.5 volts.
The
voltage collector-to-emitter with the
The diode Di
is
germanium and has
wish to clamp the collector at 6V.
your answer.
75
Is
this possible?
forward
Explain
experiment
DIODE LOGIC GATES
QJ^QQJ
INTRODUCTION. Gates are used to control the

we shall examine how diodes are used as logic gates.
DISCUSSION. Logic
normally operate
input
levels.
with two
These inputs are
logic cir-
gates, like all
cuits,
selection of logic pulses.
input terminals with a semiconductor diode
possible
signals that
in
OFF or ON, or
number system. The
two signal levels could be represented by any
two voltage levels. When the more positive
series
with each.
types.
operations,
represents the binary
system
level
0 or "no".
is
or a "yes", the logic system
termed negative
different
logic.
The
levels
is
types of systems
(+)
and times
(X).)
Figure 9-1
Notice that the
gates.
In
the case of the
OR
gate,
when any one
of the gates receives a signal, the gate pro-
duces an output.
is
can be of
exists
same polarity so
more negative or more positive
than the other.
two Boolean
and AND. (We also frequently
In
when any or
present
polarities or the
long as one
them plus
to the
two
polarity of the diodes are reversed.
or "yes", the
logic.
OR
shows both types of
more negative level repreWhen the more negative
positive logic, the
sents
termed positive
is
call
Basically, there are
They correspond
represent "true" or "false",
logic
experiment
diode gate consists of two or more
the digits of the binary
level
In this
at
A,
That
all
is,
an output pulse
of the input signals are
The Boolean
or B, or C.
equation for the circuit shown
is
There are many different

in
use today.
Some
A+
of the
B + C = Output
(9.1)
most popularly used levels seem to be -11

and -3, -10 and
0,
-6 and
0,
OR
and -5 and 0
operate for any number of
inputs as long as the inputs are
volts.
AO-
gates will
more
positive
BO-
+4
bO-
CO-
+4
OR
cO-
GATE
AND GATE
6 -V BIAS
Fig.
9-1
Diode
6 -V BIAS
AND and Diode OR

76
Gates (For Negative Logic)
than the applied negative bias voltage at the
lower
end of the load
truth
table
the
for
AO-
The
shown in
figure 9-1.
in
OR
DIODE LOGIC GA TES
EXPERIMENT 01001
ELECTRONICS/DIGITAL
gate
is
figure 9-2.
BO-
INPUT
OUTPUT
>r
C O-
6-v Bias
Truth Table for an
summary, the
In
an output
C, or
OR
there
if
is
OR
Gate
Positive
"You
circuit says,
Circuit for
Going Pulses
get
the
In
an input at A, or B, or
electronics
N."
An OR
9-4
Fig.
9-2
Fig.
-0 E c
case
of
almost
is
the
OR
circuit,
the
Pulses which
trivial.
appear at the input are accepted or rejected
The
AND
on the other hand,
circuit,
requires that an input be present at
and
C and
The
Boolean
circuit
in
and B
order to obtain an output.
equation
for
AND
the
according to their polarity.
Reversing the
diode
the
positive pulses.
is
times larger
ABC
= Output
of
pulses
Figure 9-4 shows an
polarity.
gate
select
will
As long
opposite
OR
gate for
as the R|_
many
is
than the forward drop of the
diode, the output voltage will approximately
(9.2)
equal the input voltage (with a slight loss due
AND
The truth table for an

in
circuit
is
shown
forward resistance of the diodes). Due
to the
figure 9-3.
to
the
losses
across the
diodes,
it
is
not
usually practical to use extremely long strings
INPUT
OUTPUT
of diode gates in series without reestablishing
the signal level occasionally.
Fig.
electronics
may
require
cause of the bias voltage at R|_,
Truth Table for an
circuit
somewhat more extensive examination.
9-3
AND
AND
are
conducting with no input
total
voltage of the bias
is
all
Be-
the diodes
signal.
The
dropped across
R L or
(The voltage drop across
Circuit
R|_)
V RL
V Bias
(9.3)
77
EXPERIMENT 01001
ao
DIODE LOGIC GA TES
ELECTRONICS/DIGITAL
+4
bO-
co-
+4
Bias
9-5
Fig.
Positive
AND
Gate
dropped
inputs,
one or more of the diodes may be
across R|_, no output voltage will appear be-
turned
off;
tween the output terminal and ground.
conduct and continue to drop
Since
all
of the supply voltage Vgj
as
is
but the remaining diodes
OV
be an output will
(9.4)
receive the proper pulses
At that time, the

9-5
Figure
positive
pulses.
pulses can be
shows an
made by
AND
when
for
zero,
gate for negative input

reversing the diodes
drop goes
to
bias voltage (or supply voltage)
appears at the output.
and
These are the most basic and perhaps
most important of the gate circuits.

The
symbols used in logic schematics and ref-
at an
erence works are shown
input, the diode at that input stops conduct-
However, the remaining diodes are
AND
still
conducting and the Vgj as will still be entirely

dropped across R|_.
Consequently we will
still
Rj_ voltage
off.
In figure
and magnitude (equal to Vgj as appear

ing.
and the
and are turned
pulses of the correct polarity (+)
the polarity of the voltage to R[_.

9-5,
gate
will
the bias
The only time there will

be when all the diodes
voltage across R|_.
E0 =
all
have zero volts at the output point.
inappropriate
pulses appear
(INPUTS)
at
gate and
Many
practical
If
any of the
in
other
logic
logic
gates are used as are
Fig.
9-6
Three Input AND Gate Symbol
78
figure 9-6 for the
figure 9-7 for the
circuits.
in
gates
are
OR
gate.
used
in
Resistor-capacitor
many types
(OUTPUT)
of transistor
EXPERIMENT 01001
ELECTRONICS/DIGITAL
DIODE LOGIC GA TES
A
(INPUTS)
(OUTPUT)
Fig.
The
gates.
9-7
Three input
transistor gates have the important
to the output. This
when
important
is
Gate Symbol
diode
particularly
will
a sort of
zero output
normal
is
shown
backward
when
AND
ative
gate that has a
In
Vpj_
is
at
because
-V^
is
v RL
with a
off but
C and
A and B,
negative
the diodes
when
at
least
at the
positive pulse
equal
to V-|
be forced into conduction by
will
the load and E
will
I
6 +v.
9-8
is
same time A and B

A and B will be cut
not change
level.
"0 E r
Fig.
a neg-
the positive pulse, a current will flow through
the bias applied to R|_
still
output goes to -V1

drop across R|_ = 0.
receive negative pulses.

(9.5)
the voltage drop across the load
A o-
voltage
magnitude
applied to
cut off.
=o
the
Inhibition will occur
and
When
B.
pulses are applied at both
sufficient to hold diode
this case,
pulse
are both cut off, but the
-v 1 +
while
input
the pulses are present.
all
B diodes will conduct, provided the inhibitor

is
The same thing happens with
would be the reverse of a

gate.
With no input at A or B
table
AND
would stop conducting but B would
to V2.
This
in figure 9-8.
and only the inhibitor signal at C, the
voltage
voltage.
conduct and the output would remain clamped
particularly interesting diode gate, the
truth
V2
In the case of a negative input pulse to A,
diode inhibitor,
Its
be conducting, and the output
will also
long strings of series gates are
it
is
and B conducting, the clamp
be clamped to the
employed.
With
resistor.
advantage of being able to provide amplification
OR
Inhibitor Gate
79
EXPERIMENT 01001
ELECTRONICS/DIGITAL
DIODE LOGIC GA TES
MATERIALS
2 Resistance substitution boxes
2 Semiconductor diodes (breakdown
(15ft- 10megS2)
potential greater than 5V)

1
DC power
Oscilloscope
supply (0-40V)
Function generator
PROCEDURE
1
Connect the
circuit
shown
in figure 9-9.
OUTPUT
+5V =
V(1)
+4
AO-
2.4
-^^V
0=
V(0)
BO-
Fig.
2.
0+4V
9-9
The
First
Apply approximately +5 volt pulses
at
kHz
to input A.
output. (Leave B input at zero volts.)

3.
Apply approximately +5
volt pulses at
kHz
to input B while
is
at zero volts.
Measure
and record the output waveform.

4.
5.
Apply +5 volt pulses at 1 kHz to both A and

Record the type of gate, (positive Logic)
B.
Measure and record the output waveform.
Disassemble the circuit, and assemble the circuit
in figure
9-10.
O OUTPUT
+5V =
V(1)
>r
INPUT A O-
30 kn
-O +4 VOLTS
0=
V(0)
INPUT B O-
Fig.
6.
Apply +5
volt,
9-10
kHz
pulses at
with B at zero
waveform.
80
volts.
Measure and record the output
EXPERIMENT 01001
ELECTRONICS/DIGITAL
7.
Apply +5
volt,
kHz
pulses at B with
kHz
pulses at
at zero volts.
DIODE LOGIC GA TES
Measure and record the output
waveform.
8.
Apply +5
type of
9.
and
B.
Measure and record the output waveform and
(Positive Logic)
Disassemble the circuit and build a two input gate that
+3V
10.
volts,
gate.
at
will
accept negative pulses of
kHz.
Construct a truth table for your
ANALYSIS GUIDE.
In this
circuit,
and
give
its
Boolean equation.
experiment the diode as a gate device has been examined.
analyzing these results, an explanation of the diode action should be given.
In
Also discuss the
operation of each of the experimental gates using your waveforms to illustrate their operation.
Output
Input
A = +5
B=
Output Waveform
Input
A=
Output
B = +5
Output Waveform
Fig.
9-11
The Data Tables
81
EXPERIMENT 01001
ELECTRONICS/DIGITAL
Output
Input
DIODE LOGIC GATES
= +5
B = +5
Type
Circuit
Output Waveform
Output
Input
= +5
B=
Output Waveform
Input
A=
Output
B = +3
Output Waveform
Fig.
9-11
82
EXPERIMENT 01001
ELECTRONICS/DIGITAL
Output
Input
A = +3
B = +3
Circuit
Type
Output Waveform
Circuit Diagram for
Fig.
9-11
Two
Input and Gate
83
DIODE L OGIC GA TES
EXPERIMENT 01001
ELECTRONICS/DIGITAL
DIODE LOGIC GATES
INPUTS
OUTPUT
Fig.
9-11
BOOLEAN EQUATION
PROBLEMS
1.
Given a load resistor to ground from

at the diodes of
2.
Will
AND
0 and +2 volts DC. What
AND
will
gate,R|_ = 5.1 k2 and
the output
level
two inputs
be?
gates have slightly higher or slightly lower output levels
are used in place of

3.
diode
if
silicon diodes
germanium? Why?
In the circuit of figure 9-10,
what
will
be the effect of an open diode at
84
A?
experiment
INTRODUCTION.
this experiment we
gates are
RESISTOR-TRANSISTOR LOGIC
01010
(RTL) CIRCUITS
Basic logic operations

shall
may
examine transistorized
be performed by either diodes or transistors.

logic gates of
constructed using only resistors and transistors.
perhaps the simplest type.
They
In
These
are often referred to as
RTL
circuits.
DISCUSSION.
of
shown
the circuit
transistor
supply
ative
Qi
Vgg.
consider the operation
Let's
is
If
figure
in
simply, a
The
10-1.
for such a gate
pulse
we apply
If
further into saturation
the
However,
circuit
since
if
that
acts
driving
is
inverted.
is
called
As
possible.
OR
like
an
the
base
where E 0
(10.1)
is
the output and the negative sign
indicates the polarity reversal across the gate.
Appropriate values for the various
gate.
negative
causes the collector to go positive, the
often
+ B + C = -E,
a single input
another input will only drive the transistor
result,
is
completely into
transistor
then applying another pulse to
saturation,
The Boolean expression
a sufficiently neg-
can be turned on.
drives the
gate.
biased to cutoff by the base
pulse to any one of the inputs, then the
transistor
NOR
cuit
output
resistances
can
cir-
be readily determined
using the transistor input and output char-
Such an inverted/OR gate is

negative OR gate or, more
acteristics.
curves
shown
For example,
let's
consider the
in figure 10-2.
INPUTS
'"LTLTLT
:
o o
b
i_n_r
u-
Fig.
10-
An
Inversion/OR (NOR) Gate
85
_rLn_rr:
EXPERIMENT 01010
-I
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
'B
(|iA)
0.05
V CE (VOLTS)
Fig.
10-2
Transistor Characteristics
60
the
Rq we first choose some reasonable

maximum collector current (Iq SAT^ From
the output curve (Vq^ vs Iq) we see that
choose
mA
The
would be reasonable.
would then be
Using th is value (lg

sat
input characteristic, we
things.
First,
resistance
V cc
20
5
CSAT
observe
second, the transistor input
0.15V -0.13V
80 juA - 40 juA
Al g
0.02V
= 500fi
40 /nA
The base resistor Rg is usually chosen to

be large enough so that it will not seriously
On
reduce the transistor input resistance.

other hand,
Since this
not a standard
is
size,
probably use 3.9 kfi, which

standard
is
we would
lector load line
from
Vqq
transistor
C max
20
5.1
saturation.
line
plotted
is
usually quite satisfactory.
this
mA
we observe
60 mA or more
j = 60 (x A)
g
base current of
off.
10R in
In
our example,
would be
R B = 10 R jn = 5
With the load
large that the
not completely cut
R B=
to
3.9k
must not be so
col-
is
V CC
it
will
the
value of
the nearest
Then we would plot the
size.
two
be approximately
approximately
AV BE
= 4kfi
mA
is
on
will
/xA) with
col-
'in
RC =
Vgg
And
0.15 volts.
lector resistor
0.20
V BE (VOLTS)
Suppose the collector supply (Vqq) is

to be -20 volts and Vgg is +10 volts. To
about 5
0.15
0.10
kft
that a
and
required for
4.7
86
we would probably
k2
resistor.
decide
to
use
EXPERIMENT 01010
ELECTRONICS/DIGITAL
The input
R2,
resistors (R-j,
R3)
are
usually all equal values
cases,
Vg on
input
pulse
R 1 = R2 = R3
lg
chosen
are
and
applied,
if
assure
that
VA
To turn
satisfy
VB
V c = 10 volts
we must
the transistor fully on,
we have
10-0.15
= 164
60 /xA
kl
inverted
size,
size.
more
10-3
figure 10-1
is
cir-
In
the value of
Rg
to a
is
applied,
and saturate
inputs are applied, then
AND
gate.
Such
a gate
if
it
we
have an
is
called a
gate.
most
The equivalent circuits of the two input

shown in figure 10-3 for N
conditions are
practical
inputs.
ALL BUT ONE INPUT

Fig.
in
we would
Using a smaller size assures us of having
(A)
shown
we merely change
all
NAND
not a standard
enough base current.
circuit
but one input
when
normally use the next smaller standard
than
use 150 k2
value which will hold the circuit cut off

all
is
our example. In
perhaps one of the most versatile logic
If
Since this
in
cuits available.
BSAT
R,-
bsat
we would probably
The RTL
V A- V BEon
Therefore, in our example,
VA
for the input resistors.
the relationship
_
R1 =
use simply
which would give 167 kl
the input pulses have a height of
we can
is
either case,
height that
sufficient
flow when an input pulse
will
g^y
to
compared to the
so small
is
R
"1 ~
(RTL) CIRCUITS
(b)
Input Conditions for a
87
NAND
Gate (with
ALL INPUTS
N inputs)
EXPERIMENT 01010
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
Fig.
10-4
An
Inversion /AND
The two equations which describe these
(NAND) Gate
urated.
If
we apply two
only slightly saturated.
s-
\^
Oand s -\\ = lg
\
Assuming that Eg and

greater than
Vgg
Vgg on we
this
much
are both
V BB
q
andR
.
(N-1)l BSAT
We
acts as an
conditions to circuit values of
happens,
pulse.
can reduce these
But
we
now
we apply
inverting
Rq
all
get a single negative output
AND
circuit
NAND
or a
circuit resistances
what more involved than for

However,
be
circuit will cut off.
can say, therefore, that the
Choosing the
S
1-!^
if
same time (A and

When
three positive inputs at the
SAT
B and C), then the
RB =
B),
the circuit will not cut off but will
circuits are
inputs (A and
is
NOR
gate.
somegate.
can be selected the same way
as
must be chosen such
as
before.
Hence, the Boolean equation becomes
The base
ABC
= -E
Q
(10.2)
resistor
to provide sufficient saturation current that
only the final
where the minus
If
we
transistor
sign indicates inversion.
We
reverse the polarity of the base
sistor
Q.|
is
forward biased deep into
uration with no inputs present.
If
one input
sat-
still
we apply
not cut off because
it is
too deeply
cutoff.
must,
satisfy
therefore,
lg
is
than
SAT
That
Vg^ on
Secondly,
present, the transistor
sat-
88
First,
two conwhen all but
applied, then the transistor must
be saturated.
greater
a single positive input pulse (A), the circuit

will
from saturation to
ditions simultaneously.
{Vgg) supply, the circuit will appear as

shown in figure 10-4. In this case, the tran-
switch the
input pulse will
is,
Vg E
must
still
be
and lg must exceed
when
all
must be cut
inputs
off.
are
That
EXPERIMENT 01010
ELECTRONICS/DIGITAL
10-5
Fig.
is,
Vgg must
approximately
be
perhaps even a
little
we choose
cutoff.
We
circuit
shown
R3 =
= R =
2
From
Equivalent Circuit at Cutoff
zero
one input applied
(or
From
reverse biased), and lg
must also approximate zero.

that
to have
Vg^
this circuit
is
shown
we have
figure
in
10-6.
the equation
Let's suppose
equal to zero at
'bb
's
'bsat
can then draw the equivalent
in
.
10-5 (assuming
figure
or
= R ).
N
this circuit
we
V BB
see that
V BEon
5
ES +
Kg
V BB
(RTL) CIRCUITS
N Es
where E5
is
Similarly,
the equivalent circuit for
the height of the input pulses.
Fig.
10-6
all
V BEon
ffc
(N -
1X
1)
K-|
'bsat
Solving this equation and the one from figure
but
10-5 simultaneously and assuming
Equivalent Circuit with (N-1) Inputs
89
Vgg
EXPERIMENT 01010
V BE
on
AND
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
BE on
9 ives us
circuit
component
the circuit
values.
Rg
If
is
such that
barely saturated with no input,
is
then applying any one input can cut
BB
B
(1/N)
SAT
=
RR
B
off.
values of
and
R 1 ~\
it
This set of conditions would give us circuit
V BB
i
'BSAT
and Ri =
1
SAT
SAT
And
the Boolean expression becomes
Using the values from our previous example,
A+
these equations render
RB
B + C = -E,
Or, in other words, the circuit performs the
55.5 kQ,
NOR
operation.
and
NAND and NOR gates rather than

and OR, usually do not present any seri-
Using
R-j
= R =
2
R3=
166 kft
AND
ous problems since the output of

In this case,
we would probably
use values of
always be
56 kft and 168 kft respectively.
INVERTED
As was the
function
case before
we can change
by selecting another
the
set
or
of
NOR
gate,
we can convert
OUTPUT
INPUT
jj
-OE,
. . -
WV-
+v
BB'
Fig.
10-7
Logic Inverter
90
Figure
By
to the output of a
logic.
INVERTER
a gate can
necessary.
10-7 shows a typical logic inverter.

ling this circuit
logic
if
_TL
to
coup-
NAND
AND and OR
EXPERIMENT 01010
ELECTRONICS/DIGITAL
Fig.
In
Rl =
an inverter
Rg = 10
Rj
Rq
is
10-8
NPN Logic
chosen as before,
the input circuit.
for
The
have
logic gates discussed
used
PNP
transistors
up to
this point
only.
Similar
Gates
circuits can, of course,
provides satisfactory values
(RTL) CIRCUITS
NPN
transistors.
and
NOR
gate
You should be
NAND
and
be constructed using
Figure 10-8 shows a
employing
NPN
able to figure out
NOR
NAND
devices
which
is
the
gate by yourself.
MATERIALS
2
DC power supplies
or FEM
(0-40V)
8 Resistors (values to be determined
VOM
2 Transistors, type
by student)
2N 1304 and 2N1305
or equivalent
Breadboard
2 Transistor sockets
Set of curves for the transistors
PROCEDURE
1.
2.
Examine your two
and decide which one you
will use for a logic gate.
Using your transistor curves, determine an appropriate value of collector resistor to use
= 10 volts.
V
with
3.
transistors
cc
Determine the appropriate values to use for Rg,

gate which has a
Vgg
of 10 volts and a
Eg of 10
R-j
and R2, with a two input
volts.
Use the type of
circuit
NAND
shown
in
figure 10-4.
4.
Assemble the appropriate
5.
When your
present.
circuit
is
NAND
gate circuit using either figure 10-4 or 10-8 as a guide.
assembled, measure and record your value of
Record the polarity too.
91
Vq^
with no input
EXPERIMENT 01010
A
Connect input
6.
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
only to a 10-volt potential of the proper polarity.
(B input should be
grounded.)
Vq^
Measure and record
7.
and
Connect input B only to
8.
polarity.
its
(A should be
10-volt potential of the proper polarity.
grounded.)
Record the value of Vq|= and
9.
10.
Connect both input
11.
Record the value of
Vq^
polarity.
its
a 10-volt potential of the
and input B to
and
polarity.
its
2.
Prepare a truth table of your observations from steps 5 through
3.
Reverse the polarity of
V BB
proper polarity.
then repeat steps 5 through

that you
1 1
2.
would use for an
14.
Compute the values of Rq, R b and

15.
Using your remaining transistor, construct an inverter and connect
your
R-|
inverter of the type
it
to the output of
logic gate circuit.
16.
Repeat steps 5 through 12 again and
17.
Again reverse the polarity of
V BB
this
time measure the
Vq^
and repeat steps 5 through
of the inverter stage.

13, recording the
Vq E
of
the inverter stage.
Draw
18.
complete
transistor type,
ANALYSIS GUIDE.
circuit
and power supply
it
how your
how you
an
can
tell if
this experiment,
you should
discuss each circuit
truth tables verify each Boolean equation.
RTL
V CE
No
from
Give the Boolean equation which describes each circuit and
means. Also discuss
Discuss
values,
polarities.
In analyzing the data
used and the results observed.
what
diagram of each of the setups used, showing circuit
circuit
is
NAND
V CE
Input A Only
Input
or a
Input B Only
Circuit
Second
Circuit
Third
Circuit
Fourth
Circuit
Measured Data
10-9
The Data Table
92
gate.
V CE
First
Fig.
NOR
V CE
Input
A&
tell
EXPERIMENT 01010
ELECTRONICS/DIGITAL
(RTL) CIRCUITS
Circuit Diagram
The Data Table (Cont.)
10-9
Fig.
PROBLEMS
1.
Using the methods outlined

the circuit shown
JTTI
TL
JIT!
the discussion, compute the
component values
for
10-10.
in figure
o-WVi
WV
n.
JUTJl
in
o
D
OUTPUT
o-WV"
__n_TL
ALL INPUTS 5V_p-p
Fig.
10-10
Circuit for
93
Problem
EXPERIMENT 01010
2.
3.
Make
(RTL) CIRCUITS
a sketch of the input
ELECTRONICS/DIGITAL
and output waveforms for the
What would be the peak-to-peak
signal voltage at the
circuits in figure 10-8.
output of the
figure 10-10?
4.
What
5.
Explain
is
the Boolean equation for the circuit

in
your own words how the inverter
94
in
in figure
1O10?
figure 10-10 works.
circuit in
INTRODUCTION. There
are a variety of direct-coupled transistor circuits

In this
perform logic operations.

coupled transistor logic
(DCTL)
experiment we
three
state
a negative pulse
only, the transistor Q-j
on.
off,
is
voltage
would
applied to input
inputs
to
come
the
and
on.
B,
both
equal
be
0_i
all
pulses to
all
three transistors will
current will flow through Rq.

will rise to
approximately
would want to turn
The
to
get
-Vqq.
Q 2 would
and
However, since
Q3
is still
overall result, then,
pulse only
an output
negative
pulses are applied simultaneously to
direct-
zero.
neously.
If
then
The output voltage
However, since both Q-2 and Q3 are cut

no current can flow through R c and the
output
inputs,
come on and
All three transistors will, therefore, be

If
common
we apply simultaneous
If
currents supplied to the three input bases are
cut off.
which are used to
examine some of the more
circuits.
Suppose that the steady
figure 11-1.
zero.
will
Let's look at the circuit given
DISCUSSION.
in
DIRECT COUPLED TRANSISTOR

LOGIC (DCTL) GA TES
own
experiment
inputs to
all
This circuit
three
then
is
that
we
will
when we apply
is
bases
a
simulta-
NAND
gate
and provides the Boolean operation,
want
cut off
ABC =
(11.1)
-E,
output would remain at -Vqq.
OUTPUT
'cc
INPUT
i_n_n_r
0
-E c
UTJ
i_r
oAA/V
^f^-(fc^)
Fig.
11-1
Series
DCTL NAND
95
Gate
EXPERIMENT 0101 1
(DCTL) GA TES
Fig.
The DCTL
ELECTRONICS/DIGITAL
1-2
Series
shown in figure 11-1

has a logical dual as you might expect. The
dual of the series DCTL is shown in figure
circuit
DCTL NOR
sistors,
of
of
of the input signals.
Rq need
safe
cut off producing signals which are at a neg-
(Figure
was such
1-1
RC =
a circuit.)
In such a case the transistor
is
Q^, G^, and

normally on and the output of the gate
normally near zero.
If
any one of the
sistors receives a positive pulse
the output drops to

therefore, a
sion
NOR
its
Iq
max
and
(11.3)
Some
tran-
max
applications require that the tran-
sistors
be biased individually.
shows
a typical bias arrangement.
Figure 11-3
cuts off and
The
-Vqq.
gate and
it
value of
V cc
'C
Q3 are
value
computing Rq.
nected to other logic circuits which normally
ative voltage.
DCTLs, only the
be determined. This can be done
by choosing
three inputs are con-
all
the only difference being the polarity
Vqq, and
In building series
11-2.
Suppose that
Gate
circuit
Such
is,
a circuit
may be
either a
NAND
or
NOR
gate, depending on the polarity of the

By now you should be able to determine
which type of gate would result from each
Boolean expres-
bias.
is
A+
Series
B + C = -E,
DCTL
(11.2)
bias polarity.
DCTL
circuits can, of course, be
constructed with either
NPN
or
PNP
tran-
parallel
96
circuits can also be
transistors.
made
using
Figure 11-4 shows one
EXPERIMENT 01011
ELECTRONICS/DIGITAL
Fig.
1-4
Parallel
97
DCTL NOR
Gate
(DCTL)
GATES
EXPERIMENT 0101 1
(DCTL) GA TES
ELECTRONICS/DIGITAL
v ccQ
cc
_n_n_TL
j~ltl
BO
n
11-5
Fig.
such
In this circuit
circuit.
sistors
are
voltage
is
all
A DCTL NAND
three tran-
Figure
negative input pulse
any one of the

output
transistors,
rises to
fore, of the
it
near zero.
NOR
is
DCTL
parallel
circuit.
dual
parallel
near zero.
turns on and the
The gate
is
sistors,
there-
case.
all
three transistors
output
If
we
normally
turn off one of the
we
two
transistors are
tran-
still
on.
Sim-
turn off two of the transistors, the
is still
near zero due to the conduction
of the last transistor.
(11.4)
level is
are
the output stays near zero because
the other
type and has
B + C = -E,
circuit
this
normally on and the output
applied to
ilarly, if
A+
the
shows the
11-5
In
If
of
dual
logic
normally cutoff and the output
normally at -V cc
Gate
But
if
we
turn off
all
three transistors the output falls to -Vqq.
for
its
Boolean expression.
as a
We can
see, therefore, that the circuit acts
NAND
gate.
is
consequently
If
which
the inputs are connected to sources
normally
produce positive
have a negative
signal
pulses
level
we have
and
ABC =
the
98
-E,
(11.5)
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
+v ccO
Oe.
AO
AAAr
AAAr
v bbO
A/W
AAAr
v bbO
CO
AAAr
B
AAAr
v bbO-
Fig. 1 1-6
As was the case with

cuits,
we need only
build
parallel
series circuits,
'c
max
anc
'
sistors
DCTL
11-6
gate.
You should know by now which type of

would have positive bias and which type
would have negative bias.
cir-
to
gate
Also, like the

a safe value of
Selecting a base resistor value
bias
V cc
line
u
'C max
them
is
almost
always done simply by laying out the load
to build parallel
shows
Rq
com P ute
can use either
separately
DCTL
find the value of
we simply choose
=
Rr
C
We
series
Separately- Biased Parallel Gate
if
of
Rq and
determining the value of the
saturation base current.
a separately biased
NPN
is
then calculated
using
PNP or NPN tranDCTLs and we can

necessary.
Rg
Figure
R B~
circuit.
99
V BB
|
SAT
(11.6)
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
This value will normally be satisfactory

for either series or parallel
NAND
current to
base
limit
to
NOR
twice lg SAT'
chosen
n1
or
safe
value, say
gates.
E
Similarly, the input resistors are
2lgg A j
MATERIALS
3 Transistors type 2N 1304 or
Breadboard
2N1 305 or equivalent

Set of output characteristics
for the above

1
VOM
DC power
FEM
or
supplies (0-40V)
4 Resistors, values to be determined
by student
PROCEDURE
1.
Choose
10
a value of
Rq which
is
appropriate for use with your transistor type and a
V cc
of
volts.
which
appropriate for your transistor, Rq, and E5 of 10
2.
Compute
3.
Construct a circuit similar to figure 11-1.
4.
Apply
5.
Repeat step 4 with input B only, then with input C only.
6.
Apply the voltage of correct polarity to inputs
a value of R-]
a voltage of correct
is
Measure the output with no input
polarity to input
only and record the output
volts.
signal.
voltage.
and B simultaneously. Record the
out-
put voltage.
and C.
7.
Repeat step 6 using inputs B and C, then
8.
Now
9.
Prepare a truth table showing the results of steps 3 through
apply the signal to
Use
zero output.
all
three inputs simultaneously.
for input applied and output =
8.
Use 0 for no input and
Vqq.
10.
Write the Boolean expression which represents the results
11.
Connect the input
in
your truth
signal to all three inputs so that the three transistors are on.
the output voltage.

the signal from input
2.
Remove
3.
Repeat step
table.
only and record the output voltage.
2 with the signal removed from B only, and
100
only.
Record
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
14.
Disconnect the input signal from
and B simultaneously and record the output.
15.
Repeat step 14 for B and C, then
and
16.
Disconnect the signal from
17.
Prepare a truth table of your results from steps
and output
Vqq. Use
all
C.
three inputs and record the results.

1 1
for input disconnected and output
18.
Write the Boolean expression for your truth table.
19.
Construct a circuit similar to figure
20.
Draw
ities
gate
1-4 and repeat steps
In analyzing
gates to parallel
NAND
your
gates.
results
zero.
all
18.
circuit values.
you should compare the operation of
series
Explain the operation of each and discuss their similar-
and differences. Compare series and parallel

do you prefer? Which NOR gate? Why?
NOR
First Circuit
Inputs 0 or
4 through
detailed circuit diagrams for both test circuits showing
ANALYSIS GUIDE.
NAND
through 16. Use 0 for input connected
gates in the
Data
Output
Oor
Boolean Expression
Fig. 1 1-7
same manner. Which
The Data Tables

101
volts
NAND
EXPERIMENT 0101 1
(DCTL)
ELECTRONICS/DIGITAL
GA TES
Second Circuit Data
Inputs 0 or
Output
0 or
volts
Boolean Expression
Third Circuit Data
Inputs 0 or
Output
Boolean Expression
Fig.
11-7
102
Oor
volts
EXPERIMENT 0101 1
ELECTRONICS/DIGITAL
(DCTL) GA TES
Fourth Circuit Data

Inputs 0 or
Output
Oor
volts
Boolean Expression
Fig. 1 1-7
The Data Table (Cont'd)
PROBLEMS
1.
Design a series
|E
= 5
S
I
NAND
gate using
Repeat problem
using a parallel circuit.
3.
Repeat problem
using a
4.
Repeat problem 2 using a 2N 1305.
5.
Discuss the operation of the circuit

1
15
volts,
volts.
2.
figure
to operate with |Vqq| =
2N 1304s
2N1305.
shown
in figure
1-8.
How
is it
different
from
1-1?
the output waveform for the circuit
6.
Draw
7.
figure
in
1-8.
shown
in figure
8.
Write the Boolean expression for the circuit
in figure
9.
11-9 and sketch the output
waveform.
shown
in figure
1-9.
11-10 and sketch the output
waveform.
10.
Write the Boolean expression for the circuit
103
in
figure 11-10.
(DCTL) GA TES
EXPERIMENT 0101 1
v cc
INPUT
AO
LT
"LTLTLT
+E
-i
Fig.
1-8
VW
Circuit for
Problem Five
INPUT
ruu
~U
VW
ao
LT
LT
uuu
Fig.
VW
1-9
Circuit for
104
Problem Seven
EXPERIMENT 01011
ELECTRONICS/DIGITAL
(DCTL) GA TES
+v cc
GATE
OUTPUT
?
INPUT
"0
AO
VW
i_n_r
+E C
~LTLT
Fig.
1 1-
10 Circuit for Problem Nine
105
Er
experiment
INTRODUCTION.
experiment we
NOR
Inputs A,
other
which prevent
it is
logic gate operations are called inhibitor circuits.
shown
gate
B,
in
figure
gates could produce this type pulse.
negative
is
reference
is
voltage.
(12.1)
The value of Rq can be determined by
used,
all
the
When
the output will drop to
c~
VCC
I
i
'C
max
any of the
where \q max is choosen
a pulse
device.
transistors,
that transistor will be biased to cutoff, and
is
on and the output
at zero volts.
arrives at the base of
-s
for this series
+ B + C = -E 0 (lnvertedOutput)
arrangement
transistors are normally
of the gate
gate
In
can be inhibited.
which produce positive
from
this
DCTL NOR
and C are connected to
NAND
a logic gate
12-1.
pulses
When
necessary to prevent a logic gate from operating
examine some of the ways that
shall
circuits
logic
logic operations
Let's consider the operation of
DISCUSSION.
the series
some
Circuits
at certain times.
this
In
/f///f/t INHIBITORS
By
as a safe value for the
reversing the polarity of
-Vqq.
could be constructed with
NPN
transistors.
"LTLTLr:
nji_n_
n_n_
J~L
Fig. 12- 1
Vqq and
inverting the output, the circuit in figure 12-1
Series
106
NOR
Gate
'cc
EXPERIMENT 0 1 100
ELECTRONICS/DIGITAL
WV
WV
ao
o
io
'1
WNr
Âfc~
Fig.
As we have
said,
any time
12-2
Transistor inhibitor Gate
can be turned off by introducing a signal at
positive
A, B, or C which
going pulse of negative voltage arrives at the

base of
any of the
that
Q3),
output
some
cut
will
switch
or
and the
off
Suppose for
drop to -Vqq.
reason we wish to exclude certain
For
inhibitor.
diode and
12-2
this
we
need to
possible
Inhibitors are
transistor
is
devise
logic.
transistor
The
in
inhibitor
B-|
or
C.|
many ways
We
cutoff.
by applying
can
signals at A-|,
to prevent the change
in
bias
and
prevent (or inhibit) at any given desired time.
As with the other

ities of Vqq and
in
gate.
allow us to use
Actually there are
to
thus keep the transistor on and prevent a shift

These pulses can be chosen to
in the output.
an
both
circuit
the
change the bias and
will
transistor
inhibit this action
will
pulses.
figure
transistors (Q-|, Q2,
transistor
INHIBI TORS
gates,
changing the polar-
inverting the signals will
NPN
or
PNP
transistors
and
either positive or negative logic.
for the
gate action of the transistor to be inhibited.
This circuit in figure 12-2
ways.
The
is
Many
only one of the
transistors are normally on.
They
other types of inhibitor circuits can
be constructed.
107
The
idea of inhibition can be
EXPERIMENT 01 100
INHIBITORS
OR, NOR, AND, and
applied
to
circuits,
and
NAND
one.
Its
Boolean expression
is
simply means to block the
it
gate,
thereby preventing a change
due
to
incoming
the
ELECTRONICS/DIGITAL
pulse.
in
output
The
inputs
AB
required usually have opposite levels, and the
Its
truth table
is
= -E,
shown
(12.5)
in figure 12-4.
inhibitor signal causes the logic signal to have
no effect
(it
inhibited).
is
equation for the circuit
on which gate
series
NOR
will
shown
gate
Boolean expression
A+
is
B +
vary depending
AB=E Q
10= 0
00= 0
01
11 =
In the case of the
inhibited.
is
The Boolean
in
figure
12-1, the
equation 12.1.
C = -E rt
=0
1
and would become

12-4
Fig.
A+
B + C = -E,
Truth Table for Inhibited
(12.3)
The output of
A+
when the other
signal at
B +
Ai
C = -E,
(12.4)
The
in figure
or "false" unless the
12-3.
is
inverted
from
= E,
that
(12.6)
symbol for an inhibited
logic
is
is
is
AB
gates are inhibited.
Another form of the inhibitor
NAND
so the Boolean expression for an
AND
inhibited
gate
can be seen
AND,
of an
With an inhibitor
NAND
shown
NAND
in figure 12-5.
circuit
The output
is
zero and the B
The
is
gate in figure 12-1
The
series
NOR
in figure
12-6.
symbol for the
logic
is
shown
shown in figure 12-7 demonthe symbol for inhibiting one or more

The symbol in figure 12-7 shows the
alteration
strates
inputs.
A-gate inhibited.
Inhibitors are used with diode gates as

well.
gate.
V^V
12-8 shows a diode inhibitor
Figure
Its
inhibitor's,
truth
is
When A and B
or B
inhibitor signal
B
O
Fig.
*^YV
12-3
Inhibited
NAND
at cutoff.
108
transistor
is
That
(inhibitor signal), neither
diodes
will
conduct
if
the
sufficient to hold the diode

is
v RL - Vl
Gate
the
have no input and with
negative voltage at
of the
like
table,
the reverse of the normal gate.
to say,
= o
(12.7)
EXPERIMENT 01 100
ELECTRONICS/DIGITAL
Fig.
12-5
Logic
Fig.
Symbol
12-6
Fig.
12-7
for inhibited
Three Input
Inhibited
NOR
NAND
Gate
NOR Gate
+v i
Fig.
12-8
Diode Inhibitor Gate

109
Gate
EXPERIMENT 01 100
where Vp|_
The equation
voltage
(negative value)
in
with
re-
the bias voltage applied
is
to R|_.
opposite
ELECTRONICS/DIGITAL
the drop across the load
is
R|_ and V-|
sistor
INHIBITORS
conducting.
to both
really says that the bias
the pulses are applied

and B, both diodes will cut off, but
If
the level can shift only to the value of -V^

because there is no voltage from the diodes
must be equal and
order to cancel and hold diode
across R|_.
off.
With diodes
D3
clamp diode
output
voltage
and B conducting, the

conduct and clamp the
will
to
the
V2
Inhibition occurs
is
When
value.
A and
cut off, but B will conduct and the output
remain clamped to
will
at
will
will
the
nullify
The same thing
happens when negative pulses appear
cause
load and E
when
at the
receive negative pulses.
negative pulses are applied to A, the A-gate

will
applied to
and B
and B
In this case the diodes
be cut off but
a positive pulse
same time
C will conduct
inputs.
and
The diode C
current to flow through the
0 cannot change.
MATERIALS
3 Transistors type 2N 1 304 or
2N1305
1
or equivalent
Resistors, values to be determined
by students
Breadboard
the above transistors
(1512- 10 megft)
1
VOM
Oscilloscope
or
supplies (0-40V)
Set of output characteristics for
DC power
3 Semiconductor diodes, type
FEM
N305
or equivalent
Function generator
PROCEDURE
1.
Choose
10
a value of
Rq which
appropriate for use with your transistor and a
is
2.
Compute
3.
Construct a circuit similar to figure 12-1.

the
4.
Vqq
of
volts.
VOM
Apply
a value of
R 1 which
is
compatible with R and an E of 10

c
s
volts.
Measure the output for no
signal input with
and oscilloscope.
kHz
pulses of the correct polarity to
and record the
results of the oscilloscope
reading.
5.
Repeat step 4 with pulses at B only and at C only.
6.
Now try
7.
Construct a truth table for this
8.
Select a value for
9.
Apply pulses to A,
all
the pulses at the same time.
and
C.
amplitude and polarity to Aj,
results.
circuit.
R2 and modify
B,
Record the
the circuit similar to that of figure 12-2.
At the same
B<|,
and
C-|.
70
time, apply inhibitor pulses of the correct
Record the
results.
EXPERIMENT 01 100
ELECTRONICS/DIGITAL
10.
Remove the
pulses
from
A-j.
Record the
results.
11.
Remove the
pulses
from
B<|.
Record the
results.
12.
Remove
the pulses from
C-|.
Record the
results.
13.
Construct a truth table for the fully inhibited
14.
Disassemble the circuit and assemble a circuit similar to that shown
15.
Calculate a value of R L for V-j = 10 volts.
circuit.
Choose proper amplitude and polarity pulses to create

this circuit and then repeat steps 9 through 13.
16.
ANALYSIS GUIDE. In analyzing these data you

inhibited. Some statement should be made as to
INHIBITORS
in figure
a diode inhibitor gate.
12-8.
Record
a gate can be
should discuss the ways
in
which
the exact time the gate
is
inhibited and under
The results of the diode inhibitor should be compared with those of the
what conditions.
transistor inhibitor. The uninhibited transistor gate should be compared with the inhibited gate.
PROBLEMS
1.
Draw
a circuit for an inhibited series
2.
Show
symbolically three, two-input
the
3.
input which
is
NAN D
NOR
gate.
Show
the truth table.
gates feeding a two-input
inhibited.
Write the Boolean expression for the network of problem two.
111
NAND
gate at
EXPERIMENT 01 100
INHIBITORS
ELECTRONICS/DIGITAL
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ELECTRONICS/DIGITAL
EXPERIMENT 01 100
INHIBITORS
E
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EXPERIMENT 01100
INHIBI TORS
ELECTRONICS/DIGITAL
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FUNDAMENTALS OF
experiment
INTRODUCTION.
bistable.
stable
01101 MULTIVIBRATORS
Multivibrator circuits consist of three basic types:
The introduction
As the names imply, an
stable
astable multi-
or free-running oscillator,
vibrator,
shot,
refers
two-stage amplifier with positive feed-
back.
has no
condition, and the monostable, or one-
component values for

made by a step-by-step
Selection of the
13-1
figure
be
will
procedure.
Characteristic
those shown
in
'b
vs
^BE^
w '"
curves
figure 13-2 (Iq vs
such
Vq^
as
and
b e necessary.
multivibrator has one stable condition.
Step
Astable multivibrators, because of their
output waveforms, are used as square wave
generators, as
frequency dividers, and for the
The design criteria for

the same as for Class A
1.
current corresponding to point
(Vqc to IcMAX^ mav

maximum power dissipation
line
resistance of this load
multivibrators
where
amplifiers
feedback
with
loop.
is
the addition
Figure 13-1
of
shows
positive
a
basic
For symetrical
=
operation, R 2
Rg4 while R B i = Rg3,
B
and R|_-| = R[_2- This allows each transistor
astable multivibrator circuit.
ON
for alternate half periods.
R|=
is
'cMAX
'
line
is
intersect
V CC^'CMAX'
tne short circuit Iq.
Since
not bypassed, this resistance adds to the
total collector circuit resistance.
RT = R E + R L
Normally R
E
less of Rj.
is
Thus
(13.1)
usually about 10 percent or
L1
'B2
5
Fig.
13-1
Basic Astable Multivibrator
115
the
The
curve.
1
^Bl
can be chosen by the designer, and the load
timing of frequency.
to be
and
mono-
multivibrator circuits.
DISCUSSION. The term multivibrator

to a
astable, monostable,
to multivibrators will begin here with analysis of the astable and
Fig.
Step
The
2.
it
should be kept
near the
point
be
portion of the
linear
bleeder
thus
Read from the curves the values
3.
V CCr Tney
anc
'BQ' 'CQ'
'
re
<
13 4
-
>
Note that the current through R B 2 at rest

will
enhance thermal stability, but more
line.
Step
most
the
Vreqêqê^Ccq+'bq)
mind
criteria so
are designing with Class
should
in
we
the
of
selected
that
load
13-2
may normally be selected
point
by the designer, but
center
ELECTRONICS/DIGITAL
MULTIVIBRATORS
EXPERIMENT 01101
current
resulting
sistance.
indicates
in
smaller
reduction of
Therefore, the advantage
Rg2,
input
is
re-
limited.
of.
As
are the values at
a rule of
thumb,
let
in figure 13-2.
(13.5)
'RB2Q- 'BQ
Iqq
to
the lg
vsVg^ curve, the value of Vg^Q may
be
read
directly
Step
By
4.
Step
transferring the value of
To determine Rg2
5.
on the base of
Vg^Q
Also
base of T^
step).
is
is
is
the forward bias
provided by
in
calculation of
R B2 ~
Vpg2.
the above
a reverse bias,
enough to offset
VggQ. The
requirement
Now
Rg2 may
be found from
13-2B).
V RB2Q
J
RB2Q
V REQ
V BEQ
(13.6)
RB2Q
required to forward bias the
Vg^Q
large
equal
T-j
figure
(VggQ was found
Since
must be
still
Z on
(point
Step
Vpg2
V R g2Q
6.
To determine R B1
it
is
seen that
Rgl and Rg2 form

Since V RB 2Q has been determined
Vqq.
a voltage divider across
and
equation relating this
previously, then
is
V,RB2Q -
REQ + V BEQ
V RB1Q _ V CC" V RB2Q
(13.2)
116
(13.7)
EXPERIMENT 01101
ELECTRONICS/DIGITAL
passing
Current
+
!rB2Q-
through
Rg-j
equals
IgQ
definite frequency
Therefore,
f~
~
where C
R B1 ~
RB1Q
RB1Q
may
This
(13.9)
RB2Q
<
desired.
1Q6
1310
UAiui
0.025C + 2.5
the cross-coupling capacitor in pF.
nonsymmetrical astable multivibrator
be designed by causing one transistor to
oscillate for a
V RB2Q
Rqi
SI"
(13.8)
is
is
MULTIVIBRATORS
is
greater time than the other.
accomplished by changing the values of
the coupling capacitors,
making
C-j
and C2
different values.
Rg^ = Rg3,
=
R L1
R L2' 3ut c ue to
of components, the value of Rg2
For symmetrical operation, recall
Rg2 = R B4' anc*

variability
and
Rg4 may
be adjusted to bring
transistors to the value
In the case of a
multivibrator there
'
'
Vq
determined
in
one transistor
of both
ON
is
monostable, one-shot,
only one stable
while the other
For reliable timing, the
step 3.
ON
be designed for saturation operation.
required.
lations
itors
the
affect
empirically
either
lations,
an
tran-
OFF, this forces the OFF transistor

Upon being driven into an unstable
condition by the external pulse, the feedback
RC
network automatically begins to bring the

circuit back to its stable state.
derived
time
constant,
formula
may
be
thus
An
used
to determine the frequency of oscil-
or to
When
ON
The cross-coupling capac-
frequency of oscillations.
affecting the
sistor
ON.
OFF.
transistor should
externally applied pulse turns the
The determination of the value of the

capacitors depends on the frequency of oscil-
is
state,
evaluate the capacitors
Fig.
13-3
if
Referring to figure 13-3,
let's
again do a
step-by-step procedure for the one-shot multi-
Basic Monostable Multivibrator
117
MULTIVIBRATORS
EXPERIMENT 01101
Fig.
vibrator, similar to the
The
multivibrator.
will
be helpful
Step
1.
in
this effort.
R E (Again R E
<
10% R T
figure 13-4
R^
and
must be drawn).
was presented
(13.13)
R B3"
B.
= R|_2
s,
(this
Again,
is
Rg2 and Rg4 ma Y
(13.27)
)
be adjusted due to
variability of parameters until the correct
separate
The same
V RB3Q_ V CC~ V RB4Q

1
RB3Q 'rB4Q + BQ (T 2
is
pro-
C-|
is
time
for the astable design:
Vq
The value of
desired amount of
The larger the C-j
obtained on both transistors.
chosen so as to get
in
the unstable state.
value, the longer the multivibrator remains
V CC/'CMAX
d3.11)
R T = R L1 + R E = R L2 +
(13.12)
RT =
the unstable state.

is
For this reason the
Oscilloscope
Variable
used to standardize nonstandard random-
timed pulses to be fed to computer
circuits.
DC power
2 Transistors, type
(15ft- 10 megft)
supply (0-40V)
2N1305
2 100 kft or 50 kft potentiometers
or equivalent
(1W)
Set characteristic curves for the
2 2.2 kft 1/2 watt resistors
transistor used
1
2 Capacitor substitution boxes

1
0.01
nF
capacitor
2 47 kft 1/2 watt resistors
Function generator
220ft 1/2 watt resistor
118
in
circuit
MATERIALS
1
Monostable
cedure can be used for determining the load

line as
R L2 = Rj
transistor characteristics
Here we chose
lines
R[_1 =
for the astable
not necessary and for unequal R|_

load
design will correspond to the
characteristic
points given
in
one
13-4
ELECTRONICS/DIGITAL
Breadboard
PROCEDURE.
1.
R|_i
= R
=
L2 2.5
kfi,
Constructthe circuit shown
Do
not connect
C-j
and C2
Rg2 = ^B4 =
R B1 = R B3 = 100
in figure 13-1
until
Step
kfi,
R E = 200ft
using 100 kfi potentiometers for
3.
and
J2
are
2N 1 305s and Vqq
2.
Start with
3.
Connect Ci and C2 and observe the output across T2. Make
4.
Double
5.
Slightly vary
6.
Measure the frequency of the output and record
7.
Disconnect the circuit and construct the circuit shown
C-j
9.
Connect
^2 anc adjust resistance values until
Rg2 and
=
Rfj4-
2V.
= Vq2-
'
a sketch of
it.
and note what happens.
one of the potentiometers and observe any change
Fig.
8.
MUL Tl VI BRA TORS
EXPERIMENT 01101
ELECTRONICS/DIGITAL
a 5
p p
13-5
1000 Hz
Notice any effect a change
in
it.
in figure
3-5.
positive pulse signal to the input
in
output.
pulse duration has on the output.
and observe the output.

Also notice any effect
the frequency of pulses has.

10.
Vary the value of the capacitor and note any change
ANALYSIS GUIDE.
In analyzing this data
in
the output waveform.
you should discuss the operation of the astable and
comparison of input and output waveforms will be helpful

monostable multivibrator circuits.
in clarifying your discussion.
Explain any changes in waveform that you observed in steps 4, 5,
9,
and
10.
119
EXPERIMENT 01101
MULTIVIBRATORS
ELECTRONICS/DIGITAL
PROBLEMS
1.
Calculate the frequency of oscillation of the circuit of the astable multivibrator and
compare
it
with the observed result from step
how the output changed
during step
6.
2.
Explain
3.
Did the base resistors change the output waveform
4.
in
step 5?
If so,
how do you
explain what occured?
II
MM
till
Mil
mm" MM MM MM'
Output Waveform of
MM MM MM
Mil
1-1
1
1
First Circuit
|j
'mm Mil
Output Waveform of Second Circuit
120
Mil
II
MM
experiment
INTRODUCTION.
Some
01110
In this
experiment the bistable type of multivibrator circuit
DISCUSSION. In a bistable multivibrator,

two stable conditions of operation:
example,
is
last
T2
saturated and
T-|
T2
Ti cutoff and
will
two
saturated.
cutoff, or
The
state.
multivibrator
known as the Eccles-Jordan

named after
flop" circuit
inventors.
its
is
also
is
state.
commonly
let's
also
used.
stable circuit
starts
is
it is
used
in
This
OFF
The
T-|
is
initially in
resistance of the
ON
tran-
be very small compared to R3, and
because of their voltage-divider action, the

collector
potential
computer
Sometimes the bi-
potential
(zero).
will
be close to ground
Referring to figure 14-1,
notice that the base bias of
the
it
other circuit actions, or a "binary"
because
transistor.
For the purposes of this discussion,
Bistable
called a "trigger" because
other
the
second transistor into the
suppose that transistor
sistor will
multivibrators are often used in a
electronic counting.
than
conduction.
"flip-
With the application of

draw more
transistor will normally
forces the
trigger circuit,
The name
one
current
Either condition
indefinitely unless an external signal
bistable
active devices.
Vqq
used to trigger the device into the opposite
for
be examined.
basic design criteria for the bistable or "flip-flop" multivibrator will be presented.
there are
for
will
collector
potential
relative values of
Rgand
of
T2 depends on
T-j
and on the
R2.
binary counting systems.
With the lower end of R3 very near to

Figure 14-1
shows
multivibrator circuit.
a typical
PNP
zero potential,
bistable
Direct coupling and
commutating capacitors are used between the
R4,
Bistable Multivibrator
121
will
be cut off.
Vq2 w '"
Rgand R^ form a
INPUT PULSE
Fig. 14- 1
T2
cut off, the voltage
With T2
approach -Vqq.
voltage-divider network
BISTABLE MUL TIVIBRA TORS
EXPERIMENT 01 1 10
Vqq
across
and the values of these compo-
even
which
in
ON
the
When
condition.
are satisfied, the circuit
in
is
will
keep
its
and
T-j,
T2 ON.
conditions are not altered.
the
If
a positive pulse can be applied to
applied to the base of Ti
through T^ to
T-j
and
-Vqq
in
the negative direction.
cation of the input pulse

great
is
This
value.
If
J2
Two
to
long enough and of
applied to the base of
is
T-j.
Fig.
positive
will
pulse only drives T^
Now
citors
and
consider
to conduct
14-2
negative
pulses
or
and
positive
This
is
sometimes not
signal
does not trigger the multivibrator.
This reduction of
T-|
applied to
be used to insure that an unwanted
the potential being
negative base potential causes
OFF,
T-j
desired reaction and additional circuitry can
will
negative and tends to go toward ground
This
is
Ti through C3, nothing
the stable state.
become sufficiently negative that T2 will

As T2 begins to
become forward biased.
conduct, the collector voltage Vq2 becomes
less
other stable state,
negative pulse could also cause a reversal of
the appli-
enough amplitude, the base of I2
(zero) potential.
saturation
transistor circuit has
dotted lines in figure 14-1) would be required.

Then each positive pulse that is applied will
cause one reversal of the multivibrator's state.
this will
action will cause the base voltage of
change
in
For another positive pulse to cause the

state to change, a capacitor C3 (shown by
to go from the zero
toward the
cumulative,
T2
further into cut off.
cause conduction
start decreasing,
cause the collector of

potential value
will
conducting
is
through
T-j
This triggering pulse
the input capacitor C3.
its
T2
less
another positive pulse

of
base
happen as
the stable state of the circuit
The
cut off.
then reached
stable
states and will remain there so long as the
To change
this action of
with the final result being
it
these conditions
one of
and
less
more and T^ conducting
nents are selected so as to maintain a negative

potential at the base of T-|
ELECTRONICS/DIGITAL
let's
remove the commutating
relabel
some
in
Basic Bistable Multivibrator
in figure 14-2.
capa-
order to
design criteria for the
This has been done
122
the resistors
circuit.
Vqq
After
we were dealing with a symmetrical multi= R

vibrator, Rg2 = ^64' anc R
BV
B3
and R|_ have been determined
If
the usual manner using collector curves and
in
load line
construction,
ON and T2
OFF
is
let's
assume thatT-j
'
the same procedure would be used to
not,
is
Since
compute the unknown resistances.
R L V BE (J^ ON) a f and V cc were
for the first stable state.
In this condition
treated
V cc
C1
BISTABLE MULTIVIBRA TORS
EXPERIMENT 01 1 10
ELECTRONICS/DIGITAL
<L1
[ci
T2
V BE
may
OFF) =
(T 2
OFF, the Iqq
being
transistor often
(14.2)
'B1
by use of the
plotted
be
R B ^.
equation for
For
the variation of R B3
constants,
R B 4 may
and
(14.1)
as
(l
of this
not be neglected.
b eeder
-l
co )R B2
(14.9)
Substituting,
B1
The current through R B
V CC
= (V cc /R L )ap =
H a
L F
_V CE
(14.3)
(T-|
'RB1
is
-|
ON)-V BE
!
(T 2
B1
OFF)
-- 'co
(14.10)
From the
we
circuit of figure 14-2
notice that
So
'rB3~
B1
V BE
(14.4)
RB4
OFF)
(T 2
R B2
=
'C2
since
^2
cut
V CC- V BE< T 1 0N
RB3
'
V CE
(T-!
ON)- V BE
(T 2
OFF)
-
R B1
CO
(14.11)
>
(14.5)
R B3 + R L2
or
R B2 =
and
V BE
(Tt
V BE
ON)
v CE
(14.6)
'RB4
R B4
(T 2
OFF) R B1
on)-v be
(Tt
(t 2
off)-i co r b1
(14.12)
and, as before, R B2 vs. R B

Substituting the equivalent values
from the
Remember
above equations,
V CC
figure 14-1?
V BE T 0N_>
<
^CC_
V BE< T 0N
R L1 a F
R B3 + R|_2
tors
were
-|
can be plotted.
the capacitors
C-|
and C2
The main purposes of the
in
capaci-
to;
>
1.
R B4
2.
Reduce the recovery time.

Reduce the transition time (which,
turn, reduces the
(14.7)
That
capacitors
is,
C-|
in
minimum pulse width).

and C2 provide base
overdrive for pulse shaping and faster switch-
From
this
we
get an expression for
R B4
ing time.
R L1 V BE (T 1 ON)a F (R L2 + R B3
VqqRl"|<>:pV be (Ti ON) - V CC R L2 - V CC R B3
)
Rd/1
B4 "
123
(14.8)
EXPERIMENT 01 1 10 BISTABLE MUL Tl VIBRA TORS
ELECTRONICS/DIGITAL
MATERIALS
Oscilloscope
2 Variable
2 Resistance substitution boxes (15ft - 10 megft)

2 Transistors type 2N1305 or equivalent
DC power
Multimeter
2 0.01
juF capacitors
2 2.5 kft 1/2 watt resistors
2 33 kft 1/2 watt resistors
Function generator
SPDT
200ft 1/2 watt resistor
supplies (0-40V)
Breadboard
switch
PROCEDURE
1.
Construct the circuit
apply the Vqq.
in figure 14-3.
Have your
check the circuit before you

Use the resistance substitution boxes for the base coupling resistors
lab partner
(47 kft).
2.5 kft
V CC =15V
TRIGGER
PULSE INPUT
Fig.
14-3
2.
Measure and record the voltages, Vq-j and Mq2-
3.
Determine from the above measurements which transistor

is
4.
is
conducting and which one
OFF.
Apply
a positive
3 volts to the base of the
Momentarily close the switch to do
this.
124
ON
transistor through the switch
and C3.
EXPERIMENT 01 1 10
ELECTRONICS/DIGITAL
VC 1 =
V C2 =
II
M-H
MM
MM MM
till
II
V C 1' =
VC2 =
1
nil
MM MM
HH
1l-H
Mil
It
14-4
II
\[
MM
nil
Mil
MM MM
Mil
till
H-+-H H-+-H
The Data Table
125
H-HHH-
M -M-H
Fig.
Mil" "mm
Mil
-ttIt-
++++
BISTABLE MUL TIVIBRA TORS
EXPERIMENT 01 1 10
5.
Measure and record

stable states.
If
V C1
'
V C2
and
the answer
is
'
ELECTRONICS/DIGITAL
again and determine whether the circuit switched
no, then repeat steps 2, 3, and
4 using
a five-volt positive
signal.
6.
Connect the oscilloscope to view
C3
to the base of
drive the base of

7.
T-|.
T2
V C2
and put
a pulse signal of
Also connect a 0.01 juF capacitor (as
about 1000 Hz through
C 4 shown
in figure 14-1) to
Record the output waveform
at
V c2
and compute the frequency. Compare
this with the
input triggering frequency.

8.
Vary the coupling

boxes).
satisfy
Then
resistances several steps
up and down (the 47 kfi on the
them to 47 kSl and similarly vary the value of C

4
yourself that you know what is causing any change that you observe.
ANALYSIS GUIDE.
reset
In analyzing these results
criteria,
resistance
Be able
you should discuss the application of the
circuit investigated to the basic design criteria presented.
covered with regard to the design
and with
special attention given to the effect of
PROBLEMS
2.
How many
How
stable states
were there
in
the experimental circuit?
did the output waveforms change
when the
value of the base coupling
tance was varied?

3.
Explain
how the
experimental circuit could be used as a counter.
126
basic
Operation of the circuit should be
varying the coupling.
1.
to
resis-
MULTI VIBRATOR
experiment
INTRODUCTION.
01111 TRIGGER CIRCUITS
General triggering power requirements and frequency limitations are very
important to practical digital applications.

factors.
We
will also
In this
operation the
ON
a transistor
OFF
is
that required to turn an
transistor
is
be supplied by the trigger circuit.
trig-
trig
normally
OFF
less
transistor
= Q B + Q BS
(15.3)
than
where Q.q = stored base charge of the
ON.
urated transistor.
The trigger circuit must furnish a sufficient amount of power to dependably turn
the transistor.
off
examine some of these
OFF, because the time required to
gered
turn
will
the stored base charge of the transistor must
DISCUSSION. To cause a multivibrator to

change states we must apply a trigger signal
Under
to correct polarity and magnitude.
normal
experiment we
look at a basic design criteria for a Schmitt trigger circuit.
If
the transistor
is
In a practical multivibrator the coupling
circuit capacitors also affect the
not
for switching.
then the trigger charge that must
saturated,
be supplied
sat-
time required
the trigger input
is
capac-
coupled, then reducing the capacitor
itively
can be approximated by
If
reduces the differentiated trigger pulse
size
duration, allowing higher triggering rates to be
This reduction
used.
limited since the capacitor
(15.1)
that
The time required to
turn the transistor off
may
Wn
also be approx-
QB
v trig
(15.4)
(Nonsatu rated Case)
(15.5)
or
(15.2)
O-B
If
must handle the
required at the base. Since
is
'mm
(0.159) h FE
is
then
imated.
OFF ~
capacitor value
Q =V trig C
where fa is the alpha cutoff frequency. Any

charge lower than Qq will not dependably
turn the transistor off.
in
quick turnoff time
is
'mm
required, then a
Q BS
V trig
(Saturated Case)
(15.6)
glance at this equation indicates the use of a

transistor
or a
with a high alpha cutoff frequency,
Emitter triggering
is
the
name
applied to
the technique of connecting the input trigger
low current gain can be used to reduce
to the emitter of the transistor
the turnoff time.
and
is
used
most effectively at lower triggering frequencies.

If
the transistor to be switched
saturation,
is
Figure 15-1 shows a typical emitter triggering
in
then additional charge equal to
circuit.
127
EXPERIMENT 01 1 1 1
TRIGGER CIRCUITS
Fig. 15-1
The frequency of the

important since
pulse
is
is
Emitter Triggering
very
the capacitors should be
normal state before the next trigger
at their
should
all
trigger
ON
constants and
constants
in
In figure 15-1 the circuit
PNP
transistors
is
constructed using
and positive
trigger pulses are
used.
For that reason, the pulse
applied.
be
ELECTRONICS/DIGITAL
for at least 5 starting time-
OFF
Let
for at least 5 recovery-
us
turn our attention
now
to a
special application of a bistable multivibrator
order to insure proper triggering.
which
common
is
Schmitt
computer
in
The
trigger.
circuitry, the
chief uses of a Schmitt
trigger are:
For base and collector triggering, the
same basic requirements are necessary

emitter triggering.
triggering
is
as for
(1)
To
(2)
To
convert or reshape sinusoidal or
rectangular waveforms
point to note about base
that the signal frequency at the
detect the presence of a
signal.
collector will be one-half the triggering fre-
quency.
Consequently,
multivibrators
Figure
are
15-2
and figure 15-3
sometimes used to divide pulse rates by two.
is
is
a basic
its
Schmitt
trigger
associated waveforms.
Rather large pulses are required to trigger a

multivibrator at the collector.
However, the
output waveform with collector triggering
The
is
that the stable state of
usually the most square of the three types.
will
=
R L1 = R L2 R B1 = R B2 R
B3 R B4
;
circuit in figure 15-2
remain
until
T 2 ON
input
designed so
and
When
this signal
to the base, the circuit flips,
(15.7)
725
T.j
OFF
of pre-
signal
determined magnitude and polarity
to the base of T-j.
= C
2
an
is
is
applied
is
applied
and the other
EXPERIMENT 01 1 1 1
ELECTRONICS/DIGITAL
TRIGGER CIRCUITS
10V
Fig.
Fig.
stable
state
opposite
15-2
Schmitt Trigger Circuit
Waveforms For a Schmitt Trigger
15-3
ON, 7"i OFF will be assumed, and the value of

Vg^, (T2 ON) must be known, as well as the
hold until a signal of the
will
polarity
and
sufficiently
large
is
applied to the base of
Ti to shut it off again.

By varying the potentiometer R^, the trigger
level at which the

may be changed.
We
values
can
for
following
transistors
determine
the
Schmitt
process.
The
value
change state
circuit
trigger
stable state of
at
which the
V RE, Q - V RB2, Q ~ V BE<
component
using
Ej,
circuit
(T 2
must
ON)
<
flip.
15 8 >
-
and
the
T2
i,
129
min
V BE, min
(Tj)
+ V,
V RE,Q
(15.9)
For our circuit Ej
ELECTRONICS/DIGITAL
TRIGGER CIRCUITS
EXPERIMENT 01 1 1 1
-2V and
Vg^ q
transistor
= -0.2 V
This implies that
We
can
V B E,
(T
for
solve
VR
q = -1.8V
p_
V RB2
we know
if
be computed
VRB2,Q =
-2
1V
'C2,
ON
'RE,
_ h
FE
_I C2,
(15.10)
select a bleeder current of say
0" 4
1
of the
ON
'b2,
(15.13)
ON
B2,
(15
ON
4)
V RE, Q
(15.15)
amps,
R|_2
then
hp^
known.
is
RE,
we
the
Therefore,
Therefore,
If
if
and
= -- 3V
ON)
may
Rp_
VrB2 Q
'
B2"l bleeder
may
V RL2
= 21 kfl
be determined by
V CC
V CE,
(15.11)
(T 2
ON)
V RE,
q]
V RL2
l
and
R bl + r Ll
By choosing
V CC-Vr B 2,Q
'bleeder
value of Rjj.
'b2,
L2"i C2, ON
=
(1512)
V CC "[ V CE,
ON
'C2,
we may compute
With this
the circuit
Rg-|.
ON) + V RE, q]
(T 2
ON
in
mind, using the obtained
in
figure 15-2
is
values,
ready for operation.
MATERIALS
1
3 Resistance substitution box
Oscilloscope
2 Transistors type
2N 305
1
(15ft to 10 megft)
or equivalent
Capacitance substitution box
Function generator
DC
2.2 k2, 1/2 watt resistor
2 k2 potentiometer
Breadboard
transistor
power supply (0-40V)
PROCEDURE
1.
Use
2.
a collector voltage of
Apply
in
Vqq
a sinusoidal input of
figure 15-4 using your computed values of R|_ 2 and Rg= 10V. Record your values on the diagram.
1000 Hz and observe the amplitude necessary to
circuit.
130
trigger the
TRIGGER CIRCUITS
EXPERIMENT 011 1 1
Fig.
3.
When
the input
15-4
triggering,
is
ELECTRONICS/DIGITAL
determine the frequency of the input and output waveforms
and record them.

4.
Slowly increase the input frequency to 10,000 Hz and observe the output waveform.
5.
Reset the input frequency to 1,000
Hz and vary the emitter
resistor.
Note any effect
it
has on the output.
ANALYSIS GUIDE.
analyzing these results the general triggering considerations of the
In
multivibrator should be discussed, including the

Also discuss several practical applications for a
power requirements and frequency
Schmitt
Input
+++- till
""
I
limitations.
trigger circuit.
Output
II
lilt
l)
ll
Fig.
15-5
The Data Tables

131
-H-+4
EXPERIMENT 01 11 1
ELECTRONICS/DIGITAL
TRIGGER CIRCUITS
Output
Output
MM MM MM MM* MM MM
Fig.
15-5
H-H- -H-+-+.
PROBLEMS
1.
In step
3 of the procedure, was the frequency out one-half the input frequency?
Explain.
2.
What
3.
Explain what happened as the input frequency was increased.
effect did varying the emitter resistor value have?
132
"-
'""
INTEGRATED
10000
CAE
CIRCUIT
FLIP- FLOPS
INTRODUCTION. Computers
computations.
how
consider
will
In this
use literally thousands of multivibrators to perform their

experiment we are going to examine an integrated circuit flip-flop. We
the operation of the IC
is
similar to that of a discrete
component
flip-flop
circuit.
DISCUSSION.
its
modern computer makes

transistors ON and
by turning
calculations
OFF.
These transistors are arranged
types
of
counters,
circuits,
including
shift
ring counters, etc.
in
many
registers,
These
circuits
The
Counting
design.
and
ers,
circuits
of multivibrators fed
strings
are
made up of
by
gates, invert-
The electronic signals are

through the computer to the output
routed
triggers.
devices (card
storage)
punches, printers, tape, and disk
by these building-block
circuits.
Each integrated
module contains many

components (or the equivalent) for a
number of the discrete circuit building blocks.
Back at the beginning of the electronic

development, the most common
devices available for constructing these build-
blocks were
same
the
vacuum
be
to
effort
tubes.
The
idea
as for transistors but the size
requirements for
was
and
vacuum tubes required much
toward cooling the

All of these problems created a
machine.
directed
limitation in the practical handling capabilities
of the
For instance, a typical IC
AND
several
stable
gates
and some
multivibrators).
representation appears
may
contain
flip-flop
typical
(bi-
schematic
in figure 16-1.
This
is
many
applications. We can recognize

the representation as being. DTL logic.
Figin
ure 16-2 shows a logic symbol representation

of
this
symbol
same
Actually,
circuit.
representation
the logic
usually the
is
Although the schematic
useful.
is
most
drawn
using conventional symbols, the actual oper-
only approximates this
ation
enough to know that the

the logic symbols indicate.
circuit.
It
is
circuit operates as
vacuum tube computers.

The
With the advent of the transistor, designers were able to greatly decrease the size,
and operating temperature of any

computer by simply using transistor
weight,
given
multivibrators,
The
etc.
size reduction
given
area
flip-flop.
The
is
commonly
stable state of the
not discernible from the diagram.

Since both states (condition ON or OFF) are
circuit
is
is
dependent on the
application of a trigger pulse and the immedi-
allowed more circuits
and the capacity of the
The
called
bistable multivibrator
stable, the particular state
diode gates, transistor gates,
machine could be increased.

ing
circuit
a highly versatile building block that can be
computer
in
some of
carries
these refinements to an even higher degree.
used
of
circuit
be considered building blocks for logical
can
ing
integrated
ate past history of the circuit.
We do know
that in each state one of the transistors
fast switch-
cutoff while the other
times of present transistors allow more
ure
computation per unit of time.
in saturation.
16-3 shows a general circuit for a
stable multivibrator.
133
is
is in
Figbi-
EXPERIMENT
10000
AC FLIP-FLOPS
ELECTRONICS/DIGITAL
EXPERIMENT 10000
ELECTRONICS/DIGITAL
AC.
FLIP-FLOPS
'CC
0 0 0 0 0
Ly rj-LL T- d
J
KEY
'
O 0 0 0
GND
CP
76-2
F/y.
Aoflr/'c
Symbol Representation of an IC Unit

-O-v cc
Y1
'L2
WAr
OUT
nouT2
3r
'C2
'C1
GNDQ
O GND
7 6-
F/fli
If
then
Vg
is
1
in
saturation and
Q2
is
,4
Bistable Multivibrator
C3
at cutoff,
V c2 = V cc and V C1 = V E The voltage

will be less than V
Capacitors C and
E
1
are
sition
135
Capacitor C
2
constant during the tran-
speed-up capacitors.
serves to keep
from one
VE
state to the other.
EXPERIMENT 10000
ELECTRONICS/DIGITAL
FLIP-FLOPS
I.C.
O-v cc
-O GND
When
Ql
a trigger pulse
is
Direct Coupled Flip- Flop
16-4
Fig.
Any
applied so that
driven to cutoff, the circuit changes to
is
the other stable state where Q-| remains in
Q2
cutoff and
these
^C1
Vg.
remains
remains
conditions,
^CC' ^C2
Another
in saturation.
Ê'
anc
^B1
'
added.
input
ess tnan
other
'
would cause the
trigger pulse
or
less
logic
are
will
The
first
input
multiple
a set or reset input
directly
a logic circuit
is
the switching device.
into
There are usually two outputs, one
So we see that the flip-flop consists of

two common emitter switches. The two are
for a
connected so that the output of the
figure 16-5.
and the other not
NPN
The
or Q.
reset-set flip-flop
The
gates.
which goes more
circuit to revert to the first condition.
first is
Usually each side of the flip-flop
through
is
becomes
flip-flop
input and output circuits
have two inputs.
Under
unchanged,
'
basic
when
flip-flop
clock input
logic symbol
illustrated
is
is
labeled
in
usually present
the input to the second, and the output of
to provide automatic reset at a given clock
the second
frequency.
the input of the
is
general circuit
is
is
The operation
same as that
essentially the
In
The circuit can be triggered

by application of pulses of the proper magnitude and polarity to any one of the trandescribed before.
An
sistor terminals.
is,
the
ON
and
to
urating type
go
is
slow operation
many
into
NPN
flip-flop, neg-
ative trigger pulses are applied to the set input
when the
is
flip-flop
is
in
the opposite state and
to be brought back to the
initial
condition.
negative pulses can be applied to the reset
or
may
input and the bistable will switch states. The
further classify
flip-
application of the negative signal pulses to the
may
saturation.
The
the easiest to build, but
makes
the case of the
output.
in its
times
flops as to whether or not the transistor
allowed
16-1
When
OFF
We may
not be equal.
in figure
may be
astable flip-flop
symmetrical or nonsymmetrical
That
This can be seen
labeled Cp.
the direct-coupled bistable
multivibrator of figure 16-4.
of this circuit
Another
first.
it
less
desirable
the reverse condition
logic input or reset of
is
to
sat-
T2
0.
Qi
is
desired, the
will flip
it
from
Negative pulses to logic input or
set of
from normal 0 state to 1.

(These are labeled Set and Clear or Sq and
Cq on many ICs).
its
in
practical applications.
136
will
flip
it
EXPERIMENT 10000
ELECTRONICS/DIGITAL
OUT
(Q)
IN (ONE)
SET (ONE)
OUT(Q)
LOGIC
RESET (ZERO)
1&5
Fig.
Before
we go
further
it
is
Logic Symbol
worthwhile to
the
to
vious
casual
Unlike basic
and
When
is
is
required which will not
going from one state to the other.
by mechanical switching methods.
mechanically trigger the set and reset of an
may
integrated circuit and therefore create a pulse
open
actually
in
of a millisecond. Therefore,
The circuit which will be used in this

experiment takes advantage of the ability to
circuits,
integrated
mechanical switch
bounce
only the set
(ZERO)
sensitivity of the clock pulse, a
triggering circuit
observer.
DTL
in a fraction
due to the
not always ob-
IN
can be
of the
reset
triggered
which
circuits
(ZERO)
NPN Flip- Flop
times
consider a particular triggering limitation of

integrated
FLIP-FLOPS
(ONE)
LOGIC
AC.
and
close
is
circuit
closed,
(bounce)
it
of the desired type.
several
MATERIALS
2 Integrated circuits type
2
1
SN 15845
or equivalent
sockets
DC power
Oscilloscope
DPDT
switch
supply (0-40V)
PROCEDURE
1.
Very carefully plug the IC into the socket.
Observe the key mark as shown
in figures
16-6 and 16-2.
2.
Using figure 16-2 as a guide, hook up the power supply to provide Vqq.
Do
3.
Vqq
= 5V.
not turn the power on.
Connect the
DPDT
switch so that a low input V(0) =
either the set or reset terminal
when
desired.
137
OV = ground may be
applied to
EXPERIMENT 10000
I.C.
ELECTRONICS/DIGITAL
FLIP-FLOPS
G)G)G)G)G)G)G)
KEY
Fig.
4.
When you
The IC Socket
16-6
and the polarity of the Vqq are right, turn on the power
supply and record the output of this "triggering circuit" when a low input is applied to
are sure the circuit
the set and reset terminal respectively.

cuit
which
These ICs use positive
supply the necessary pulse so that
will
logic.
we can examine
We now
have
cir-
the different modes of
operation of our ICs.

5.
Turn the power off and connect

circuit"
is
a circuit so that the output, Q, of the "triggering

applied as the clock pulse of the other IC (leave the arm of the switch in a
The
neutral position).
V cc
6.
Turn the power supply on and observe

gering circuit").
change
7.
and the IC must have a
triggering circuit
common ground
and
= 5V.
it
Connect
If
is in
the
state
and Q, the outputs of the IC (not the "trig(high state at 5V) use the "triggering circuit" to
to the 0 state.
a
"high"
level
input to
S-j
and
"low"
level
input to
C^ Now,
using the
"triggering circuit", apply a pulse to the clock pulse input of the IC and observe
and Q.
8.
Reverse the inputs of step 7 and apply another clock pulse while observing the outputs.
9.
Fill in
0.
Repeat steps
6,
11.
Short inputs
S-|
2.
13.
as
much
of the R-S
Mode Truth
Table, Figure 16-7, as possible at this time.
8 and 9 using inputs S2 and C2.

to S
2 and C1 to
C 2 and
repeat steps
Turn the power off and short terminals 4 to 9 and
Turn the power on and
1 1
collect the data necessary to
7,
8 and
to 6.
9.
The
IC
is
now in
the J-K mode.
complete the J-K Mode Truth Table,
Figure 16-7.
ANALYSIS GUIDE. The
results of this experiment should be compared to the theoretical

operation of a discrete flip-flop circuit. Discuss any difficulties that you encountered in carrying
out the experiment.
138
EXPERIMENT 10000
ELECTRONICS/DIGITAL
R-S
Mode Truth Table

*n
Outputs
Inputs
c2
c1
s2
S1
FLIP-FLOPS
I.C.
Q
t
bit
time before
clock pulse
bit
time after
-J
clock pulse
= no input, terminal
left floating
Indeterminate
J-K Mode Truth Table

Vi
Triggering Circuit Data
Outputs
Inputs
Si
Cl
Outputs
Inputs
s1
Fig.
16-7
The Data Tables
PROBLEMS
1.
What
2.
What would be the
3.
Would
are the basic differences
it
between PNP
logic
effect of clock pulses at the
and
Cp
NPN
logic?
input of the IC?
be possible to complement the IC logic flip-flop? Explain.
139
experiment
INTRODUCTION.
circuits.
In this
BLOCKING OSCILLATORS
10001
Multivibrators can be used as logic pulse generators as can a variety of other
experiment we
We
called a blocking oscillator.
will investigate circuits for a self-gated pulse
will
examine the design and waveforms for
generator usually
several basic types
of blocking oscillators.
DISCUSSION. A blocking
the
oscillator has the
feature of being able to cut
itself
prescribed period of conduction.
markings on the transformer.
polarity
These
off after a
indicate connection
When
the base.
mally be used to provide positive feedback
the only current flow
from the output to the input of the
is
monostable.
The
may be
circuit.
either astable or
astable circuit
is
The monostable blocking
lator
is
development of
a favorite for
the
will
the circuit
180
will
induce a voltage
will
logic
energized,
the collector circuit
in
in
the
base winding
The base voltage (Vg^)
forward bias the base to emitter junction.
Forward
oscil-
is first
This leakage current Iqq,
leakage.
of the transformer.
used as a
source of pulses and as a generator of saw-
tooth waves.
that a
phase shift occurs between the collector and
In a block-
ing oscillator circuit, a transformer will nor-
Blocking oscillators
so
of the
bias
increase
Iq,
base-emitter junction
and Iq will increase
Vgg
times with
some more.
This increasing cycle will con-
short pulse duration are readily obtainable.
tinue until a
Like the Schmitt trigger, blocking oscillators
is
maximum amount of bias voltage

This maximum will occur when
are also useful in pulse shaping.
the transformer or collector circuit are driven
pulses.
Very
fast rise
and
fall
reached.
into saturation.
Figure 17-1 shows a basic astable com-
mon emitter
will
blocking oscillator circuit. Notice
field
That
is,
momentarily there
be no further change
in
the magnetic
around the collector winding of the
-O v cc
TR
Fig.
17-1
Common
Emitter Blocking Oscillator
140
EXPERIMENT
ELECTRONICS/DIGITAL
10001
*3
*1
w
I_l
o
>
111
CO
>
TIME
'CC
TIME
Fig.
the
sistor
in
will
Therefore,
drop
in
the flux at
Figure 17-2 shows the
itself.
waveforms associated with the base and
no
Note carefully the
longer
collector
be
forward
current
lector
biased.
EMF
in
col-
during the oscillation cycle.

relative
phase relationship.
to
The
develop in the collector winding inducing a

reverse voltage
circuits
This
drops.
collector current causesa back
in
then repeats
no voltage will be
the base winding; and the tranwinding,
collector
induced
Blocking Oscillator Base and Collector Voltage Waveforms
17-2
With no change
transformer.
the base winding.
These
cutoff,
instant the transistor
is
driven into
the collector voltage spike
is
much
voltages will act to drive the transistor into
higher than the collector supply voltage. This
cutoff.
is
function of the transformer winding,
which acts as a voltage source that

While
the
transistor
the capacitor, C|,

current,
lector
stops,
was conducting,
was charged.
C-|
When
ing
base
The
maintain
current
voltage at this point
Vqq
discharges until col-
current can flow again.
to
and
the'
EMF
(Iq)
(Vq^)
is
is
attempt-
The
the sum of
flow.
of the transformer winding.
This represents a peak voltage which
cycle
141
may
EXPERIMENT
BLOCKING OSCILLA TORS
10001
ELECTRONICS/DIGITAL
O Ycc
CLAMP
Fig.
17-3
Protected Blocking Oscillator Circuit
exceed the breakdown potential of the

base
lector
There
junction.
apparent fault with this basic

collector
extra winding allows the addition of diodes
col-
one other
is
across
The
circuit.
The
negative excursions.
purposely driven into saturation.
is
for the limiting of both positive and
it
shown
in
figure
third
winding
is
7-4.
This causes the circuit to suffer from the

full
effect of storage time delay
and
Astable blocking oscillators
there-
fore sets the lower limit of pulse duration.
constructed using the

uration.
For these reasons, the basic circuit

modified
usually
to
Diode
figure 17-3.
shown in
a voltage clamp which
collector from going
the
D-j is
prevents the transistor
Diode D2
placed
winding to
transformer
the
field.
quickly
transistor
When
is
while
the
the transistor
reverse biased
cuit, saturation of the
D2 becomes forward
D2
in
the previous
transformer core or
cir-
tran-
allows no further flux changes, and the
from the secondary. The capacitor,
discharges the emitter to the base, reverse

ing the junction
cutoff.
and
is
C-j,
bias-
driving the transistor into
The time required
the cutoff region
biased
discharges the transformer winding
induced voltage stops, removing the forward

bias
instant the transistor goes
into cutoff, diode
and
sistor
cutoff.
conducting, diode
forward biases the emitter junc-
the bias at the emitter. As
and has no effect upon the
At the
circuit.
is
in
base config-

two voltage supplies.
voltage into the secondaryand further increases
is
This happens very

is
V^^
common
also be
Collector current flows and induces
tion.
provide a path for the discharge of the voltage
due to the magnetic
is
requires
circuit
Voltage
circuit
deep into the saturation region.

across
The
is
This circuit
may
for the transistor
in
equal to the time required
for the capacitor to discharge.
at
zero.
Often
a third
winding
is
With the voltage on C1 at zero, the
provided on the
transformer for coupling the actual output

voltages.
The major advantage of
circuit
in
is
its
flexibility
this
of design.
source
V^^
will
tor and start a
type
The
transformer
142
bias
again forward bias the transis-
new
cycle.
prevents
The diode across
transistor
the
breakdown.
EXPERIMENT
ELECTRONICS/DIGITAL
10001
OUTPUT
CLAMP
Fig.
17-4
A Common
Emitter Blocking Oscillator
with Transformer Coupled Output
17-5
Fig.
Common
of
base and
Common
common emitter forms
the blocking oscillator exist for the
stable version as well as for
both
the
source
of
the
trigger
conducts.
creases
Regenerative feedback
the forward
bias
on the
the astable.
For
until either the transistor or the
reverse
bias
core saturates.
monostable types,
cutoff until a trigger pulse
sistor
mono-
must be used to keep the transistor
application
Base Blocking Oscillator
is
applied.
pulse,
Then the
transformer
transistor will
drop
back to cutoff until the next trigger pulse
in
Upon
applied.
the tran-
143
in-
transistor
is
EXPERIMENT
BL OCKING OSCIL LA TORS
1000 1
ELECTRONICS/DIGITAL
Ov cc
_TL
'CLAMP
Fig.
17-6
monostable
stable
blocking
the
state,
-Vgg.
Common
Emitter Monostable Blocking Oscillator
common
emitter
For the
oscillator.
voltage
base-to-emitter
The
actual reverse bias
instant of cutoff
collector
current to flow and
Just as
the astable circuit, the transformer
in
V Reverse
The base
'1-
rate
is
rent until D-| conducts, limiting the voltage to
when
No
voltage
With the
winding.
is
induced
in
the base
collapse,
and
-V BB-
maximum
The
trigger
the time constant R-jCi-
of collector current,
fall
this
induces an
is
is
low,
opposite
the amplitude of the
sensitivity
circuit will trigger
the
Vgg
trigger
polarity voltage across the collector winding.
This reverse pulse of voltage
Vgg
If
point
so
great
trigger pulses can be small.
where the
the field around the collector winding begins
to
discharges through
C-j
saturation occurs, and the
magnetizing current of the collector becomes

constant.
(17.1)
(
bias returns to
major limiting factor for
base positive and increases the collector cur-
a safe value
v BB + v
Bias
During the stable period,
This drives the
voltage.
given by
drops.
induces a base voltage of opposite polarity
from the collector
transistor at the
is
Application of an input trigger causes
Vq^
is
on the
will
on
is
on noise alone.
make
the circuit
is
reached
that the
Increasing
less
likely to
noise, but will also require a higher
amplitude trigger pulse.
induced into
the base winding and drives the transistor into

cutoff.
r>2 discharges the collector
The common base monostable blocking

Positive
is shown
in figure 17-7.
winding
oscillator
and prevents breakdown.
trigger pulses cause collector current to flow
through the transformer primary. This causes
When
the
transistor
is
in
the
a forward bias
active
region (briefly), the bias developed across the
base winding has to be greater than

base
increase
Vgg. The
current develops a charge across
in
corresponding
until
C-j.
144
on the emitter winding.
An
collector current results with a
increase
in
emitter
current
the core of the transformer saturates.
EXPERIMENT
ELECTRONICS/DIGITAL
BLOCKING OSCILLA TORS
10001
TRIGGER
JL
T~
'EE
Fig.
When the core

emitter
17-7
saturates,
R-^C-j
present and collector current starts
is
The dropping
induces an
EMF
the
drives
ductance
in
magnetic
cuit are
not so
and the
common
emitter circuit.
negative,
Ci then discharges
and the transformer secondary.
transistor goes to cutoff.
is,
through
source
R-|
The two voltages
EMF)
cutoff.
are
(C-j
in-
(L).
The feedback requirements for
of opposite polarity across
emitter
time constant and the secondary
collector current
The decrease
primary.
field
Base Monostable Blocking Oscillator
no feedback to the
dropping.
the
Common
CC
discharge and secondary
in
fact,
critical
paralleled
The feedback loop

by the reverse
The same
-Vgg.
this cir-
as they are for the
sensitivity
bias
and
stability conditions are appropriate for this
added and hold the transistor in

trigger rate is limited by the
circuit
The
were
as
for
the
common
emitter
circuit.
MATERIALS
2N 1 304 or equivalent
sheets, 2N 1 304
Transistor type
Set of data
Resistance substitution box
DC power supplies
Oscilloscope
2 Semiconductor diodes (low forward
(15fi to 10 megft)
drop)
2 Capacitance substitution boxes

1
(0-40V)
Function generator
Pulse transformer with 3 windings
Breadboard
PROCEDURE
1.
Determine the proper clamp voltage for the data sheet.
2.
Assemble a
circuit for the
common
emitter diode protected blocking oscillator, such as
in figure 17-1.
3.
Apply the proper clamping voltage
4.
Apply the proper
Vqq
R-j
V cl_.
for oscillation (probably in the vicinity of 10V).
Be sure to
some adjustment.
Start high.
observe the proper polarity.
Record the values of
at
R-j
and
C-|
andC-j.
145
will
require
EXPERIMENT
5.
10001
Observe the
Vg^ waveform on
values, frequency,
6.
7.
rise
Observe the
waveform on the
and
time on
rise
Record
the oscilloscope.
its
maximum and minimum
time on a sketch of the waveform.
values, frequency,
Record
oscilloscope.
a sketch of the
its
maximum and minimum
waveform.
Vary the capacitor

any changes
8.
and the
ELECTRONICS/DIGITAL
in
one step above and one step below the present value and
the Vgg and Vq^ waveforms.
Disassemble the circuit and assemble a
common
record
base monostable blocking oscillator
similar to figure 17-7.

9.
Choose the proper

sheet)
and
trigger pulse
10.
-Mqq
bias (-V^
E voltage to prevent transistor breakdown (see the data
compatible with values of R-j and Ci for oscillation with a 3V input
)
(low frequency).
Record the values of

frequency, and
rise
R-j'
and Cy.
time on
Record the
maximum
voltage,
minimum
waveform of the output from
a sketch of the
voltage,
collector to
ground.
11.
Vary the input pulse frequency and record the
resulting change.
12.
Vary the input pulse amplitude and record the
effect.
ANALYSIS GUIDE.
In analyzing these data,
two types of blocking
oscillator.
The
you should discuss the output waveforms of the

R and C should be noted as
effect of different values of
well as the effects of varying the amplitude and frequency of the input pulses.
PROBLEMS
1.
A common
emitter blocking oscillator has a
across the transformer

2.
3.
Determine the phase
What
is
is
50V. What
is
Vqq
of 10V.
the actual value of
The
voltage induced
Vq^?
shift in the following transformers.
the effect of lowering the value of
Vg B
in a
'common
emitter blocking
oscillator?
4.
List the
components which determine the maximum
emitter monostable blocking oscillator and of a

oscillator.
146
common
trigger rate of a
common
base monostable blocking
EXPERIMENT
ELECTRONICS/DIGITAL
10001
R1
C1
MM
Common
Effects of
MM MM MM MM MM MM MM MM
il
Emitter
Vg^
varying
R,
Effects of
varying
MM MM MM MM MM MM MM MM
Cl
Common
Emitter
Vq^
R 1-
Mil
Common
Effect of
1
1
Emitter
MM
Mil"
Vqq
varying trigger frequency
Effect of varying trigger
amplitude
Fig. 17-8
The Data Tables
147
II
Mil
II
MM
II
experiment
10010
INTRODUCTION. As we
deal with logic circuits and logic generators,
becomes apparent that

and keep track of the pulses generated. One such storage
the two-diode storage counter. In this experiment we will examine a simple staircase
some means must be devised to

circuit
is
TWO-DIODE STORAGE
COUNTER
generator.
We
will
DISCUSSION.
select
look into the storage method and characteristics of this circuit.
name
given to a two-diode counting circuit.
This
Staircase generator
is
counting circuit has the ability to store the
on
effect of pulses
predetermined count
input and to trip at a
its
level.
The
rate
disregard the volt-
let's
age-operated discharge switch and

itself.
at
which
charge
will
C-|
is
RC
determined by the
time constant of C
1
and the sum of the diode resistance plus the
generator
(around
resistance
many
generators).
very
small
duration,
For the present,

only the counter
it
When
compared
the V-|
to
500
kft
for
time constant
this
the
input
is
pulse
value will
charge to the
(V^j = E).
amplitude of the input pulse
consider
While
Refer to figure 18-1.
C-| is
charging,
D2
and the voltage across C2

After the pulse
is
will
will
not conduct
remain
zero.
Cj is left with a
= E across D1 and in
Because the polarity
past,
The output waveform for this circuit is

shown in figure 18-2. The capacitor at the
charged voltage of
input allows us to assume a starting point for
cannot conduct. C
1
wants to discharge, however, and does so
through the source, D and into C
2
2 C 2 will
charge to equal the voltage at C1 (V
=
C1
the voltage of zero volts.
Ci
is
zero as
is
The
initial
the charge on
apply an input pulse, the
C^ to charge through
first
C2
charge on
When we
one
V
C2
1
series
is
D 2 and
with
reversed for D^,
it
will
cause
V C2>-
D-j.
"1
f+
l\
nr
~c
VOLTAGE
OPERATED
DISCHARGE
E0
SWITCH
>
-O
Fig. 18-1
Two-Diode Storage Counter

148
18-2
Fig.
TWO DIODE STORA GE COUNTER
EXPERIMENT 10010
ELECTRONICS/DIGITAL
Input Output Waveform Correlation Two-Diode

Storage Counter
The time constant Rq2 (C-j + C2) must

small compared to the pulse off
in order for the voltages Vq-j and Vq2 to
To complete
time
stabilize.
For this reason, C2
At some preestablished reference value (voltage level on C2),

the switch closes to give an output. As the
ordinarily
is
chosen quite large compared toC-j. Therefore,
change
the
in
C2
voltage across
will
the counter, a circuit switch
must be normally open.
quite
be
the switch will be reset to
charge leaves
be small
original
its
state
ready for the next cycle.
compared to Vq-j.
During
of
the
next
more charge
first
than was the case for the

successive
input
pulse
slightly
first
pulse.
will
will
The output,
as
shown
Among them
are blocking
unijunction transistors, and neon
cause
Let's
in figure
examine what
plest circuit
progressively smaller voltage step at the output.
purpose.
pulse, the
be
will
of switches can be used for
bulbs.
Because C2 has
in
some initial charge from the

amount of voltage transferred
Each
this
A number
oscillators,
This stores
that pulse discharges into C2.
a little
less
input
Vq-j again charges to E and at the end
pulse,
of
time
the
18-2,
staircase generator
greater than this because the
put
amplitude asymptotically.
149
is
staircase action.
18-3.
rent) at
approach the value of the input pulse
possibly the sim-
is shown in
The bulb fires (conducts curabout 70V. The input pulse must be
neon bulb
figure
is
and examine the
approximately
equal
maximum
to
the
out-
pulse
TWO DIODE STOP,A GE COUNTER
EXPERIMENT 10010
A Neon Staircase
18-3
Fig.
Generator
amplitude.
maximum
will give
stage
The circuit shown in figure 18-3

you about five steps with the bulb
on the
firing
trailing
The action of the

before,
scribed
edge of the sixth step.
circuit
with the
is
is
more
about
steps for one
ten.
Because
of
step size with the number
in
of steps, counters
trigger point
number of
practical
of storage
decrease
this
exactly as de-
70V
ELECTRONICS/DIGITAL
may be cascaded
to obtain
steps.
of the bulb setting the predetermined count
We
level at Q,2-
and
The number of
may
be increased by
in
Decreasing
capacity of
the
increasing
steps
can write equations for the number
size of the steps.
circuit
figure 18-4 will be helpful in understanding
the mathematics.
C2 will decrease the number

The counting ratio may be in-
The equivalent
This circuit represents the
when diode D2
conducting,
the capacity of
circuit state
of
represented by S. Writing the equation for the
steps.
creased by raising the voltage at which the
comparator (bulb)
practical
because
Q>2
value
the
is
soon
reliability
reached,
of
voltage across
A maximum
responds.
the
difference voltages per step
that
noise
and
across
Fig.
become
fluctuations
voltage obscure the action.
18-4
j),
however,
level
becomes uncertain as the steps approach

and closer to the pulse amplitude E.
small
at the first step (V n +
as
we have
vn
closer
The
C2
is
in
vn
<
V -V n
>
cTTc:
so
the
where n
Normally, the
is
the
number
of the step.
Equivalent Circuit for Calculating Step Voltage
150
(18.1)
Since the change

j
proportional to
in
Vn
TWO DIODE STORAGE COUNTER
EXPERIMENT 10010
ELECTRONICS/DIGITAL
Vn
V [A(V n -
-V, then
it
will
Therefore, the voltage for each step (V
V)]
can
be calculated using
vary
exponentially with n as seen in figure 18-2.
the exponential charge relationship
Thus,
Vn
= Ae an
V n -V
is
V-(V-V
(18.9)
l)5T
(18.2)
The
step
difference in level between the n
total
and the n +
step
is
where A and a are circuit constants determined

by the characteristics of the actual
components
V n+1-V n
involved.
-M
(v
v n -v n+1
(V n -V)
+ C2
D =
f_J_^ Aean
c i + c2
(18.10)
An example might
we have
a(n +
-c7Tc 2
(18.3)
Substituting equation 18.2 into equation 18.3,
Ae
18-4 )
mv
C2
is
9 times
V-
Suppose that
help.
larger
than
My = (110-
10) =
100V
which renders
but
a =
n
c
C2
Tn
+c
2
(18.5)
C 2 =9C 1
or
C2
c7Tc^
9
= 10"
or
So
V n- V
A laTrc1
2
'
= 10V
(100)
(18.11)
So
The
Vn
c2
+ A[ ^
)n
first
(18.7)
100
Now,
and
is
for n = 0,
Vn
The tenth
step has a level of 10V.
step has a level of:
= some voltage V^,
1-:
^)-(to")
(
10=1v
(18 12)
-
defined as
Storage counters are limited to counting
= V-j-V
pulses
(18.8)
757
which are
all
the same.
This
is
true
EXPERIMENT 10010
because the step
determined
by
charge
leak
will
(and dependability)
level
the
on
charge
off through
matter what type device
is
The counter may be used with
is
This
the
load
ELECTRONICS/DIGITAL
input pulses with
D2 and
no
used as a discharge
is
The capacitor must be able to charge

means its size must be
relatively small.
Where storage counters can
charging
C-j
thereafter through Di-
that the step at
C2
will
first
One
positive
through
difference
occur at the leading

The counter may be
switch.
edge of the input pulse.
quite rapidly, and this
operated with either polarity of input pulse

by reversing the polarity of the diodes. When
much cheaper then
be used, they are
binary
this
is
done, the output steps
will
also be
reversed.
counters.
MATERIALS
Neon bulbs w/socket type

NE51 or equivalent
Oscilloscope
Breadboard
(150-10
meg)
4 Diodes type
N34
or equivalent
Function generator
PROCEDURE
one shown
1.
Connect
2.
Apply 45V negative pulses of appropriate duration
3.
Observe the output on the oscilloscope.
4.
Record the number of steps and sketch the waveform, (each cycle)
5.
Measure the amplitude of each step and record the
6.
Calculate the amplitude of each step using the circuit values measured
7.
Observe the output across the 2.2 k2
a circuit similar to the
in
figure 18-3.
resistor,
at a rate of
results
about 100 Hz.
on your sketch.
in
equation
and record the waveform and
18.9.
its values.
(Don't forget the frequency.)

8.
Decrease the value of
and increase the value of C2 by two steps on the substitution
C-j
boxes.
9.
Repeat steps 2 through
7.
10.
Reverse the polarity of the input pulse.
11.
Record the effect using
12.
Reverse the neon bulb.
13.
Assemble
14.
fig.
sketched output waveform.
Record the
effect.
a second circuit similar to figure 18-5,
values of figure 18-3.

(See
18-5).
Take the output of the
first
Use positive input pulses to #1
and restore the
and feed
it
staircase.
Observe output one and output two. Record both waveforms.
152
original to the circuit
into the input of the second.
ELECTRONICS/DIGITAL
Fig.
ANALYSIS GUIDE.
In
EXPERIMENT 10010
18-5
important characteristics of the two-diode storage counter and
two waveforms
in step
comment on
operation. Discuss how
analyzing these data and waveforms, you should

its
14 compare to each other.
Mil
Mil
MM
MM MM MM MM
Fig.
18-6
\'
MM
MM MM
The Results
153
Mil
MM
III!
the
the
EXPERIMENT 10010
lilt
II
II
MM
MM
It
ttir
III!
Mil
MM MM
MM
il
till
Fig.
18-6
II
'
1^
MM
till
ELECTRONICS/DIGITAL
Mil
"mm Mil Mil
II
M MM MM
till
Mil Ml)
II
The Results (Cont'd)

154
MM
MM
il
EXPERIMENT 10010
ELECTRONICS/DIGITAL
MM MM
Mil
MM
llll
MM
II II
llll
MM
lilt
mi
Mil] JIM
llll
till
F/flr.
II
MM MM
till
MM
75-5 7/?e Results (Cont'd)
PROBLEMS
1.
certain staircase generator generates six steps.
storage counters which generate three,

pulses will be required
five,
It is
and four
feeding three other two-diode
steps, respectively.
How many
on the input of number one to get one pulse out at number
four?
2.
3.
C1 =
0.01/zF
C2 =
0.02/iF
AV C2 for step
A.
What
B.
Step six?
It is
is
one?
desired to have a storage counter that will trigger on every twelve input pulses.
Sketch the circuit you would
may
use.
Any type
be used.
755
of trigger device (discharge switch)
experiment
INTRODUCTION.
multivibrator,
11
BASIC COUNTERS
1 1 I I
Multivibrators are used extensively throughout logic circuitry.
either the saturating or nonsaturating configuration,
in
The
bistable
especially useful
is
experiment we are going to investigate the use of

stable multivibrator with binary coded numbers.
counting applications.
logical
DISCUSSION. The
two
cuit has
In this
where
bistable multivibrator cir-
This makes
es-
is
in the binary coded number

Both the saturated and the nonsatu-
is
stable states.
it
pecially useful
system.
The
rated versions are used.
saturated types
build.
They
in
have
less susceptibility
tion stated differently
the long run, are
power supplies
more reliable and
causes
the
to noise.
switch
action
to
be
where N
the
is still
transistor while
of 15.
is
operating in the satura-
The slow switching action of

flip-flops makes them particularly
industrial circuits which do not re-
region.
useful in
quire
it
high-speed
switch
action
2N -
(19.2)
Saturation,
a four-flip-flop
saturated
predic-
is
Maximum count =
slower, due to the collection of charges in the
tion
counted.
require fewer
and,
however,
number of bistables.
the decimal number to be
the
Another equation with the same
have the advantage of being easier to design
and
in
a bi-
and
first
Thus,
maximum
Figure 19-1 shows such a four-stage
The input
pulses are fed to
J-K flip-flop (FFq). The reset pulses
can be fed to
rapid
flip-flops.
counter can count a
binary counter.
the
number of
all
of the FFs at the same time,
or the J-K operation can automatically
calculations.
them. The circuit blocks

the
The no nsatu rated type has the advantage
powers of two
in
set
(flip-flops) represent
the binary
number
system.
of very high-speed switching at the cost of
more complicated
circuitry.
type most often used
They overcome the
in
These are the
digital
storage
FF 0 =
computers.
delay time
1
FF-j = 2
re-
quired by the saturated transistor.
FF 2 = 2 2
The
multiyibrators of any counter must
FF 3 = 2 3
have symmetrical triggering for advancing the

count, and nonsymmetrical triggering to allow
It is
The number of flipdetermined by the size
the circuit to be reset.

flops
in
the counter
is
of the numbers to be handled.
3
very easy to determine that 2 + 2 1 + 2
= 15.
This can be
When
calculated using
from 0 to
the
1,
first
bistable (FFq) switches
the second bistable (FF-j)
not switch because the pulse

(19.1)
to switch FF-|.
0,
156
then FF.|
When FFq
is
will
inappropriate
switches from
will receive a pulse
which
to
will
EXPERIMENT
ELECTRONICS/DIGITAL
ii
0
m
C
COUNT INO-
BASIC COUNTERS
FF
FFo
FF,
1001
m
R
Tf
IT
RESET O-
Fig. 19-1
switch
FFq
This pulse
FF
1.
Thus, two pulses into
tive
it
will
not switch
FF2
with
NPN
transistors)
input of the next bistable.
cause FF-| to switch and produce a
will
pulse.
like
from 0 to
it
Four-Stage Binary Counter (All FFs in J-K Mode)
coupled to the
By proper
arrange-
(similar flip-flops), this pulse will be of
ment
because,
is
the wrong polarity to switch the next flip-flop.
must receive the appropriate pulse
-J
which
polarity,
receives
its
will
be passed only when
enough pulses to change
When two
FFq
back to
FF-|
original state.
pulses are received at the input of
the bistable, the output will
first
then back to saturation.
As
go to cutoff,
the transistor
switches from cutoff back to saturation, a

pulse of the correct polarity to switch the
So we
see, in
of flip-flops can
sired
like
next FF will be coupled from the output col-
manner, any number
lector.
be linked to produce any de-
decimal-binary conversion.
It
made
that a bistable multivibrator can be
the
like
did on the original FF, and so on
true
is
This pulse acts just
first
pulse
down
the
chain.
to
respond to either positive or negative pulses.
We
What happens
multivibrator
is
in
electronically?
When
will
assume that the transistors
the
the zero state, the output
to
-V cC with
the
first
correct pulse polarity to the input will cause
-Vqq to near 0 when

A PNP bistable circuit
the output transistor to go into cutoff (and
positive pulses,
transistor
is
in saturation.
Application of the
the input transistor to saturate).

stant the
change
in
At
that
PNP
transistors
and
the
and
switch (0 to
1),
and
it
switches from
is
usually triggered with
this will
happen
to 0.
at the
when Vq^ changes from -Vqq to

This condition is shown in figure 19-2.
collector
in-
voltage at the output col-
lector (negative with
in
example are PNP. The magnitude and polarity

of the voltage at the collector is from near 0
near 0.
The counter
posi-
157
is
said to be full at the
15th
EXPERIMENT
pulse,
and
all
pulse.
The
pears
in figure
revealing
1001
BASIC COUNTERS
bistables are reset
by the 16th
number of pulses which have

been fed to the input of the counter. Notice
therefore, the
truth table for this counter ap-
This table
19-3.
the actual
ELECTRONICS/DIGITAL
useful in
is
FF
state of each
the binary
FF corresponds
also that the state of the
and,
10
11
number
12
13
for each decimal count.
14
15
16
UJJJJJJJJJJJXLL
^WLjWLTLrir:
ov
Fig.
19-2
10
11
12
13
14
15
16
FF 1
FF 2
FF 3
Fig.
19-3
Voltage Waveforms of a Four-Stage Binary Counter

(The FFs used above trigger on positive-going pulses)
Count
(or pulse)
FF
Truth Table for Four-Stage Binary Counter
158
to
EXPERIMENT
ELECTRONICS/DIGITAL
1001
BASIC COUNTERS
O-v,
OUTPUT
Two
Fig. 19-4
Stages of Diode-Steered Base-Triggered Binary
When
Probably the most important consideration for designing a counter after choosing the
FFs is the manner in which they are to be
bistable pair with diode steering
The diodes
and base
tive pulses,
and the
this,
both
state.
is
To
them
When
a reset pulse
is
Q2 and Q 4
are driven into cutoff.
duct at the saturation

directed to
Q2
by D 2 and
,
throwing Q1 into saturation.

a negative pulse to
go to FF-j
appear at the base of
Q3
or
This
Q3
will
diode (D 3 and D 4 )
quently, this bistable does not change
to near 0
This positive pulse
is
at the base of
When Q 4
cuts off,
its
base.
Q 4 will cause
Q 3 must go to
it
to
sat-
uration.
Again, a negative pulse occurs at the
output.
This will go to the next stage (not
third pulse (count 3) switches
state.
The
out through
pability
is
count.
its state.
755
it
will
remain at
all
first
the
is
bi-
carried
maximum
all
count beyond
The
1.
This
11.
stages until the
reached, and then
to 0 by the
Conse-
FFq to
resulting negative pulse will not
now becomes
nary count
not
Q 4 because of the
steering circuits.
pulse).
switch FF-j, and
cause
will
at the col-
already cutoff, nothing happens at
The
will con-
which
The output
shown) where the steering diodes will block it.

The pulse count is 2, and the binary reads 10.
A count pulse is
Q 2 will cut off,
level.
its
applied to
state; Q-j cuts off and
Q 2 now pulses from -Vqq
positive
cut off.
off.
applied, Q-| and
does change
But the pulse
the input transistors are supplied a
positive pulse to turn
it
is
coupled to the input of FF-j, and the diodes

direct it to the bases of Q3 and Q4. Since Q3
to posi-
reset line will switch
output transistors to the saturated
do
(a
trig-
are so placed that they
make the multivibrators respond only
goes to saturation.
lector of
Figure 19-4 shows the circuit for a
coupled.
gering.
FF Q
Q2
the next count pulse
ca-
are returned
its
maximum
EXPERIMENT
Fig.
A common
ling
BASIC COUNTERS
1001 1
19-5
Binary with
There
is
Common Load Resistor and Capacitor Coupling
load resistor and single coup-
capacitor can be used as
19-5.
ELECTRONICS/DIGITAL
still
shown
in figure
no problem with a negaFF, but a positive
first
The input count pulse is applied to the

FF and to the first AND gate. If the FF
in
the zero state, no output will go to the
is
tive pulse switching the
next stage because the required second pulse
pulse from the first stage to the second will
to the
tend to turn the
FF
ON
transistor of the second
AND
will shift
circuit will be missing.
from zero to one. When the second
AND gate will produce

an output one because both of the inputs to
off.
pulse
When
a high speed counter
is
desired,
it
is
applied, the
are 1s
(if
AND
the bistable circuits must be of the nonsatu-
for
rating type.
proceeds as
Collector triggering
is
often used
necessary, refer to the truth table
gates clarification).
in
creased speed
the load on the pulse source.
the counter operation.
Clamping
is
used to prevent saturation of the collector

circuit. Actual circuit operation is very simi-
can be speeded up by using

sense the bistable states.
is
Any
to that already discussed.
shown
in figure 19-6.
AND
to switch
in
is
counter
its
change.
AND
gate,
must be
in-
AND
The
is
normally only
will
the ordinary type.
160
output, can sense
one output and the
and the counter
gates direct the pulses to the proper flip-flop.
its
gate input to slow the shift indication.
delay
AND
on
In this case, a delay
serted between the
Such an arrangement
The
in
This also creates
a possibility for a bistable to switch states
before the
gates to
This type of circuit
sequence.
the only real difference
is
major problem with the gated counters. There
eliminates the time delay required for each

bistable
The counting
The in-
the previous circuits.
for faster switching response, and to minimize
lar
The FF
few microseconds,
still
operate faster than
EXPERIMENT
ELECTRONICS/DIGITAL
t
0
FF 0
R
t
0
FF
FF
C:
1001 1
R
i
F =3
(:
BASIC COUNTERS
<
RESET IN
COUNT
IN
F/g.
19-6
Gated Binary
FFs
(All
in
J-K Mode)
MATERIALS
4 Integrated
1
flip flops,
type
SN1584N
or equivalent
Data sheet for the IC FF
1
DC power supply (0 40V)
4 IC sockets appropriate for the ICs
-
Oscilloscope
Function generator
1
1
DPDT
switch
SPST momentarily-closed
switch
PROCEDURE
1.
Determine the correct number of FFs for
maximum count
of seven.
Show
all
of your
work.
2.
Draw
for a
maximum count
block diagram similar to figure 19-1 of a circuit using IC flip-flops

of seven.
Show your
in
the J-K
mode
block diagram with a coupling reset switch
(SPST) and supply voltages. Have the instructor check the drawing before proceeding.
3.
Checking figure 19-7 and being very careful to plug

circuit.
Remember, these
in
the IC correctly, construct your
ICs use positive logic.
0 0 0 0 0 0 0
O 0 0 0
Fig.
19-7
The IC Socket
161
EXPERIMENT
4.
1001 1
Connect
BASIC COUNTERS
ELECTRONICS/DIGITAL
V cc of 5V and a DPDT switch to short either the

one IC to ground. The output of this "triggering circuit" should
a "triggering circuit" using a
set or reset terminal of
be applied to the clock pulse terminal of FFq. The counting circuit and triggering
must have a common ground and Vqq = 5V.
5.
Check the data sheet
circuit
Vqq (magnitude and polarity). Be sure to monitor

with an accurate meter. It cannot vary more than 1.5V without
for the proper
this voltage constantly
destroying the IC.

6.
Check the terminals
7.
Apply
8.
Observe the outputs (Q) of FFq, FF-,, and FF

2 If they are not all in the 0 state, use the
SPST switch to momentarily ground pin 5 (C ) of all the FFs. Recheck the outputs to
D
see if they are now all in the 0 state.
9.
Now
Vqq
for accidental short circuits. These can easily destroy an IC.
to the whole system.

.
use the "triggering circuit" to apply pulses to the binary counter and complete the
data table.
10.
Observe what happens
if
the reset switch
is
closed while the counter
is
a state other
in
than 000.
1 1
Turn the power supply off and disconnect the
triggering circuit
from the binary counting
circuit.
12.
Now
connect the function generator (pulse output) with the amplitude off to the clock
pulse of FFq.
13.
Turn the power supply back on,
set to
Vqq
= 5V.
Now adjust the function
generator so
that a pulse train of about 7 positive, 4-1/2V pulses being applied to the clock pulse input
of
FFq can
be seen on the oscilloscope.
Set the oscilloscope triggering for negative
in-
ternal trigger slope.
14.
Now make
accurate sketches of the pulse train being applied to
FFq, FF.|, and FF

2
in
15.
Observe the outputs when the reset switch
16.
For your
own
is
multivibrator
the system to
In analyzing these results,
as a basic binary counter.
work
the output of
momentarily closed.
understanding, observe the outputs
cy and duration are applied to the counter.

as this may destroy the IC.
ANALYSIS GUIDE.
FFq and
the space provided on the data table.
when
pulse trains of different frequen-
Do not exceed
4-1/2 volt pulses
in
amplitude
you should describe the operation of the bistable

any problems you had in getting
Also discuss
properly.
162
ELECTRONICS/DIGITAL
Fig.
19-8
The Data Tables
163
EXPERIMENT
1001
BASIC COUNTERS
ELECTRONICS/DIGITAL
Pulse Train Data
Clock
Pulse
FF,
FF-
FF-
Time
= 0
Counting Data
Decimal
Equivalent
0
1
CP
FF 2
FF 1
FF
4
5
6
7
Figure 19-8 The Data Tables (Cont'd)
PROBLEMS
1
How many FFs would
be required for a 32-scale counter.
2.
Describe the condition of the FFs for the binary count of 6.
3.
What was the
4.
What type
effect of the reset switch
on the outputs of the binary counter?
of pulse triggers the FFs used (negative going or positive going)? Explain.
164
experiment
INTRODUCTION. Counting
applications. Many different
a
computing system.
the several
ways
DISCUSSION.
the first
is
is
which
in
of
bers to
will
examine
other logic
in
This circuit
a ring counter.
output of
the next binary.
state;
last
last
is
one of
used
as
At each count the one
and places
back to one.
it
in
it
FF
the one
is
when
indicated
we
the
discuss the actual ring counter
to be used in this experiment,
a binary counter.
state.
first bistable
returns to one.
Before
reaches the
count through the entire
of the register
scale
The
binary
numdecoding
makes
a "ring"
decimal easy. When the ring counter is
from
bistable
first
be
supply the one to
The next count pulse sets the
other
all
will
moves around the circuit until
only one bistable at a
can
count pulse
state.
coupled back to the input of the
arrangement
a series of
The output of the
etc.
decimal readout
use
is
the
"1"
time is allowed in the
"0" state.
bistables are in the
This
computers and
in
which electronic counting can be carried out.
In a ring counter,
first.
experiment we
coupled to the second, the second
the third,
binary
important operation
a very
types of circuits can be used to perform a given calculation within
ring counter
counters
binary
to
in
In this
is
RING COUNTER
10100
let
us examine
the integrated circuit that will be used to
make
this counter.
used for readout, there must be one bistable
multivibrator for each decimal

read.
Each of the bistable inputs
When the counter

ing
is
to decimal zero
state; all
KEY-
number
reset,
is
the
As you
to be
two J-K flip-flops which operate independently

Each has two accessible outof each other.
omitted.
is
FF correspond-
turned on to the
16
puts,
the others are switched to the zero

1K
see in figure 20-1, the IC contains
and Q, which are always
states.
1Q
1Q
GND
2K
2Q
2Q
15
14
13
12
11
10
CLEAR
PRESET
PRESET
CLEAR
K
CLOCK K
Fig.
20-
1J
in
V CC
The Integrated Circuit

165
CLOCK
2J
opposite
EXPERIMENT
10100
RING COUNTER
Truth Table (Each
ELECTRONICS/DIGITAL
flip-flop)
*n
Qn
t
t
clear
= Bit time before clock pulse
the
logic
20-
The Integrated Circuit (Cont'd)
The
and preset terminals operate
independently of
= Bit time after clock pulse positive
Fig.
The
clock,
and
may be
operation
The
follows:
applied either mechanically or electronically.
This
system.
is
of
counter
the
move
first
is
to
is
as
reset the
done by momentarily
closing
the reset switch which applies a low input to
The
The
20-1.
the preset terminal of FFq, putting
transitions of the J-K flip-flops cor-
respond to the truth table shown
in figure
and K terminals and are
kept constant while a negative going pulse

applied to the clock
terminal.
FF5
is
of
the
ring
flops, so
of 5
if
to
be
used
in
first flip-flop is
count pulse
first
devices
it
will
is
the
The
applied.
0 before the pulse so these FFs
in
the same state, which
first pulse,
Kg of FFq
this
will
used to represent 0
make the transition from
Jo
1
is 1,
is
the
due
to
FFq
0, so
to 0 and remain
Before this pulse, the J1 terminal of
FF1
is
due to
from the 0
its
coupling to
state to the
The next count

FF2 to
count
sixth
initial
is
is
Qq
the
state.
pulse shifts
1.
In this
which returns the
(preset) condition.
back
FF-j
manner, the
passed around the ring
pulse,
of FFq,
0 due to
Therefore, FF-j will switch
to 0 and sets
to favor the proper binary so that
At
there.
and the K1 terminal of F F-j
The coupling between binary
will remain
logical 0.
is
flip-
The important thing to note is that the

count is applied to all of the FF devices at the
same time. This count pulse has the same
effect as a reset input to any device that is in
state.
is
all
feedback loop.
Now
the 0 state.
the feedback loop from Qq.
or the reset state.
the
in
ready to count.
time of this
has a decimal readout capability
it
the
counter
This counter contains six
them
and K inputs of FF2, FF3, FF4 and FFsare
20-2 shows the block diagram
experiment.
is
The
often
characteristic of mechanical switches.
Figure
putting
system
is
This pulse
must be free of the bounce that
is
applied to the clear terminal of FF-| through
desired input levels (not pulses)
are applied to the J
in the
it
At the same time the low input
state.
until
ring
The system
to
the
its
can be
returned to the reset state at any time by use
respond, and the count will be passed
of the reset switch.
to the next binary as desired.
166
RING COUNTER
EXPERIMENT 10100
ELECTRONICS/DIGITAL
PR.
ST.
FF
CLR.
PR.
ST.
FF 5
PR.
ST.
FF
CLR.
COUNT
INPUT
PR.
ST.
FF 3
Q CLR. K
RESET
Each
of
are
like
has a transition time
flip-flop
about 50
flip-flop
ns.
The Ring Counter
20-2
Fig.
This
is
the time
it
Tt
to respond to a clock pulse.
If
in
there
step.
stages (or binary devices) in a counter
the one
imum time
shown
one complete ring
is
output of any stage
minimum
each pulse
in figure
20-2, the min-
possible for the counter to
period
is
N X Tt
is
NTt
the time
may be thought of as a stepping switch

which each count advances the switch one
system
takes the
make
The outputs can be fed to succeeding

at
fan-out
limitation
of
the
Therefore, the
is
regard
ICs
to the
being used.
given in the data
sheets for the devices.)
a pulse train with a
and the duration of
Any type
T^
Ring counters are used

sequential
point with
(This fan-out limitation
counter.
where
each
circuits
gating
is
in
applications
required.
transistor
The
binary device
may be
used as a
Typical of these binary devices are

flip-flops,
unijunction transistors,
tunnel-diodes, and silicon-controlled rectifiers.
167
EXPERIMENT
RING COUNTER
10100
ELECTRONICS/DIGITAL
-o v cc
4e
V,
INPUT
O-
20-3
Fig.
Ring Counter
SCR
ring counter in
switches on, an abrupt drop
In this circuit, the
counting pulse
at
For instance, consider the

figure 20-3.
SCR
voltage occurs
This voltage change
anode.
its
in
will
be
coupled
transmitted through
C2
to the anode of S^,
through a capacitor to the anode of the next
which drops below
its
maintenance
is
Each of the anodes
positive.
SCR.
S-]
is
is
and
triggered to start the ring,
and turns
all
same
of the other devices are off. All of the diodes

are reverse biased
by
Vqc
except D2, which
The
is
only slightly smaller than
S2
will
D2
to the gate of
switch on (logical one).
binary device starts out
and resets the
in
the on
is
fluid switching devices
When S2
in
or gates
proper condition
This same principle applies
for change.
S2 and
The diodes
first.
select the device that
in
This pulse will be
amplitude and positive.

transmitted through
Vqq
was described for
is
condition, a count pulse turns on the next one
only slightly reversed biased because Si is

on. This diode D2 will accept a trigger pulse
is
which
as
first
voltage
much the
the J-K FF counter.
Thus, the action
off.
and works well
to
with
fluidic flip-flops.
MATERIALS
1
DC power
supply (0-40V)
3 Integrated dual J-K flip-flops, type
SN7476N
or equivalent
1
Integrated dual J-K flip-flop, type
SN15845N
or equivalent
In-line IC sockets
SN15845N
(SN7476Ns have 16
Set of data sheets for each IC type
Oscilloscope
Function generator
SPST
DPDT
switch
(center-off) switch
pins;
has 14 pins)
PROCEDURE
Examine your
ICs.
reset terminal of the
DPDT switch from the

Vqc should be 5 volts.
Construct a "triggering circuit" using a
SN15845N
(or equivalent) to ground.
168
set or
EXPERIMENT 10100
ELECTRONICS/DIGITAL
2.
RING COUNTER
Connect the output of your "triggering circuit" to the clock terminal of one of the other
ICs.
Use Vqc = 5V Experimentally determine the truth table for the ICFF. Record
-
3.
your
results in the data table.
Now
construct the 5 scale ring counter
to apply count pulses. Measure

4.
Record the
0s,
states of
all
not actual voltage
Vqc
shown
in figure
to be very sure
the FFs (values of Q)
when
Use the "triggering circuit"
20-2.
it is
not over 5
the reset switch
volts.
is
tripped.
Use 1s and
levels.
the FFs after
and 6 count pulses are applied.
5.
Record the states of
6.
Record the response of the counter
7.
Disconnect the supply voltage and the "triggering circuit" from the counter.
8.
Connect the function generator (pulse output) to the counter so that +4.5 volt pulses
will
all
be applied to the count
1, 2, 3, 4, 5,
if
the reset switch
is
tripped after a count less than 5.
circuit.
9.
Adjust the generator so that approximately 20 pulses
may
10.
Sketch the input waveform and the waveform of at
least
form of
11.
of
is
2 FFs.
Also sketch the wave-
FF.
Observe the waveform of the counter

train
be viewed on the scope.
if
the reset switch
is
held closed while a pulse
being applied.
ANALYSIS GUIDE.
counter and the use of the IC modules for
its
you should discuss the
construction.
Train Data" should also be included.
Truth Table
tp
Fig.
20-4 The Data Tables
169
characteristics of the ring
complete discussion of the "Pulse
EXPERIMENT 10100
RING COUNTER
ELECTRONICS/DIGITAL
Ring Counter States

Input
Reset
FF 0
FF1
FF 2
FF 3
FF 4
FF 5
Effect of reset
when count
MM!
< 5 was
MM
nil
Nil
mm'
MM MM HM
Mil
Mil' llll
lilt
Fig.
MM MM MM
M MM nil
20-4 The Data Tables (Cont'd)
170
HI
Mil
II
RING COUNTER
EXPERIMENT 10100
ELECTRONICS/DIGITAL
MM
H-H
Mil
Fig.
MM'
II
lilt'
1111
mm'
MM
II
Mil' H-H
Mil
MM
PROBLEMS
the scale of count for the circuit
1.
What
2.
From the
3.
What
is
4.
What
is
used
is
in
data sheet, what
is
the
in figure
maximum
20-2?
fan out capability of the ICs you used?
the power dissipation of your ICs?

the
maximum
frequency of a pulse train that can be applied to the counter
the experiment?
171
experiment
INTRODUCTION. The
ing of binary
numbers.
number
shift the binary
It fill
10101
HIF T R E
GIS TER S
arithmetic operations of a computer depends on the storage and

processOne of the circuits is a register. A particular kind of register which
can
to either the right or left of the binary point is called a shift register.
|
this
experiment
we
will
DISCUSSION. Data
examine the operation of
storage in a shift register
Let's look at the
is
usually very temporary, sometimes for only
in
few microseconds.
output
Because of this short
storage time, bistable devices are used exten-
Therefore,
sively.
made up
most
shift
are
registers
of binary devices coupled together.
figure 21-1.
lines are
The
sistor.
choosing the
The
condition.
series,
in
with the output of the
first
is
chosen
side to
put
is
andO
input
tran-
After
the
is
go to the one
reset input then, will switch
the side to the one state.
con-
arbitrarily.
side, the set (S)
a flip-flop
the
each the collector of a
side
symbol for
In the usual case,
input that causes the
Flip-flop circuits are normally connected
a simple shift register.
The T or
trigger
in-
the complementing input.
nected to the input of the next and so on.
Clock pulses (the pulses to be counted) are

fed to the input binary and stored.
The
pulse to be stored sets the first flip-flop.
second pulse resets the

the transfer of the
next FF
circuit.
first
first
FF and
first
The
causes
stored pulse to the
Thus, as each pulse appears
down
at the input, a shift of pulses occurs

string of flip-flops.
The new pulses

So you
are pieces
of information (called bits).
see,
time a pulse appears, information
is
from one binary to the next and
every
first.
Many bits can be
way (depending on the number
of flip-flops)
until
on command or
for
after
is
will
If
called
the binary
will
shift register arises
shift the
left
is,
number
in effect,
to the right
in effect, division
in
is
is
The
simply the
state of the
the S state, output
FF
at T.
1
applied at T; then the binary
To
comple-
invert the state, a zero potential can
transistor,
or to the base of the con-
ducting transistor
and compatible).
Shifting to the left
multiplication by two.
is,
ting
used to
either to the right or to the
of the binary point.
in effect,
be applied to the collector of the nonconduc-
because the
is
is,
switch to the opposite state.
ment or
particular circuit of interest here
Symbol
be changed by proper input pulses
and a pulse
some predetermined
length of time.
The term
Flip-Flop
inverting of the flip-flop.
entered into the
the information
21- 1
Complementing
"bit"
stored in this
is
Fig.
shifted
new
the
and
Shifting
(all
In
else
remaining constant
most cases of counting
shifting, a special input trigger
network
or gate would be used.
by two. The
0 and 1 outputs of one state are taken to the

R and S inputs of the next stage. The bits are
Let's
transmitted unchanged from stage to stage.
registers
172
interrupt our discussion of shift
to discuss one basic circuit which
EXPERIMENT
ELECTRONICS/DIGITAL
SHIFT REGISTERS
10101
CLOCK
PULSE
INPUT
OUTPUT
2" OUTPUT
21-2
Fig.
Four-Stage Binary Counter Using J-K
often serves as an input trigger network.
shows
ure 21-2
you
FFs
is
such that the
the trigger input of each
FF 0 (2)
cuits will
state
input voltage pulse
applications) the
is
logical 1,
0 volts =
is
trigger
counter.
There are 2
NPN
cir-
counter.
It is
on
is
0001
0010
referred
up
to as an
counts with an n stage
interesting to note here that the
be thought of as
by
where n = the number of the output
stage being the input frequency divided
2 n+1
stage.
logical 0.
NPN
logic,
go from 0 to
1,
of the wrong
polarity.
Frequency =
with the
the FF-j stage (2
(21.1)
>n+1
1
)
These types of counters are referred to
The second
the FFq (2)
as binary accumulators or adders.
If
n pulses
are fed to the input, the register goes to bi-
complements (switches)
stage from 1 to 0. This time the switching is
stage
in the proper direction to cause the FF
pulse
input frequency
because the
not complement (switch)
slope
state
frequency divider, with the frequency of each
positive
input trigger causing an output at the 2
will
FF
is,
corresponds to
circuit of figure 21-2 can
defined as + volts =
Getting back to the
stage to
is
the
rarely used in practical
FF would
Positive logic
That
the up or increasing direction.
in
This type counter
sloping negatively. For
is
1),
(binary 2)
With
pulse
pulse,
complemented.
is
(binary
output feeds
successive unit.
Mode
one corresponds to
pulse
be so complemented only when the
positive logic (which
pulses.
input clock
negative-going
each
first
As
can see in this circuit, the interconnection
of these
OUTPUT
increases as the count progresses.
Fig-
a simple binary counter.
OUTPUT
IT
nary
n.
Then
if
n'
additional
numbers
are fed
to the input, the register goes to the n
n'
-j
However, the polarity
complement.
wrong to complement the FF2
to
Figure 21-3
carried out
count
is
shows how
one pulse
stage,
binary number.
is
will store as
etc.
these operations are
at a time.
The binary
Two more
pulses
count to go to binary
Up
in this
addition.
173
binary 3 (11).
at the input cause the
5 (101).
equal to the input pulse number, and
In specific terms, three pulses
counters are used
way
for
EXPERIMENT
10101
SHIFT REGISTERS
FF
ELECTRONICS/DIGITAL
FF 2
FF 1
FF 0
Output
Output
Input
Output
Output
Pulse No.
23
22
10
12
13
14
16/0
Fig.
21-3
In order to divide, the reverse
Four-Stage
counting
a circuit for counting
down.
the difference
is
the trigger input.
now
is
erations for four stages.
fre-
quency dividing characteristics remain the

same (because the outputs are taken from the
point).
It is
is
valid.
In this case
down
Fig-
op-
the pulse
count corresponds to the complement of the

decimal output.
easily seen that the only
difference between up count and
the side of the
seldom used but the principle
ure 21-5 shows the table of count
feeds
Also note that the
side
traction. Actually this simplified arrangement
Notice that
that the zero side
be used for addition and the zero side for sub-
Each successive
stage operates at a slower rate.
Up Count
Arithmetic operations require that the
operation must take place. Figure 21-4 shows
is
11
15
same
FF used
down count
to trigger the input.
of
174
method more frequently used
consists
combination of these two simplified
EXPERIMENT
ELECTRONICS/DIGITAL
10101
SHIFT REGISTERS
CLOCK
INPUT
6
Fig.
Four Stage
21-4
OUTPUT
Down Count
FF 3
FF 2
OUTPUT
Register (All
6
FFs
OUTPUT
in
OUTPUT
J-K Mode)
Decimal
FF 1
2
OutDUt
Output
Output
Output
Output
Count
16 or U
lb
1 A
14
\6
4
5
Input
Pi cp imu.
Nn
rUloc
i I
o
2.
10
11
12
13
14
15
16/0
Fig.
21-5
175
0/16
EXPERIMENT
SHIFT REGISTERS
10101
ELECTRONICS/DIGITAL
INPUT
R
0
0
FF,
FF,
FF.
OUTPUT
OUTPUT
INPUT
SHIFT
(CLOCK) O"
INPUT
Fig.
21-6
Four-Stage Shift- Right Register
methods with suitable coupling to allow shifting from one mode to the other.
By using
steering gates, the input
FF can be
controlled
by the condition of the remaining

and the
shifting
ing to
binaries,
is
a circuit
Variations can be
flip-flops.
one
one
bit at a
shift per pulse).
pulses over one bit.
ing to the left can
fc>e
As
it is
time (correspond-
Each
shift
moves
Figure 21-6 will move
the pulses one bit at a time to the right.
made
the gating to shift bits to the stage on
on its left.
Figure 21-6 shows the circuit for
all
S and T
fed into one side of the register,
is
shifted serially,
which can allow

of stored information (bits) from one
result
stage to the other.

in
right register using R,
data
Shift-
accomplished by using
a circuit similar to figure 21-7. This circuit
its
right, or to the stage
the
complement of the
the inputs and outputs are exchanged.
a shift-
INPUT
OUTPUT
f
OUTPUT
1
INPUT
SHIFT
PULSE
O
Fig.
21-7
Four-Stage Shift-Left Register
176
is
figure 21-6 circuit and
EXPERIMENT
ELECTRONICS/DIGITAL
SHIFT REGISTERS
10101
SHIFT PULSE INPUT
Fig.
21-8
Broadside Shift Register
Actual computing circuits require somewhat more gating than

ure
21-6 or 21-7.
is
shown
in either fig-
which
all
is
You
a right shift circuit
would be used for division.
One other type
and
used ex-
Delay
The
delay lines to avoid the "race" problem.
lines are
through the
circuit,
count to ripple
changing one FF at a
Figure 21-9 shows a ripple shift to the
time.
S and R inputs.
is
tensively and gets around the need for the
ripple shift register allows the
shown between the output of the gates and

the
shift register
bits are shifted
from one to the next simultaneously.

notice that this
a multiplication broad-
side shift.
Figure 21-8 shows a broad-
side shift register in
will
ment would provide
These are necessary for

left.
practical
delay lines
one binary
make
is
mation
is
well as
0 and
but they
certain that the content of
transferred before
stored.
1
The
to insure reliability.
circuits
As always,
set
new
and
infor-
reset as
inputs are defined arbitrarily
must remain
first
shift
pulse
gates.
One
is
applied only to the
of these gates will oper-
ate with FF-j in a particular state. Whichever
gate operates
the
consistent.
The
two
first
OR
it
will set or reset
FF2. Through
gate and the second pair of
AND
gates (3 and 4), the selection of state of

In
plied,
when
operation,
only those
AND
a shift pulse
gates with
from the FFs will respond.
is
ap-
inputs
These gates
cuit
and
shift the
count. This
provides a division shift and
its
made and FF4
Again
we
is
have explained the circuit
beginner to understand.
it
comple-
is
The
normally use negative logic
cir-
in
terms
easier for the
actual circuits
NAND
gates with negatively pulsed FFs.
177
FF3
set or reset accordingly.
of positive logic because
will
then apply pulses to the set or reset inputs of

the next binary
is
and
NOR
EXPERIMENT
SHIFT REGISTERS
10101
ELECTRONICS/DIGITAL
SHIFT PULSE
Fig.
As we have
of register
is
term implies
the
a
Ripple Shift to the Left
common
type
or shift register.
The
said the
serial
21-9
most
number of FFs
in
series,
present day operational computer on a
the
all
the FFs.
When
to the first
FF where
it is
stored.
circuit
one
Several bits
may be
scale integrated
modules (MSI).
8-bit shift register.
gram
stored
is
shown
is
Its logic
in figure
consumer-type
and package
21-10.
This unit
typical standard integrated circuit shift
They can be stored for any

time and retrieved on command.
bit per stage.
length of
for economical and
medium
One such module
is
The
next clock pulse causes the bit to transfer to

the next FF, etc.
single
the
clock pulse appears, a bit at the set input
moved
common
practical reasons are
output of one feeding the input of the next.

Clock pulses are fed to
Also very
chip.
ter.
diais
regis-
Set reset (SR) flip-flops are used with an
input gate and an inverter for complementary

pulses at the S and
R inputs of FF Q
clock pulses are inverted also.
The
Figure 21-11
The foregoing discussion has been general

but would lead the reader to think of discrete
shows the input output clock relationship.

Notice that the output pulse appears eight
logic or logic blocks.
clock pulses
In reality, the present
generation of computer uses integrated circuit

logic
almost exclusively.
Whole
often contained on a single chip.

in fact, is
toward
clock pulses
registers are
The
later,
in
and
is
the width of two
that the binary does not
until the start of the next clock pulse.
trend,
The clock
which includes many of the functions of the
gate.
pulses are required to be at
least
25 ns wide and can be as
775
Nega-
NOR
tive pulses are required to trip the
large scale integration (LSI),
shift
fast as
18 MHz.
EXPERIMENT
ELECTRONICS/DIGITAL
10101
GND
12
13
14
SHIFT REGISTERS
CP
10
11
*5
R
CP
CP
CP
KEY
CP
S I
CP
CP
r-i
CP
CP
'cc
Fig.
Logic and Package Diagram of an 8-Bit Shift Register
21-10
CLOCK PULSES
nnnjimruuinJuT
2ND
[1ST
1
AB INPUT
Ji
h
1ST
Q OUTPUT
Fig.
21-11
Input and Output Waveforms for 8-Bit Shift Register
179
2ND
_TL
!
EXPERIMENT
SHIFT REGISTERS
10101
ELECTRONICS/DIGITAL
The unit uses transistor-transistor-logic

(TTL), which is similar to diode-transistor
logic but the diodes are replaced by multiemitter
transistors.
cludes 4
This unit actually
of
35
gates.
The
110 mils and the
silicon chip itself
total
power
is
55 %
dissipation
i
about 175
mW. The
unit will drive 10 other
gates.
in-
gates for each binary giving a total
MATERIALS
1
Oscilloscope
DC power
8-bit shift register,
supply (0
40V)
type
SN7491AN
or equivalent
5 J-K/RS
flip-flop,
SN15845N
type
or equivalent
6 IC sockets
1
Data sheet or equivalent for
DPDT
VOMorFEM
Function generator
each type of IC
center-off switch
PROCEDURE
1.
Examine the data sheet
Note Vqq, rep
for the ICs involved.
rates, pulse width, and
fan out.
2.
Arrange the JK/RS flip-flops
Include a "triggering circuit"
in a four-bit shift register.
constructed by shorting either the set or reset terminal of one FF to ground through
the
3.
DPDT
switch. Use
V cC
= 5V.
Before applying power, place an accurate meter across the power supply and make
that
Vqq does not vary more than
4.
Have the
5.
Apply power to the
6i
Note the operation of the
lab instructor
shift a given input
sure
0.5 volt.
check your
circuit.
circuit.
register, especially
completely through the
how many
register.
clock pulses were necessary
Draw
a sketch of the
output
to
trains
for given input and clock pulse trains.

7.
Study the data sheet of the
8-bit shift register.
Then repeat
steps 3 through 6.
It is
still
necessary to use the "triggering circuit" to supply the clock pulses.
ANALYSIS GUIDE. The
analysis of these data should contain observations
on the
characteris-
tics
of the shift register and IC application of the logic theory. Discuss each of the circuits
Was
their operation identical?
Which was
easier to
180
work with? Why?
used.
EXPERIMENT
eL ectronics/digital
MM
HM
Mil
II
MM
till
Mil] 'mi
in
lilt
Mil
MM
Mil' "mm
MM MM MM MM
Fig.
Mil'
21-12
MM
II II
MM MM
10101
MM
SHIFT REGISTERS
Mil
MM
MM
MM MM MM' MM MM
The Results
181
EXPERIMENT
10101
SHIFT REGISTERS
nil H-H
llll
llll
llll
1
1
III
ELECTRONICS/DIGITAL
r 'llll
1
1
MM
llll
Mil' llll
nil H-H
llll
II
MM
llll
llll
mm' Mil
Fig.
21-12
llll
\\
'mm
llll
llll
MM
llll
llll
llll
llll
Mil
II
MM MM'

182
MM MM
Mil
EXPERIMENT
ELECTRONICS/DIGITAL
10101
SHIFT REGISTERS
PROBLEMS
1.
A PNP
flip-flop triggers
a positive-going voltage change.
What
triggers a
fed to the input of an up counter.
What
is
on
NPN
flip-flop?
2.
frequency of 256 kHz
of the 2
output stage?
is
Show
a block diagram
183
and explain
fully.
the frequency
DIODE MA TRIX
experiment
INTRODUCTION.
the form of
Digital logic
level shifts
matrix
is
into
some
kind
Interpretation of these levels or trains requires
One such network
a diode matrix.
to encode or decode the digital information.
is
In this
The
basic purpose of a diode
experiment we
will
examine how
computers can be done with
relatively large.
been used
The
would be necessary; a minimum of

384 diodes would be required with this
inputs each
in dig-
logic gates
even though the number of gates required
in small step
method has usually

decoding and encoding
As an example of
At
DECIMAL OUTPUT
BINARY OUTPUT
Consider a 64-step,
000
diode
true.
011
Figure 22-1 shows a
matrix for decoding three
100
false
110
101
variables.
(2")
111
<
INPUT
\y
0.
jy
>
>
yy
1
23^
+v ccFig.
22-
>
y .y
.y ,y
this
the statement above does not
Both are true (2) and
010
001
first,
seem to be entirely
Sixty four gates with six
six-stage counter.
diode matrix can reduce
number considerably.
problem, a two-stage counter for four
steps requires four gates.
method.
is
gate
within digital computers.

the
is
done.
DISCUSSION. Encoding and decoding

ital
CIR C UITS
systems require that numbers and instructions be translated
or pulse trains.
of translational network.
this
10110
Diode Matrix For Decoding Three Variables

184
inputs
EXPERIMENT
ELECTRONICS/DIGITAL
Half of these will be
are available.
other half will be
at
and the
any given time, but for
is
|l
D 2< D 3' D 13' D 14> D 15' D 16' D 17- and
lines
are high or logical
1.
The low
These
(logical 0)
present at the other inputs clamp
(decimal
The most
output.
scheme
line
5)
is
that
it
all
will
serious
produce a high
problem with
Looking
volts
of Diodes Required
22-2
back at the
in figure
22-1,
we
standard
diode
can see that the four
diodes connected to the 2 2 and the 2-2 lines
(22.1)
Fig.
been developed to decrease
this
requires
X N = Number
trick has
figure 22-2.
matrix
2N
384
the number of diodes by making some of

them perform double duty. This method is
called treeing, and it decreases the number of
diodes required dramatically. The schematic
representation of a diode tree is shown in
these lines to zero and, therefore, only the
101
requires
separate gates.
positive voltages with
inputs for a decimal 5 or binary 101.
signals
still
For example, diodes
1).
line
Dig are back biased by
six-stage matrix counter
diodes which represents no improvement over
each input combination, a different output
high (logical
DIODE MA TRIX CIRCUITS
101 10
Diode Tree Connections
185
EXPERIMENT
101 10
QQQQQQQQ
r
X
OUTPUT
DECIMAL
BINARY
INPUT 2^
INPUT
Y-
INPUT
ELECTRONICS/DIGITAL
000
001
010
011
100
101
110
111
*
>
INPUT 2 1
2'
INPUT
<
2'
INPUT
VOLTS
Fig.
22-3
Actual Connection of Diode Tree Matrix
could be replaced by one diode since any one

of
them would
zero.
Similarly, the pairs

-1 lines
and 2
could be reduced to one. So
straight matrix.
connections
for
The diode matrix

position switch.
Number
of Diodes
actuated.
(22.2)
Using diode treeing, a six-stage matrix would
line
is
number 011, diodes at

the line. They could also
activate the
diode matrix or a diode gate system.
idea of matrix coding
is
method.
one
large disadvantage of the
Let's
As the number of counts
line
with the diode at 01
This process expanded
is
the
and decoding.
suppose that the codes are stored
The
in a four-bit shift register.
shift register
FFs would feed the 2, 2

2 3 and 2T,
2~
2~ 2 2~3 inputs. These inputs are referred
to as octal numbers. The FF has a total of
the current carried by the diode
increases.
010
(figure 22-2).
the example given,

-2
2
notice that the 2 and 2
line diodes handle
clamps
network
Referring to figures 22-2 and 22-3,
0 and 01 activate
+ 2 2 + 2 3 + 24 + 2 5 + 2 6 or 126
diodes as compared to 384 for either a straight
increases,
translation
For each code, one
require 2 1
There
tree
matrix.
notice that for binary
tree
diode
can be thought of as a code-operated multi-
requires
2N =
practical
in a
we
number of diodes required by

of N for N states. The treeing method
current as each diode
can reduce the

a factor
much
four times as
clamp the line to

of diodes on the 2
suffice to
In
186
22
EXPERIMENT
ELECTRONICS/DIGITAL
16
output
mal
lines,
representing binary and deci-
numbers up to 16 rows and 8 columns
(which
called a rectangular diode matrix).
is
101 10
input
AND/OR
each
decimal
gate (one
number
AND/OR
encoded or
be
to
gate for
decoded).
The binary circuits feeding the octal inputs

have
both
pFs
are
in
lines
This
and
When
outputs.
proper
sequence,
the binary
the
correct
are fed to give the binary code to match.
system works well
in
both directions.
Depending on the disposition of inputs and

outputs,
the
matrix will
either encode or
bit
By now you should begin
to realize that
the logic equivalent of a matrix
is
a multi-
must be
numbers ending
for
all
right
in
most
bit, as
By
The binary output
for the
kn
7,
9,
seen in figure 22-4,
OR
gate.
can be broken out
is
the
The other
in
the same
closing the switch at 9, the out-
put will produce
kf2
for the decimal

a zero
its
binary equivalent 1001.
VDC
1
3, 5,
output of a five-input
manner.
the
and
1,
the others.
bit positions
decode.
most
right
converter,
decimal-to-binary
In
kn
-0
-O
-O
2-
kn
-OGND
Fig.
22-4
Diode Matrix, Decimal-to- Binary Converter

187
EXPERIMENT
101 10
ELECTRONICS/DIGITAL
IIH
\i~<r
a9
i~<r
b?
i~~<^
t~<|"
by
cs>
i~<r
c9
5V
r~<i~
d9
dO
h
CL
h
D
F/ff.
22-5
Binary-to-Decimal Converter
188
EXPERIMENT
ELECTRONICS/DIGITAL
Just as
OR
gates are used for converting
in
from decimal to binary, AND gates are used to

convert from binary to decimals. Figure 22-5
101 10
this case, A, B, C, D,
ground potential by
shows a binary-to-decimal converter.
bit position
is
All
nonenergized
in
matrix circuits. Actually, any
construction of a
lines.
or input binary FFs.
diode or transistor gate.
on-off switching device can be used
represented by
The one line or the zero line is

when
the bit value is to be expressed.
energized
The binary number five would call for A, B,
C, D lines to be energized by the shift register
two
would be clamped to
Diodes are not the only semiconductor

devices used
Each binary
matrix.
in
the
check value
could substitute as a diode or a gate value

for a gate. The input to the matrix could be
number of electromechanical or
any
fluid
flow devices.
lines,
MATERIALS
1 1
Diodes, type
SPDT
Oscilloscope
VOM
DC
Breadboard
N34 or
equivalent
normally-closed switches
or
FEM
power supply (0-40V)
k2 resistors,
2W
PROCEDURE
1.
Construct the experimental circuit shown
2.
Measure the voltage of the power supply and energize the
3.
Measure the output voltage across each of the

at a time.
Record your
4.
With an oscilloscope or
5.
Using a
VOM
0 through
6.
in figure
circuit.
kft resistors for the 9 switches, closed one
results in the data table
VOM
22-4.
and calculate the current for each value.
determine the voltage
level for
outputs of
and
0.
or oscilloscope, determine the binary equivalent of the decimal
numbers
9.
Sketch the expanded diode matrix for
a decimal-to-binary converter of the
type shown
in
figure 22-4 for the decimal numbers up to 16.
ANALYSIS GUIDE.
constructed seemed to be the easiest to
work
you should discuss which of the matrices you

Why do you think so? Where in a practical
with.
system would you use a matrix?
189
EXPERIMENT
Switch
That
101 10
ELECTRONICS/DIGITAL
23
is
Closed
Voltage Level for
Voltage Level for 0 =
Fig.
22-6
The Data Table
190
EXPERIMENT
ELECTRONICS/DIGITAL
101 10
PROBLEMS
1.
to reduce the
diode matrix provides 8 outputs. The treeing method is to be used
number of diodes in the matrix. The current flowing in each output line is 150 mA.
What is the current through the diode which is clamping the maximum number of
lines?
2.
Given
a twelve-stage counter,
matrix?
What
is
the
number
what
using
number of diodes using a straight diode

the treeing method? Would the treeing method
is
the
be better?
3.
What would normally be used
in place
of a diode matrix?
191
INTRODUCTION. Many digital devices employ

In this experiment we will examine a simple
techniques used
DISCUSSION.
in
It
error detecting circuits of

single-error
design.
its
often necessary to trans-
is
Notice that for the five variables A, B,

C
P, there is always an even number of
1s.
information from one place to another.
fer
Whether
this
inside
computer or spans
several miles,
transfer
these errors and
designer can
used
entirely
distance of
Now we
not even the best circuit
the other four variables determine the value

of P, it will be to our advantage to determine
eliminate the
among
failure
place
are faced with the problem of

generating the parity bit P. Since the values of
There are a
occur.
takes
D and
uncommon for errors to

great many reasons for
not
it is
of a
possibility
the thousands of components
circuits have
Boolean expression of P
column
experiment
this
we
examine
will
design techniques that are often used
development of a
circuit
occuring
in
which
the
in
will detect sin-
four bits of information.
order to detect these single errors
four bit words,

bit
which
check
way
occur
in
error
that an even
each
generated.
occur
this parity bit
If
such a
word,
is
generated
number of one
then
even
decimal number one,
and_D =
ABCD
is
word we
will
is
A=B=C = 0
Therefore, the product term
1.
listed
"Sum
the
in
Since the
literals
bits
know
Now
C D
it
is
of Products"
C were
A, B and
possible to write a
expression which defines
A, B,
an
C and D
terms
the
in
all
for which P =
by simply adding
suppose that we need the ability to
transfer the B
in
This
I.
Boolean form)
(in
"Sum
Boolean
combinations of
of Products"
is
all
done
the
column.
ABCD + ABCD + ABCD

ABCD + ABCD + ABCD + ABCD.
From
this expression a circuit could be
this case,
ABCD
P =
equivalent of the decimal
numbers zero through
fifteen.
To do
this
we
need four inputs to represent the word
and one input for the

Figure 23-1
P=1,
the product term.
In
will
this
in
present.
Let's
In
equal to 0, their not values were included
bits
parity
an odd number of one
If
in a particular
is
include one extra
of Products."
normally called the parity or
is
bit.
we must
in
"Sum
listed
column, the values of A, B, C and D are

listed when P = 1.
For example, for the
column.
In
terms of the
Referring back to figure 23-1, note the
errors.
gle errors
in
D.
been evolved with the capabilities
of detecting and sometimes even correcting
In
C and
A, B,
literals
modern computer. Therefore, many
in a
one type or another

detecting circuit and some of
the
illustrates
parity bit to the B
single error detection.
designed which would generate
the use of an even
C D
it
words.
However,
would be to our advantage to reduce
expression.
192
P.
Therefore,
we make
this
use of the
EXPERIMENT
ELECTRONICS/DIGITAL
Input
MA
>
Binary
101
PARITY CHECKING CIRCUITS
1 1
n
u
R
D
D
r
of
even
Equivalent
Decimal
Sum
Products
parity
THE
Equivalent 1
D C
WORDS
zero
one
ABCD
two
ABCD
three
four
five
six
seven
ABCD
eight
ABCD
nine
ten
eleven
twelve
thirteen
ABCD
fourteen
ABCD
fifteen
Fig.
Boolean identities
P =
in
23-
ABCD
ABCD
Even Parity Words
the following:
ABCD + ABCD + ABCD + ABCD + ABCD
ABCD
ABCD
ABCD
= ABJCD + CDJ + ABjCD + CD) + AB(CD + CD) + AB(CD + CD)

= AB + AB (CD + CD) + (AB + AB) CD + CD
P = (AB + AB) (CD + CD) + (AB + AB) (CD + CD)
(
193
EXPERIMENT
We now
its
101
of P
have the expression
and from
form,
reduced
1 1
design our circuit as
shown
we
this,
in figure
ELECTRONICS/DIGITAL
When
in
these five bits of information are
received at the output end, the 1s are counted.
can
Those which have an even number of
23-2.
accepted as error-free words.
1s are
Those which
have an odd number of 1s are rejected, and

machine takes the course of action
the
The distance between the inputs and

outputs over which the information
ferred
is
irrelevant.
the circuit
is
is
previously
trans-
It
odd
be these four
and the outputs received
will
inputs plus the parity
which can be used
somewhere
in
bit,
In
programmer
fact,
one "1"
bit,
Fig.
23-2
results.
an odd parity would have been
same
would
making possible the

tinction of zero from no information.
tain
line.
possible to use an
better choice because then zero
single error has occurred
the transmission
would have been
parity to accomplish the
INPUTS
the
The important thing about
to understand that four inputs
if
by
operator.
or
are fed into the parity bit generating circuit,
to determine
prescribed
C
D
OUTPUTS
Circuit for Generating the Parity Bit
194
condis-
EXPERIMENT
ELECTRONICS/DIGITAL
101
1 1
MATERIALS
1
Oscilloscope
DC power
supply (0-40V)
10 IC Sockets
10 Dual 4-INPUT
SN15830N
NAND/NOR GATE,
type
or equivalent
PROCEDURE
Figure 23-2
1.
OR
gate.
is
composed of 2 EXCLUSIVE-OR
NAND
diagram of figure 23-2 using only
NOT gates, 2 AND gates, and

NAND gates. Draw a circuit
gates,
implemented from
All of these circuits can be
Have
gate circuits.
this
diagram ready for the
lab instructor's approval before class.
Assemble the individual
2.
circuits
needed and check each one to see that
it
is
operating
correctly.
Now connect the individual circuits

= Vqq and Vj (0) = ground. Make
n
3.
to form the circuit of figure 23-2.

a
Use Vj n 1
truth table to verify that the circuit is working
(
properly.
ANALYSIS GUIDE.
In
the analysis of your results you should verify that the circuit performed
Discuss in your
the desired function.
own words how
single error parity
checks can be used
error detection.
PROBLEMS
1.
2.
Make a table similar to that of figure

The Sum of Products column will also
Use the same method as
odd
3.
Drawa
circuit
4.
(a)
which
will
odd
change.
1.
generate the expression for the odd parity bit of problem
Which of the following output words would be
from the even parity
Which would be
parity instead of even parity.
the discussion to write a reduced Boolean expression
parity bit of problem
for the
(b)
in
23-1 using
in
error
if
they were received
circuit of figure 23-2?

in
error
if
they were received from the circuit of problem 3?
(1)
00001
(6)
01111
(2)
01101
(7)
11111
(3)
11010
(8)
01000
(4)
01001
(9)
00010
(5)
00000
(10)
01010
755
2.
in
EXPERIMENT
101
1 1
Exclusive-OR Gate
NOT
Fig.
23-3
Gate
Gate Diagrams
196
ELECTRONICS/DIGITAL
ELECTRON ICS/DIGITAL
EXPERIMENT
AND
OR
Fig.
23-3
101
1 1
Gate
Gate
Gate Diagrams (cont'd)
197
EXPERIMENT
10111
PA RITY CHECKING CIRCUITS
Truth Table
Fig.
23-4
The Truth Table
198
ELECTRONICS/DIGITAL
experiment
INTRODUCTION TO DIGITAL
TEMPERATURE CONTROL
11000
INTRODUCTION. The
advent of inexpensive integrated circuits has allowed the use of digital

techniques
where
only analog systems were once economically possible. In this expericontrol
ment we
will
examine some basic concepts of
DISCUSSION.
which
may
Digital
of
the pulses.
signal
ble
tell
amplitude or position
the system
how
to
cycles
in
such a
way
is
Since this
from the variable frequency

is
because the controlled device
quency
If
is
is
being used to
fre-
oscillator.
the count that accumulates
determined
is
in
the
the pre-
amount, the controller

does nothing. However, if the count is wrong,
the controller would be activated to correct
The clock of figure 24-1 tells the counter

how long to count the pulses from the varia-
correct
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
oscillator
an indication of
counter during a cycle of the clock
loop digital servo system.
24- 1
a fixed
determine the frequency of the variable
that
the block diagram of a closed-
Fig.
is
the condition of the controlled device. This
re-
when there is no error the pulse information

causes no change in the controlled device.
Figure 24-1
oscillator.
occurring during this time
For closed-loop operation, the error

changes the pulse
frequency
time determined by the clock, the number of
the repeti-
in
These pulses with their atten-
dant information
spond.
systems involve pulses
contain information
tion rate, pulse-width,
digital control.
Digital Control
199
System
EXPERIMENT
11000
DIGITAL TEMPERATURE CONTROL
ELECTRONICS/DIGITAL
V BB = 6V
Fig.
24-2
UJT
Oscillator
Once the capacitor charges
the error which would then produce the correct count, stopping the controller. This general description fits
the concept of a closed-
loop servomechanism where pulses are used
in
age the
UJT
generating
circuit,
shown.
error sensing.
and the base one
discharge through
ter
to this volt-
"fires", allowing the capacitor to
the
emit-
output voltage
The output frequency,
f,
is
given
approximately by
In this
experiment we
will
be concerned
with the variable frequency oscillator.
Figure 24-2
is
the circuit diagram of a
unijunction transistor (UJT) oscillator.
peak potential,
firing or
of the
The
UJT
is
where Rg
is
the total emitter resistance. Thus
given by
R E = R 2 + R3
V p = 7?V BB
Since
where
t?
is
stant for
the intrinsic standoff ratio
any given UJT which
(a
varies
about 0.5 to 0.85 for most devices).
con-
from
Vg B
is
the supply voltage.
is
the variable resistor (could
be varied by temperature,
cally), this circuit
is
light or
mechani-
the one referred to
in the
block diagram of figure 24-1 as the variable
frequency
200
R3
oscillator.
EXPERIMENT
ELECTRON ICS/DIGITAL
1000
DIGITAL TEMPERA TURE CONTROL
MATERIALS
2 Potentiometers, 10 k2, 2W, linear, or a
2 Resistor substitution boxes
decade resistance box
DC power
Capacitor substitution box
Oscilloscope
UJ
Sheet of graph paper
2N4891
Transistor, type
or equivalent
supply (0
40V)
PROCEDURE
1
2.
Connect the
circu
it
of figure 24-2.
Observe and record the waveshapes at the emitter and base one with
R^
set approxi-
mately at mid resistance.

3.
Calculate the approximate frequency for the values of
R^ (which
is
R2 + R3) shown
in
the data table.

4.
Measure and record the output frequency
shown
5.
in
in
pulses per second,
PPS
at the resistance
the data table.
Plot a curve of frequency vs
R E and
plot both calculated and measured frequencies
the graph.
WAVESHAPES
VF
(FIG. 24-2)
RE
1
Calculated Frequency
kfi
2kfi
4ki2
8kS2
10kJ2
12 kft
14kft
16 kft
18 kQ.
20kfi
Fig.
24-3 The Data Table
201
Measured Frequency
on
EXPERIMENT
DIGITAL TEMPERATURE CONTROL
11000
ANALYSIS GUIDE.
measured frequency
Explain
is
why
different
ELECTRONICS/DIGITAL
changes the frequency of operation and why th&
changing
from the calculated
value.
PROBLEMS
1.
Use your graph and determine the value of the
resistance,
R3, for a frequency of
75 Hz.
2.
3.
Determine the resistance of R3 for
Redraw the
resistive type)
4.
R3
ohms with
value of
What would be the
If
value of
if
R3
if
a frequency of
the light intensity on the photocell
put frequency change
Name two
as a photocell (photo-
a frequency of
that the resistance changed from 10k
7.
R2
a given light intensity.
75 Hz was desired when the photo10k ohms? (Use information from problem 1.)
What would be the
condition where the photocell resistance

6.
frequency of 150 Hz.
but show the resistor
with a resistance of 10k
cell resistance is
5.
a desired
if
R3 were
is
in
150 Hz were desired under the
10k ohms?
the previous question should increase so
ohms
to 5k ohms,
held constant at 5k
how much would
the out-
ohms?
other transducers whose resistance change with some physical quantity
that might be used
in
place of the photocell.
202
experiment
INTRODUCTION. An
experiment we
this
DISCUSSION.
used
will
electronic clock
examine
multivibrator
is
and as
operation of the system.
a device to
chronizing multivibrator
very often
is
NOR
words
NOR
OR,
in
which the
output of
when input
a 3-input
OR
circuit
Then
invert
is
1s.
to
is
high (a
1)
is
is
illustrates
the output
OR
the variables:
OR
B + C = Output of
+ B + C = Output of
OR
NOR
By Demorgan's Theorem we
a 1.
and change
the
all
ORs
to
invert each term
ANDs and
vice versa
order to invert a quantity.
is
AX
B X C =
NOR
low
OR
Inverted
NOR
Output
Fig.
25- 1
in-
arriving at
a 1.
when the input
we
the truth table for the
Another way of
is
This
invert them:
The output is a 1 when any of

Note what happens if you
the OR.
By inversion we mean that
is
this in the table,
func-
function.
the inputs
function
the same result
Remember
or input B or input
The truth table of figure 25-1
OR
function.
A+
OR
To do
be
comes from the combination of
NOT
logic blocks.
or vice versa.
verted
called the clock.
performed then inverted.
that the
OR
(a 0)
This syn-
will
from
a clock
change the 1s to 0s and 0s to
synchronize the
The clock used in this experiment

made from two NOR circuits.
is
often called the heart of the digital control system. In
a digital control system to provide
in
pulses,
tion
is
method of making
overall
the
///////
Truth Table for
203
OR and NOR
Output
in
EXPERIMENT
TEMPERA TURE CONTROL CLOCK
100 1
00
25-2
The
Truth Table for a
shown
in
column, for example,
is
truth table for this expression
figure 25-2.
attained by changing the
is
column of
25-1 so that the 1s are 0s and 0s are
output
AND
is
The
Notice that the output
Function
which demonstrates by induction that
figure
1s.
NOR
Output
the same as the inverted column of figure 25-1
accomplished by performing the
operation.
NOR
Fig.
The
ELECTRONICS/DIGITAL
+ B + C = A'
B'
C = NOR
typical digital control system
figure 25-3 in block diagram form.
is
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
Fig.
25-3
Digital Control
204
System
function
is
shown
in
EXPERIMENT
ELECTRONICS/DIGITAL
The clock of
how
ble
Since this
oscillator.
is
time as determined by the clock, the

of cycles
tor occurring during this
the condition
of
This
is
time
is
You have
(free-running)
may be
a fixed
number
oscilla-
an indication
of the controlled device.
is
1001
figure 25-3 tells the counter
long to count the pulses from the varia-
frequency
multivibrators but figure 25-4
you have not previously

encountered.
This one was chosen because
the low price of the integrated circuit makes
it economical, especially since it contains two
total
a version that
NOR
other
being
studied several types of astable
circuits that will be used in the
system to be built
later.
used to determine the frequency of the vari-
The
able frequency oscillator.

If
the count that accumulates in the
is
the
circuit
does nothing. However,
are
the count
is
wrong,
would be activated to correct

the error which would then produce the corthe controller
rect count,
eral
is
actually a
the transistors of the integrated circuit.
predetermined correct amount, the controller

if
collector-coupled astable multivibrator using
The
diagram and integrated circuit layout
shown
quency,
in
f, is
figure 25-5.
The output
by
fre-
given approximately
stopping the controller. This gen-
description fits the concept of a closed-
1.4RC
loop servomechanism where pulses are used

in
where the output
error sensing.
205
is
a symmetrical square wave.
EXPERIMENT
1001
TEMPERA TURE CONTROL CLOCK
ELECTRONICS/DIGITAL
1
Fig.
25-5
Block Diagram and Circuit of the IC
MATERIALS
1
Quad, 2-input
MC
2 Capacitors, 10
1
NOR
integrated circuit,
724P or equivalent
DC power
(iF,
Oscilloscope
2 Potentiometers, 100
6V
supply (0
kft,
1W,
linear or a
40V)
PROCEDURE
1.
Connect the IC so that pin 4 goes to
common
206
and pin
1 1
to the 3.5V supply.
EXPERIMENT
ELECTRONICS/DIGITAL
Input B
Output
(pin 1)
(pin 2)
(pin 3)
Input
TEMPERA TURE CONTROL CL OCK
1001
3.5
o.b
n
U
3.5
3.5
(B)
(A)
25-6
Fig.
2.
3.
Output
Data for the
NOR
Logic
Complete the data table for the NOR 1 (pins 1, 2 and 3) circuit and record the output
voltage in figure 25-6A. Zero voltage means to ground the input
Consider voltage
less
than
and more than
volt a zero
volt a
one and complete the
truth table of 25-6B.

4.
Connect the
circuit of figure 25-4.
connected to
5.
Vqq
Set the resistors to 10 kft. Be sure pins
1 1
and 4 are
and ground, respectively.
Record the output waveshapes
at pins 1, 3,
5 and 7
in figure
25-7.
Use external sync so
that the phase relationship of the waves can be determined.

6.
Adjust the potentiometers one at a time and observe the nonsymmetrical output wave-
form on the oscilloscope.

7.
Adjust the variable resistors

interaction between
R.|
and R 2 to get the waveform of figure 25-8. There will be

it will take considerable adjustment and readjustment
the settings so
to get the desired results. Output can be from either pin 5 or pin 3.
8.
Carefully measure the resistance of each potentiometer and record their values in figure
25-8.
Be sure to indicate where (from which
ANALYSIS GUIDE.
pin)
you got your
In analyzing the results of these data
they agree with the material presented
in
final desired
waveshape.
you should consider whether or not
the discussion.
PROBLEMS
1.
Make
2.
Complement
a truth table for a three-input

(invert) the
AND
circuit.
Call the inputs,
output of the truth table of problem
1.
A, B and C.
What function
is
represented from input to output?

3.
If
complements
NAND
circuit
(inverses) of the three inputs are available,
may
be used to satisfy the
A, B, and C.
207
OR
show and explain how
operation of the original three inputs
EXPERIMENT
11001
ELECTRONICS/DIGITAL
Pin
Pin 3
Frequency =
Pin 5
Pin 7
Fig.
25-7
Data Table for Multivibrator
208
Hz
EXPERIMENT
ELECTRONICS/DIGITAL
4.
Calculate the value of resistors
R-j
11001
and R2 required when Ci = C2 =
mF
to pro-
duce an output frequency of 10 kHz.

5.
What
size capacitors, C-j
and R2,
if
and C2, would be
a frequency of 5
kHz was
ideal for use
with 33 k2 resistors, Ri
desired?
HIGH
0.05
0.1
SEC
SEC
Fig.
Ri =
ohms
R2 =
ohms
25-8
Data for Nonsymmetrical Output
209
experiment
INTRODUCTION.
exercise
ling its
we
will
MANUAL TEMPERATURE
CONTROL
11010
Digital controls are
employed
great variety of industrial systems.
a simple oven,
examine the operation of
basic type of digital control
If
can be represented by the block diagram of

figure 26-1
with emphasis on sensing and control-
digital
This diagram represents a closed-
The clock of
long to count the pulses from the
able frequency oscillator. Since this
is
vari-
a fixed
is
stopping the controller.
error sensing.
is
being used to
determine the frequency of the variable
quency
fre-
the count
count of pulses
rily
FREQUENCY
CONTROLLER
VARIABLE
OSCILLATOR
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
Digital Control
210
System
used
is
in
prima-
The
75-watt lamp while the temperature
DEVICE
26- 1
is
con-
be an oven heated by
CONTROLLED
Fig.
wrong,
itself
with the controlled device.
trolled device will
tored by a thermistor.
oscillator.
is
This general descrip-
This experiment concerns
an indication of
is
if
tion fits the concept of a closed-loop servo-
cycles from the variable frequency oscillator
the condition of the controlled device. This
the
which would then produce the correct count,
mechanism where
is
the
activated to correct the error

is
servomechanism.
in
the controller
how
In this
temperature.
DISCUSSION. A
loop
in a
moni-
ELECTRONICS/DIGITAL
EXPERIMENT
1010
100,000
TYPICAL
RESISTANCE - TEMPERATURE
r.URVF
RB41L1
TC
HQ.
20500
25
10000
50
4020
100
910
125
494
10,000
1,000
o
50
25
Fig.
The thermistor
ment
is
10k
ohm
26-2
25C) model that has
75
100
125
150
Thermistor Curve
to be used in this experi-
(at
AXIMIM SAFE C 3NTINU DUS

TE MPERAT URE
as
temperature goes up, the resistance goes
down and
visa-versa.
Figure 26-2
is
the
negative temperature coefficient of resistance.
sponse curve for the thermistor to be used
this
negative temperature coefficient
means that
211
experiment.
re-
in
EXPERIMENT
11010
Fig.
The experimental setup

ure 26-3.
The thermistor
is
Experimental Setup
26-3
shown
ticular
in fig-
resistance
increase while the
lamp
is
lamp
the 3.5-volt supply turning
SCR
lighted.
switch current.
is
The
circuit,
cycle (when the anode
it
is
AC
line)
is
the
low
The low control current
re-
connected to
later for
control of the
light.
on the SCR. Since
The lamp only conducts current

the power
negative and cathode
The advantage of
for half
the time (on one half cycle) but even though
recovers every half
positive) so the switch will, in effect, turn
both off and on.
the
blocks to be used
has alternating current applied to the
anode-cathode
in
quirement will allow integrated circuit logic
turned on and off with the pushbut-
ton switch because the gate
the
is
arrangement (instead of the switch
being directly
will
change with temperature and the temperature

will
ELECTRONICS/DIGITAL
is
down
the experiment that
it
when you run

about 70% brightness
to half, note
realized with half power.
this par-
212
is
EXPERIMENT
ELECTRONICS/DIGITAL
1010
MATERIALS
1
Oven
box such
(use a cardboard
as a
shoe box)
Pushbutton SPST switch
Resistor, 2.2 kfi,
1/2W
Lamp, 75W,
SCR, GE type C22B
Thermistor, bead type 10 kft,
Line cord
type RB41L1 or equivalent
VOM
15V, with socket
DC power supply
(0 -
or
or equivalent
FEM
40V)
PROCEDURE
1.
Connect the
2.
Push the button and observe that the
3.
Measure the
in
circuit of figure 26-3.
initial
light
comes
on.
resistance of the thermistor with an
ohmmeter and record the value
the space provided in the data table.
4.
Use the curve of figure 26-2 to determine the room temperature.
5.
Hold the switch on so that the

the thermistor resistance.
light
Record
remains
ON
for about 10 seconds. Quickly observe
this value in the data table.
6.
Use the graph of figure 26-2 to determine the temperature.
7.
Repeat
this process for the times listed
on the data
table.
Thermistor Resistance
Room
ANALYSIS GUIDE.
Explain the basic operation of the circuit.
delay of the thermistor

steps in the
Temperature
on the
results.
Also discuss
how
Explain the effect of the time
different lengths of time
experiment might affect the thermistor readings.
Thermistor
Time
Resistance
10 sec
30
sec
50
sec
60
sec
2 min
3 min
Fig.
26-4
The Data Table
213
Temperature
between the
EXPERIMENT 11010 MANUAL TEMPERATURE CONTROL
ELECTRONICS/DIGITAL
PROBLEMS
1.
An ohmmeter
what
that uses current to measure resistance and
effect high
ohmmeter
the thermistor and

2.
3.
4.
is
R.
Explain
(or other) currents would have on the temperature of
figure 26-2 with a straight line.
What
is
the y-intercept?
the slope?
Write an equation for the line you drew in problem 2. The equation for a straight
line is Y = mx + b where m is the slope and b is the y-intercept.
Explain with the aid of diagrams
furnace
5.
2
is
resulting temperature.
its
Approximate the curve of
What
power
in
how
the thermistor could be used to control the
your home.
Briefly explain
how
a thermistor
connected to the evaporator
ditioner in your car could be used to prevent icing.
214
coils of an air con-
TEMPERATURE CONTROL
COUNTERS
experiment
INTRODUCTION.
experiment we
this
In
error
will
measuring device.
DISCUSSION.
is
systems often employ counting as an error detection system.

examine integrated circuit counting and how it can be utilized as an
Digital control
basic digital control system
ter
variable
fixed
the coun-
a closed-loop digital servomecha-
of figure 27-1
frequency
oscillator.
tells
Since this
is
the
time determined by the clock, the num-
ber of cycles
cillator
cation
of
device.
the
is
The clock
how
is

does nothing. However, if the count is wrong,
It
nism.
the count that accumulates in the
represented by the block diagram of figure
27-1.
is
If
is
an
correct count, stopping the controller.
os-
general
is
the pulses
fits
The
concept of
is
used
in
error sensing.
being used to determine the frequency of
the variable
description
the
closed-loop servomechanism where a count of
indi-
the condition of the controlled
This
This would then produce the
error.
frequency
In this
experiment we are going to con-
centrate on the counter and
oscillator.
its
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
Fig.
27- 1
Digital Control
215
System
application
in
EXPERIMENT
11011
ELECTRONICS/DIGITAL
BINARY
3
0
U
DECIMAL
o
1
10
11
12
13
14
15
2
*
BINARY
are going to use
27-3
nary counter.
two
To
inte-
This will give us a four-bit
To
2
a
INPUT
BINARY
1
represent this counter with
and the 2
right
bi-
digit
is
minimum
is
shown on the
which
flow
216
is
reverse to the conventional
in circuit
diagrams.
the
left.
to the table
but makes the signal go from right to
advances to the next count.
con-
shown on
This makes the count correspond
review the operation refer
Each time a pulse comes into the fourit
fusion, the units digit counter
to the table of figure 27-2.
stage counter
Binary Counter
grated circuits with a two-bit binary counter
each one.
Fig.
We
BINARY
such a system.
27-2 Binary Counting
BINARY
in
Fig.
left,
signal
ELECTRONICS/DIGITAL
EXPERIMENT
14
12
13
11011
10
11
_Q
Q_
+v
KEY
ra
Fig.
27-4
Top View of the
The binary counter to be used in this

experiment is shown in figure 27-4. You will
recognize it as two J-K flip-flops in one package. Pins 10 and 12 are the DC clear pins, Cq.
MC 790P
condition until pulsed
In
periment, by pushing a switch), at which time
use
false
it
will
stable
on the
be necessary to
monostable multivibrator to eliminate

counting
bounce.
caused
is
composed of the two
left side
left
in its stable
Fig.
27-5
left.
GROUNDED AND
ICs.
217
NOR
circuits
Note that the

signal flow from
to right, which places the units digit on
the far
IS
The mono-
of figure 27-5.
3.5V
NOTE: BE SURE PIN 4

GOES TO V cc ON ALL
unstable state
stable condition.
its
circuit of figure 27-5 has a
by switch contact
The monostable remains
its
and remains there for a period of time, then
order to observe the counting action
manual operation,
the case of this ex-
the monostable switches to
returns to
by
(in
PIN 11
EXPERIMENT
11011
ELECTRONICS/DIGITAL
MATERIALS
1
Integrated circuit, type
MC
2 Resistors, 2.2 kft, 1/2W
790P
or equivalent
1
MC
4 Lamps, 3V, #48 or equivalent with
724P
sockets
4 Transistors, 2N3709 or equivalent NPN
or equivalent
1
Switch, pushbutton, normally open
Capacitor, 10 fxF,
6V DC
general purpose type
3 Resistor substitution boxes
DC power
supply (0
40V)
PROCEDURE
Connect the
1.
circuit
shown
27-5.
in figure
Apply power and momentarily connect the DC reset line, Cq, to the 3.5-volt supply. All
lamps should be out. A lighted lamp is a 1 and an unlighted lamp is a 0, so the first entry
2.
line in
the data table would be
Press the count button
3.
all
zeros as shown.
one time and enter the
Remember
results in the data table.
the table and circuit are laid out in reverse so that a lamp lighted on the far
a
one on the
right of the data table.

until the first data table
4.
Repeat step three
5.
Zero the counter by applying
6.
Connect the
7.
Press the count button once
8.
Repeat step seven

ing part
output of stage
Vqq
to the
(d) to
is
complete.
Cq
line.
the S input of stage
and enter the
until the data table
is
results in the
(a).
second data
complete. The circuit
is
table.
supposed to stop count-
way through.
ANALYSIS GUIDE.
second data table
Explain the circuit operation and
from that
in
the
tell
why
the count was different
in the
first.
PROBLEMS
1.
Draw
the
the block diagram of the four-stage binary counter with the trigger input to
first stage
being fed by a 2-input
AND.
Explain the circumstances under which
the binary counter will receive something to count.

2.
Suppose one input to the

other input
3;
If
is
AND
grounded. What
a pulse of 0.01 sec duration
to input
zeroed
that
left enters as
1,
gate of problem
will
is
is
being fed a 500-Hz signal, the
the counter do?
fed to input 2 while the 500-Hz signal
what would the counter read
initially.
218
in
binary?
Assume
is
being fed
the counter to be
ELECTRONICS/DIGITAL
4.
If
EXPERIMENT
1101
the pulse duration of problem 3 were 0.04 seconds, what would the counter have
read
in
binary?
5.
Show
a connection so that the counter
6.
Show
would only count
counter that would stop at 12. Use a 2-input
to 8.
AND
DECIMAL
BINARY
3
(b)^
(d)2
circuit to stop the count.
0
1
4
5
6
7
9
10
11
12
13
14
15
Fig.
27-6
The Data Tables
219
EXPERIMENT
101
DECIMAL
BINARY
(d)
23
ELECTRONICS/DIGITAL
(C)2
(b)2
(a)2
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
Fig.
27-6
The Data Tables
220
(Cont.)
experimen
INTRODUCTION.
this
11100
Digital servo
experiment we
AUTOMATIC TEMPERATURE
CONTROL
will
systems are used to control a variety of industrial processes. In
investigate
simplified
example of
working
digital
closed-loop
servomechanism.
DISCUSSION. The block diagram of one

type of digital control system is shown in
the condition of the controlled device.
figure 28-1.
to determine the frequency of the variable
is
frequency
The clock
how
in
This
being used
oscillator.
able frequency oscillator. Since this
is
vari-
If
is
a fixed

cycles
is
determined
correct
if
the count
CONTROLLED
DEVICE
FREQUENCY
VARIABLE
OSCILLATOR
CONTROLLER
COUNTER AND
ERROR MEASURING
DEVICE
CLOCK
28- 1
the pre-
is
wrong,
an indication of
Fig.
the
amount, the controller
oscillator
is
in
Digital Control
221
System
EXPERIMENT
V gB
1 1
- 6.0
100
AUTOMATIC TEMPERATURE CONTROL ELECTRONICS/DIGITAL
VOLTS
2N4891
C
mF
0.5
Fig.
28-2
UJT Oscillator
the error which would subsequently produce
to discharge through
the correct count, stopping the controller.
emitter circuit, generating the output voltage
shown.
A
ing a
this
UJT
will
The
is
we
f,
is
given ap-
firing or
cir-
will use.
peak voltage, V
of the
where Rg
is
the total emitter resistance.
given by
r?
is
stant for
For the control system that we are going

to use, the emitter resistance will be replaced
the intrinsic standoff ratio
(a
by
con-
any given UJT which varies from
about 0.5 to 0.85 for most devices) and

is
proximately by
V^BB
where
and the base one
serve as the pulse source in
experiment.
cuit diagram that
UJT
employ-
variable frequency oscillator
R-j
a thermistor so that as the temperature
varies, the
Vgg
frequency of the variable frequency
oscillator will change.
the supply voltage.
The
Once the capacitor charges to
age the
UJT
is
a collector-
coupled astable multivibrator. The circuit
this volt-
gram and integrated
"fires", allowing the capacitor
222
circuit layout are
dia-
shown
ELECTRONICS/DIGITAL EXPERIMENT 1 1100
KEY-
Fig.
28-3(A)
Top View of One IC

V CC
= 100
to
be Used
=3.5V
R_ = 100 kn
kn
c = 10 mF
C 1 = 10>jF
NOR
1
[2
/Y>J
i
11
TO GROUND
F/ff.
in
figure 28-3.
28-3(B)
An
Integrated Astab/e Multivibrator Clock
given approximately
f,
is
lar
by
waveform is one that

to the one shown in fi 9ure 28-4.
The
desired
The
controlled device in the system will
is
simi-
be an oven employing a lamp as the heating

element.
where the output
is
It is
shown
in
figure 28-5.
The SCR
controls the lamp which heats the oven and
a symmetrical wave.
223
EXPERIMENT
(1)
HIGH
(0)
LOW
1 1
100
AUTOMA TIC TEMPERA TURE CONTROL ELECTRONICS/DIGITAL
Fig.
Fig.
28-5
28-4
Clock Waveform
The Controller and Controlled Device
224
ELECTRONICS/DIGITAL EXPERIMENT
1 1
100
AUTOMA TIC TEMPERA TURE CONTROL
100,000
10,000
in
5
I
O
UJ
o
z
<
f
00
UJ
1,000
100
50
100
75
125
150
TEMPERATURE
Fig.
28-6
Thermistor Curve
The
shown
varies the resistance of the thermistor.
thermistor response to temperature

in figure
is
The counter
periment
shown
28-6.
225
is
in figure
that
we
will use in this ex-
four-bit counter like the
28-7.
one
EXPERIMENT
1 1
AUTOMATIC TEMPERATURE CONTROL ELECTRONICS/DIGITAL
100
Binary Counter
28-7
Fig.
MATERIALS
Potentiometer, 10 k2, 1/2W, linear, or

1
Capacitor, 0.5 mF,
UJT
transistor,
6V
Resistor,
Thermistor, bead type, 10 kfi, type
RB41 L1
4
kS2,
type 2N4891 or
equivalent
1
box
1 15V
75W,
Lamp with socket,
Resistor, 47fi,
DC power
Quad, 2-input NOR integrated

MC 724P or equivalent
Capacitor, 0.5 juF,
Resistors, 2.2 kft,
SCR, GE C22B
Line cord
VOM
or
or equivalent
FEM
MC
790P
or
equivalent
circuit,
4 Lamps with sockets, 3V, #48 or

equivalent
10V DC
2 Potentiometers, 100 kft, 1/2W,
1/2W
supply (0 - 40V)
or equivalent
1/2W
1/2W
Oscilloscope
Resistor substitution
NPN
transistors, type
2N3709
or
equivalent, general purpose
linear,
or decade resistance box
Oven
(use a cardboard
box such
as a
shoe box)
PROCEDURE
1
Figure 28-8 shows the waveform of

for comparison.
2.
The
(c)
They
are not
shown to
part of figure 28-8 illustrates
of pulses
let
in
during time periods
temperature controls the
UJT
clock,
the variable frequency oscillator and (b) the
(a)
actual scale.
what
1
is
desired to go into the counter.
The number
and 3 will be an indication of temperature since
oscillator.
circuit.)
226
(Note: This can be accomplished with an
AND
ELECTRONICS/DIGITAL EXPERIMENT 1 1100
Fig.
28-8
Waveforms
ON
OFF
3.
Time period 3
4.
For this experiment we want to arrange the circuit so that the
is
the time for the light to be
counter reaches a count of
digital
or
depending upon the temperature,
5.
will
turn the
If
positive pulse
is
ferentiate the
time periods
6.
To
SCR OFF when
not reached, the
light will
the count of 8
8.
is
SCR
reached and thus turn the light
OFF.
on the Cq line will zero the counter. Thus, it will be necessary to difwaveform of figure 28-8(b) so that a positive spike at the beginning of
and 3 will zero the counter.
1
output of
(d)
(a).
Use the thermistor curve to determine the resistance at 150F.
UJT
the
(see figure 28-7).
prevent a higher frequency from counting on past zero, connect the
of the
if
remain ON.
of the binary counter to the S input of

7.
OFF
8 (binary 1000). This can be accomplished by con-
necting the 0 output (d) of the binary counter to the gate of the
This
go
light will
Calculate the frequency
using this resistance as the emitter resistor.
Calculate the pulse width needed for time intervals
and
3, etc., to let
8 pulses enter the
counter at 150F.
9.
10.
Apply power to the clock and adjust for the appropriate time
the lamp is lighted are not critical in time length.
Connect the
circuit as in figure
interval.
28-9 and measure the temperature
lamp goes out.
227
in
Intervals
where
the box after the
EXPERIMENT 11100 AUTOMATIC TEMPERATURE CONTROL ELECTRONICS/DIGITAL

OVEN
+6.0V
ROLLED DEVICE^-^
t
10
kn
4**I
+6.0V
0.5
mF
'150
AND
~l
INVERTER
DUE TO INVE RSION

USE WAVEFO RM OF
FIGURE
'
28-4.
LAMP
LAMP
r-
LAMP 2'
LAMP
I
CD
CLOCK
FIGURE
~1
C = 0.05mF
^ R=
DIFFERENTIATOR
22 kfi
28-3
USE
__J
WAVEFORM OF
FIGURE
28-8(b)
Fig.
28-9
Experimental Setup
228
DIFFERENTIATOR
r If
2-
ELECTRONICS/DIGITAL EXPERIMENT
ANALYSIS GUIDE.
1 1
100
Explain the circuit operation.
PROBLEMS
1.
Determine the necessary changes to regulate the temperature
2.
Repeat problem
for a temperature of 250 F.
229
at
200 F.
experiment
one of the most frequently encountered applications of

elements of the digital
In this experiment we will examine some of the
computer to perinvestigate the function of each element and program the
INTRODUCTION. The computer

electronics.
digital
We
computer.
form
11101
will
is
a calculation.
DISCUSSION.
Solving problems with a digi-
the calculation
is
completed.
Pulse trains of
computer has greatly affected today's

The speed with which solutions are
world.
correct amplitude and sequence are generated
obtained has enabled space travel to proceed
computer's operations are kept
tal
at a fantastic rate.
The
actual
programming
in
acteristics
new model
has
its
own
The memory elements
char-
to be used
and special applications.
structions
Computer programs can be used

simple
to solve
R-L-C networks and then plot the
corresponding time constant curve. Or, the

ideal frequency response of an amplifier can
be predicted.
Programs are available that
will
what frequencies an oscillator will

function, and what the output waveform will
look like. Other applications for computers
indicate at
are in payroll distribution, billing charge ac-
the
all
synchroni-
in
zation by the control elements.
of computers has changed in the past few
years and each
the control logic section and thus
in
are
store data that
arithmetic operations, and

stored
also
Magnetic cores,
tapes,
the
in
is
in-
memory.
and disks are used
simultaneously to store large
amounts
of data
and instructions.
The arithmetic element

of flip-flops and gates and
consists mostly
all
the actual
cal-
culations take place in this part of the comCounters and registers are the most
puter.
common
circuits
used
in
part of the
this
computer.
counts, records on checking accounts, medical
The input-output
research, etc.
are the
Each
digital
computer
of the circuits studied
is
in this
elements
1)
in
computer.
each
digital
nicates with the computer.
There
structions are fed into the
course.
There are four main

computer. They
the control logic, 2) the
means by which the operator commu-
combination
are literally thousands of flip-flops and gates

in a typical
units of the computer
memory,
are:
3) the
arithmetic element, and 4) the input-output

equipment. The interconnection of these four
elements comprises the working parts of the
computer.
The control logic section is probably the

most complex of the four elements. It begins
the computations and terminates them when
Raw
data and
in-
computer through
them, the computations are performed within

the computer, and the results are compiled
and "returned" to the operator via the output

take
devices. Analog to digital conversations
place in this section and
human commands
machine language. Machine

language could be fed directly into a compureter and the computations performed and
are converted into
this
corded, then an operator could convert
language into meaningful data, but the speed
at
which the computer does
faster than that of
230
human
this
operators.
is
much
EXPERIMENT
ELECTRONICS/DIGITAL
The
size of
1 1
computers varies from small
the East coast and the required information
portable models used for special applications

large
to
superimposed on the
is
that are seen each

are
TV
week on
demonstrated.
appli-
computer on the West coast may
store the information concerning a
experiment we
program the
will
computer to do some problem solving for us.

The programs are simple ones but the problem
solving ability of the computer will be readily
during play
examples of long distance computer
cations.
In this
tournament standings
golf
screen.
thousands of
larger units
away which are used for general purpose

computations. The baseball player's batting
miles
average and the
TV
may be
stationary computers that
with even
linked
101
may be
game on
program using Fortran IV
compute the RC time con-
written to
stant for a
known
value of R and C.
MATERIALS
IBM 1401 computer system
(or equivalent)
to include 1401 processing unit,

drive,
20 Blank
1402 cardread punch, 1403
1311 disk storage
printer,
and 26 printing card punch.
cards.
PROCEDURE
Punch the program cards to read as shown
cause the program NOT to run properly.
1.
0 U T
mistake
in
the cards wil
0
0
N T
0 R M A T
N D
U S
U T
T 0
G 0
Any
figure 29-1.
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
T +
in
T 0
Fig.
29-1
231
EXPERIMENT
11101
ELECTRONICS/DIGITAL
2.
Load the program into the card read-punch
3.
Get the printout sheet from the
4.
Double the value of R and load the new program into the card read-punch
5.
Repeat step
printer.
unit.
3.
ANALYSIS GUIDE. Compare

relationship exists
unit.
the
two computer solutions when R =
1.0,
and R =
2.0.
between them? Why?
PROBLEMS
1.
Calculate values for the voltage across the capacitor
and 50
2.
R =
is
Explain
0, 5, 10, 20, 30, 40,
1.0.
computed values and compare them with the computer

more correct at T = 1/2r? where T = 1r?
Plot the
value
3.
sec;
when
why you
think your answer to problem 2
232
is
correct.
values.
Which
What
INTRODUCTION.
Digital
VMM A RY OF LOGIC
experiment
OPERA TIONS
has
logic
its
own
language of symbols and modes of operation.
many
Electronics can be used as the vehicle for performing
we
DISCUSSION. Logic symbols and diagrams

complex
can represent the operation of very
systems
logic
In this
any language,
As with
may
also be used to designate true
or false.
thorough under-
necessary for effective communication.
that
state
system
logic
the
all
diagram
logic
is
set
of standard logic symbols has been agreed
True" or "Negative True".
on,
and they
words True,
will
be used herein.
confuse you
binary system breaks
information
all
up into groups of two elementary
the true
These
bits.
represented by the two states, on or
bits are
When we
off.
are talking
about
these are often expressed as
the
voltage
and
0.
For this reason a translation
"Hi" for
and "Lo" for zero.
made
often
is
important
Lo or Off
The
-12, which
as
+.
It
Hi voltage here or positive term
is
also
common
in
to
negative logic system where the
Up 32
25
16
2
8
2
4
2
presence
designations
0, etc.,
of
is
that the
may
be used
complete
be easy to remember the logic
and 0 to Hi and Lo
if
the
first
letter
of Hi and Lo are disregarded.
Then
they
become
logic.
Hi
1,
In
Lo =
and
0 for positive
0.
the binary system, bits 0 and
are
combined to represent numbers. The numbers

and each successive
bit can be increased in weight by a maximum
factor of two.
The number of bits required
depends on the magnitude of the number to
Logic systems freq-
would be designated
1,
will
It
are each assigned a weight,
uently operate at levels between -24 and -12

volts.
the
individual device or for a
conversion of
simply higher with respect to
voltage.
Lo,
Even the
not necessarily be positive (above ground or
the
than
One other important point
stage.
system.
It is
Hi, and Lo should not

by leading you to think that
more significant than the false.
False,
to
The terms Hi and Lo, True and False,

and 0 are all relative. The Hi voltage need
zero volts).
"Positive
The choice of
more
for an
meaning of these terms must be defined for

a particular
either
times the absence of a signal will be
Hi,
Electron-
levels
is
usually
will
Many
signal.
logic states,
do not have to
correspond exactly to 0 volts and one volt.
ically,
experiment
The presence or absence of
Hi and +.
current
relatively simplified terms.
in
or
standing of the terms, symbols and meanings

is
logic functions.
review some basic logic devices, symbols, and operations.
will
is
the symbols
encounter a
be represented.
-24
the weights assigned to successive bits are:
is
True
In the binary
number system
1/2
1/4
1/8
1/16
2~ 1
2" 2
2" 3
2" 4
233
Down
EXPERIMENT
Each
bit
is
11110
SUMMA RY OF L OGIC OPERA TIONS
all
is
1/2
1/4
1/8
1/16
22
21
Decimal No.
16
be added to the right of the point
decimal point
the binary system
is
there are four basic types of symbols.
The
symbols
basic
called
are
shown
GATES
AND
OUTPUT
INPUTS
INPUTS
AMPLIFIERS
OUTPUT
INPUT
SWITCHING ELEMENTS
MATRIX, REGISTER,
(FLIP FLOPS,
ETC.)
ITRIGGER
SET INPUT
CLEAR INPUT
FF
(RESET)
>
INPUT
DELAY ELEMENTS
Fig.
30-
and outputs which are of importance in a

In the symbol system
particular function.
the decimal system,
more accurate number.
called
-4
2-3
23
to provide a
complete stages are
These tables show the inputs

2-2
24
in
for
2-1
Weight
in
or
devices
10110.1000.
Notice that just as
may
number
Truth Tables.
Binary No.
digits
Input-output tables for either particular
the "True" bits
are added. Therefore, the pure binary
for 22.5
the binary point.
true or false, and to obtain the
number, the weights of
ELECTRONICS/DIGITAL
Logic Symbols
234
OUTPUT
in
figure
These
30-1.
EXPERIMENT 11110 SUMMA RY OF LOGIC OPERA TIONS
ELECTRONICS/DIGITAL
30-2
Fig.
One
Symbol
for the
AND
of the basic logic circuits
Gate
is
the
AND
shown again in figure 30-2.

Notice that it has two or more inputs and
only one output.
The output of an AND
gate will be Hi (1) only when all the inputs
are Hi (1).
A Lo (0) signal on any of the
inputs will cause a Lo (0) on the output.
The logic function of an AND gate is to
gate.
Its
produce
puts
symbol
a true
are
produce
to
output only when
true.
single
a false output.
the circuit
all
is
shown
false
This
in figure
is
all
the
in-
input will
analogous to
30-3.
none of
output
Symbol
30-4
Fig.
its
of
plication
inputs are trues
be a
will
OR
The
outputs.
false.
gates
(all
Gate
false),
its
An
important ap-
in
the timing of
is
on for a
true signal to one
gate can be turned
period of time by applying a
of the inputs which will allow the passage of

signals.
When
the true signal
gate will close.
equivalent
trical
removed, the
is
Figure 30-5 shows an eleccircuit
for
an
OR
gate.
Closing any one of the switches will produce

a voltage across the output.
Obviously
of the switches must be closed for voltage
appear across the Load.
DC VOLTS
Fig.
Fig.
Equivalent Circuit for AND Gate
30-3
30-5
gate
second basic logic circuit
shown
in figure 30-4.
is
the
OR
build
This gate also has
The
two or more inputs and one output.
output will be 1 or Hi when any one of the
inputs
is
Hi.
The
OR
Equivalent circuit for the
OR
Gate
Amplifiers are extremely important ele-
ments
LOAD (OUTPUT)
LOAD (OUTPUT)
DC VOLTS
is
OR
for the
gate's logic function
in
They
logic circuitry.
up the
signal
when
it
are used to
gets too
weak to
maintain the appropriate logic signal
levels.
These amplifiers are normally operated
in
active
region
amplifiers.
and function as
They
also
linear
the
pulse
perform one other
to produce a true (1) output at any time
important function, that of signal inversion.
When
These inverter amplifiers have one input and
one or more of
its
inputs
is
a true.
235
EXPERIMENT 11110 SUMMARY OF LOGIC OPERATIONS
X (OR
IB)
from the
It
said to
is
is
be the com-
in
when
signal
is
This mark indicates
amplifier.
version of the signal.
It
is
in-
The
dicates an inversion.
is
the
OR
is
Conversely, of course,
or normal state.
gates
in-
is
Lo
Hi
Hi
Lo
the symbol
is
is
30-7
possibility
gate with an inverted input,

in
is
Hi.
the
if
The
shown
The output
30-8.
figure
input
is
lo
OR
inversion indicator
used on the inputs of amplifiers,
and switching elements;
The
in
any case
it
inversion dot can likewise appear at
the output (usually of amplifiers and gates)
not
and means that the output

normal inputs.
often
Fig.
Another
B.
to
considered the significant
The same symbol
signal occurs at A, while a Hi
indicates an inversion.
the significant state.

if
Lo
the B input
may be
symbol
inversion
often called a Lo-state indicator. This
say that the Lo-state
if
also used with
other logic symbols and always
is
Hi
of this gate will be Hi
Notice the small circle at the tip of the
there, the Hi-state
Hi
occuring at
symbolically
is
Lo
figure 30-7. This gate produces a hi output
only
two amplifier symbols.
several
Lo
used at the input of logic blocks as shown
inverted
plement of the input.
inverter
Standard and Inverter Amplifiers
30-6
amplifier output
input.
A)
INVERTER AMPLIFIER
Fig.
The
NONINVERTING AMPLIFIER
(A)
one output.
ELECTRONICS/DIGITAL
The
is
inverted for
gate in figure 30-9
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Lo
Lo
Hi
Hi
Lo
The Inverted Input AND Gate
236
OR
EXPERIMENT
ELECTRONICS/DIGITAL
Fig.
its
or an
output inverted.
OR
gate gives us a
The Inverted Input
30-8
of
a Hi at the
are
is
Lo
Hi, a
at
the
NOR
one time.
The same
If
Lo
Lo
Hi
Lo
Hi
Hi
Hi
Lo
Lo
Hi
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
OR
Gate
the inverted
AND
NOR
case
gate
Inverted
This can
gate.
is
output only when
Lo output
Inverting the output
The
with an inverter amplifier.
function
Gate)
30-9
be accomplished by following a normal

gate
OR
(NOR
Fig.
has
11110
OR
is
shown
or
in figure
NAND
circuit.
an
logic
inverter
This
amplifier.
AND
inputs are Hi.
any one of the inputs
gate
is
gate with
type of gate
produces a Lo at the output when
the inputs
Such
30-10. This circuit can
be obtained by following an
to produce
all
Gate
all
of the
Another benefit of the
NAND
to provide level restoration.
will result.
The NAND gate is the basic logic circuit

and from it all other logic circuits can be
sort of situation exists with
Fig.
30- 10
Inverted
AND
237
Gate
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Lo
Hi
Hi
Hi
Lo
(NAND
Gate)
EXPERIMENT 11110 SUMMA RY OF L OGIC OPERA TIONS
ELECTRONICS/DIGITAL
X=AB=A+B=A+B
30-
Fig.
For instance, suppose there
implemented.
an abundance of
OR
gate
NAND
1,
This
this
with
is
Lo
Lo
ttt
Lo
Hi
Hi
and
circuit
Hi
Lo
Hi
is
NAND
one of the many examples of
Hi
Hi
Lo
outputs
the
gives
OR
an
in
problem can be easily solved.
configuration
associated
Gate
on hand, but an
gates
needed immediately. As shown
is
figure 30-1
OR
Phantom
1 1
but
gate
implementation.
30- 13
Fig.
the other
will
is
Exclusive
OR
high, then the
Truth Table
output of the gate
These conditions are shown
be high.
in
the truth table.
30- 12
Fig.
Exclusive
OR
inverter, the result will be a
Gate
Exclusive
The symbol
OR.
Exclusive
produces
in
The
the
differently,
true
output
is
shown
that of the
OR
Exclusive
Gate
When
output
the
is
the outputs are the
To
false.
Exclusive
OR
say
are
However,
if
low,
the
output
produces a
will
or B
is
be
30-14.
arrangement
This configuration
is
is
It
all
the inputs are Hi.
The next
if
either input
This
gate.
followed by an
this
one and only one of the

inputs is false. The truth table for this type
of gate is shown in figure 30-13.
When A
and B are both high, or when both of the
inputs
OR
in figure
is
compliment of the
sometimes called the coincidence gate.

produces a Hi if all its inputs are Lo or if
true output any time the inputs
are not the same.
same,
figure 30-12
OR
the Exclusive
If
flop.
The
outputs.
flop
its
low.
is
last
basic-logic circuit
flip-
This device remembers what
impulse was.
capability of
238
the
basic-logic function of a flip-
storage.
until triggered to
low while
is
can have one or more inputs and two
It
It
remains
the other state.
the flip-flop
in
one
The
makes
it
state
storage
a very
EXPERIMENT 11110 SUMMA RY OF LOGIC OPERA TIONS
ELECTRONICS/DIGITAL
Fig.
important unit
digital
this
30- 14
stay at
All
Q will
systems are made up by grouping of
the
a flip-flop
is
connected as shown
A's output
is
it
as
two
NAND
Gate
is
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Hi
Gate
connected to one
let's
(from
Now
gate
Since
similar
assume an initial starting condition

and Q = 0. Starting with inputs of 1
Now let's
Q is fed
inputs of
that gate B will have
same time we can see
two
inputs so
gate
inputs so
NAND
239
Gate
on R
at
Q goes to 1.
Q goes to 0.
will
be locked at
will
is
locked at
put a
1.
have
In a
0.
on S and
Flip- Flop
0 on
R.
back to gate A, this gate has
B has two
>
30-15
two
goes to
inputs so
Again, due to the feedback loop,
will
The inputs of Gate B become
and 0 so
>
Fig.
0 on S and
feedback loop) so
has
and therefore
at the
manner, the inputs of R both become
Since
on S and 0 on R
have two 0 inputs so
will
feedback to B, this gate
is
Let's
1
put
input.
of
1.
two 0 inputs and
connected to one input of gate
B and gate B's output
Hi
0 and gate
gates
figure 30-15.
in
Lo
same time.
Oand
approach to producing
to consider
Lo
stay at
Now
delays.
interesting
and
basic circuit with gates, amplifiers,
An
OR
Inverted Exclusive
logic systems.
in digital
and thus
goes to
has
0.
two 0
EXPERIMENT
inputs so
1
locked at
is
inputs so
SUM MA RY OF L OGIC OPERA TIONS
11110
is
locked at
The
and gate B has two
The
0.
by what
is
FF
state of a particular
stored in
is
and the FF
line (Q)
This output
is
line
(not Q).
the complement (inverse) of the
stored function.
line
pulses of a given
the
that
PRF
gates will
particular
is
either
clocked
and
can be
or
Clocked
instances of time.
RS FF
limited to applications
is
will
not be activated at the
and truth table for a typical
flip-
device
Figure 30-17 shows the symbol
same time.
be open and closed at
the
because
only one state at a time. Therefore,
where both inputs
to the flip-flop gates so
reset
FF in the Lo state.
R terminals must not be
simultaneously
in
on the
a signal
the
places
use of the
the practice of feeding
by
reset to zero
is
applied
may be
changes when the inputs change.
Inputs to the S and
receive either level or pulse signals.
Flip-flops
(RS FF) is a biand two output
are opposite and respond
The outputs
state
device
The inputs of most FFs can
unclocked. Clocking
lines
RS FFs are always set to 1 and reset to zero.

An input signal is used at the S terminal to
switch the device to a known Hi state. The
identified
usually brought out and labeled
with
available
is
is
The second output
it.
set reset flip-flop
stable with two input

lines.
on an output
ELECTRONICS/DIGITAL
RS
FF.
flop outputs will respond to the inputs only at
The output of the
the proper clock times.
unclocked FF
will
Since the
respond anytime the inputs
Figure 30-16 shows the symbol

toggle flip-flop.
line
It
is
and two outputs.
one
is
until
this
is
another pulse
is
applied.
Since
the case, the state after a trigger pulse
Lo's
applied to
to
both
K,
known.
30-16
flip-
Figure 30-18
This unit
Hi input
to the Hi state.
If
Hi's
produces no change.
and K is the reset line.

much more than a simple
line
is
OUTPUT
INPUT
Fig.
The J-K
the
inputs
The J is the set

The J-K flip-flop
cannot be predicted unless the previous state

is
state.
FF switches to Lo.
If J and K receive Hi's at the same time, the
FF switches to the compliment (if it was
Applying
Hi, it goes Lo and vice versa).
are
stable in either state and remains in that
state
FF
at J switches the
The outputs
change state from one input pulse to the next.

It
no such uncertain
shows the symbol for a J-K FF.

has two inputs and two outputs.
for the
bistable with
has an uncertain state,
another type.
arises for
flop has
change.
input
need
RS FF
Symbol
240
Before
After
Trigger
Trigger
Pulse
Pulse
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
for Toggle
FF
EXPERIMENT 11110 SUMMA RY OF L OGIC OPERA TIONS
ELECTRONICS/DIGITAL
RS
OUTPUT
INPUT
RS
Lo
Lo
Will
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Hi
Fig.
30-
Symbol
RS FF
for an
OUTPUT
INPUT
Fig.
flip-flop
(TFF);
it
normally
is
rank or AC-coupled flip-flop.
method
pling
RC
uses the
either a dual
The
AC
is
faster than the
actually
The
combines two
Several gates are also used

single
logic
element.
All
of
it
The
is
Hi
Lo
Hi
Lo
Hi
Hi
Compliment
for the
both
not
the
FF
input
information
edge sets the FF.
With
at
J.
The
a Hi input at
K, and the
edge of the clock pulse stores the

information at K.
The
trailing
edge
When
and K have Hi inputs, the leading edge
and
K.
The
trailing
edge of the clock pulse
switches the state of the FF.
There are several other major types of
actual operation of the J-K (either
With a Hi input
J-K
of the clock pulse stores information at both
the action of the two FFs and the
clock pulse at the gates.

J,
Hi
of the clock pulse also resets the FF.
usually indicated by the logic symbol.
type)
Lo
input
It
one for
is
Hi
trailing
to form a
this
Lo
No Change
stores the input information at
input storage and one for output storage.

in
Lo
K, only the leading edge of the clock pulse
method
slow capacitor discharge.

flip-flops,
Lo
trailing
time constant of
dual rank
stores
cou-
Symbol
30- 18
the capacitive input for short term storage of

the input information.
Not Change
flip-flops.
operation
at
They
only the leading edge of the clock pulse
241
will
You may wish

of
these
others
to
review the
on your own.
not be discussed here.
EXPERIMENT 11110 SUMMARY OF LOGIC OPERATIONS

MATERIALS
2 DC power
ELECTRONICS/DIGITAL
supplies
Lab oscilloscope or VOM

3 IC, type SN15830N dual 4-input NAND/NOR
gate, or equivalent, and data sheet
1
4 IC sockets
PROCEDURE
1.
The Tl SN15830N
dual 4-input
is
NAND/NOR
Prepare the IC for observation.
gate.
Obtain the correct supply voltage from the data sheet.

2.
Since this IC has 4 inputs

in figure
tie
them together
so that there will be only 2 inputs as
shown
30-19.
AB
X
30- 19
Fig.
3.
Obtain the output for

values
4.
Now
in
Now
NAND
Gate
possible combinations of inputs
and
B.
Record these
an appropriate truth table form.
NOT (INVERTER)
construct the
Fig.
5.
all
Pairing Inputs to
30-20
construct the
circuit as
Construction of
AND
circuit
shown
shown
in
figure 30-20 and repeat step
NOT Circuit for NAND
in figure
3.
Gate
30-21 and repeat step
3.
AB
Fig.
30-21
Construction of
AND
242
Circuit
from
NAND
Gates
EXPERIMENT
ELECTRONICS/DIGITAL
11110
30-22
Fig.
6.
Now construct the OR
7.
Now
construct the
Fig.
8.
Construct the
Construction of
circuit
NOR
30-23
shown
circuit
OR
Circuit
in figure
shown
from
NAND
in figure
shown
circuit as
3.
Construction of NOR Circuit from
EXCLUSIVE-OR
Gates
NAND
3.
Gate
in figure
3.
Fig.
30-24
Construction of
EXCL USI VE- OR
NAND
9.
Construct the COINCI
DENCE
circuit as
from
Gates
shown
243
Circuit
in figure
3.
EXPERIMENT 11110 SUMMA BY OF L OGIC OPERA TIONS
ELECTRONICS/DIGITAL
30-25
Fig.
10.
Construct the
Construction of
RS
COINCIDENCE Circuit from NAND
flip-flop circuit as
shown
in figure
30-15 and obtain and record data
The
truth table form to describe the operation of the flip-flop.
experiment 19 should be connected such that when a

a
is
ANALYSIS GUIDE,
applied to one of the inputs,
in analyzing the results of this
and how they work to achieve
experiment you should describe the
basic
their logical purposes.
PROBLEMS
1.
Convert the decimal number 225.672 to binary.
2.
It
was stated
this
in
the discussion that the
NAND
others can be implemented. There
all
basic
and can
implement
also be used to
all
is
gate
is
the basic logic gate and from
one other gate which
other gates. This
is
the
is
perhaps just as
NOR
gate
shown
below.
We
can see that

1
then B =
0.
implement
if
we want
the output ofjhis device to be only A, then B must be
so that the Boolean identity
equal to
So by
tieing
all
A1 =
can pertain.
except one of the inputs of the
NOT gate as shown
Therefore,
NOR
if
gate to 0
B =
we can
below.
Now
in
triggering circuit of
be applied to the other.
will
logic devices
Gates
using only
NAND
circuit.
NOR
gates implement an
Be sure to
AND
label the inputs to
circuits.
244
circuit,
each
NOR
an
OR
circuit,
and a
gate included in these
EXPERIMENT
Name
Date:
Instructor
Class
Decimal
Binary
Decimal
Decimal
Binary
Binary
Decimal
26
51
76
27
52
77
28
53
78
29
54
79
30
55
80
31
56
81
32
57
82
33
58
83
34
59
84
10
35
60
85
11
36
61
86
12
37
62
87
13
38
63
88
14
39
64
89
15
40
65
90
16
41
66
91
17
42
67
92
18
43
68
93
19
44
69
94
20
45
70
95
21
46
71
96
22
47
72
97
23
48
73
98
24
49
74
99
25
50
75
100
Binary
(A)
Decimal
Binary
Decimal
111011101
353
11101101
557
10110.1101
632
.11011
0.725
.10001
0.5625
(B)
Binary
(C)
Fig.
1-3
The Data Tables
Decimal
Binary
4. (a)
4.(b)
4.(c)
5.(a)
5.(b)
(D)
Decimal
Binary
6.
7.
(E)
Fig.
1-3
EXPERIMENT
Name
Instructor
Class
Date:
THEOREM
Aa v
X
AX
3(b)
THEOREM
A
6(b)
x
TRUTH TABLE FOR
A
B
Fig.
2-10
(B + C)
(A X B) + (A X C)
(B
BOOLEAN EXPRESSION
2-10
SIMPLIFIED EXPRESSION
B
x
Fig. 2-
12
+ C)
AX
= AX
(A X B) + (A X C) =
Fig.
0= 0
n
= n
0_
0
The Data Tables
Fig.
2-10
Fig. 2-11
BOOLEAN EQUATION
A
B
C
SIMPLIFIED EQUATION
Fig. 2-11
THEOREM
BOOLEAN EXPRESSION
A
1
Fig.
2-12
EXPERIMENT
Name
Instructor
Class
Date:
DC
10
Volts
11
12
13
14
60
100
200
500
15
Power Supply Reading

(Multimeter)
Audio Generator Hz
30
1000
Time Duration 1/2 Cycle

Frequency
AC
Volts
Multimeter Reading
100 Hz
Frequency
Rise
500 Hz
Time
Fig.
3-5
The Data Tables
kHz
EXPERIMENT
Name
Date:
Instructor
Class
Waveform
Period
Freq
Period
Freq
Set
Set
Read
Read
Td
50% DC
0.1 /nF
CAP
Parallel
Inductor
Parallel
10
KC Pulse
=10 /xsec
Sketch of
First
Waveform
Sketch of
Second Waveform
Fig. 4- 1 1
The Data Tables
% DC
tr
Identity
of
Wave
Sketch of
Third Waveform
Sketch of
Fourth Waveform
Fig.
4-11
EXPERIMENT
Name
Instructor
Class
Date:
maA
. .
Vq
volts
4U
bU
on
oU
"c
'c
'c
1
I
nn
uu
on
0
2
4
6
8
10
12
14
16
18
20
VC E
l
B Ma
-1.0V
-5.0V
-10.0V
-20.0V
V BE
V BE
v BE
V BE
0
10
20
30
40
60
80
120
160
Fig.
5-17
The Data Tables
/in
'c
EXPERIMENT
Date:
Name
Instructor
Class
CALCULATIONS R L
Waveform
RB
CALCULATIONS
Fig. 6-
10
The Data Tables
rl
no
OI\
OUTPUT
DELAY
K lob
DillLot
CL
CTflD
ARC
o UnAot
P ALL
A
P
TIME
TIME
DURATION
TIME
TIME
rU
RB
POINT X Rg
OUTPUT RgCg
pni
NT X
R BC B
OUTPUT
(Three
^fpn<5 Ahnv/p
cB
POINT X
/
\
~T"
1
hrQQ
Mf cc Q+ar*e
OLcpS
Above Cg)
OUTPUT (Three
Steps Below
Cg)
POINT X
(Three Steps
Below C)
Output Waveform
with
Rg
in
the
circuit
Fig.
6-10
EXPERIMENT
Name
Date:
Class
Waveform
Point
Rg
the
in
Instructor
at
with
Circuit
C B CALCULATIONS
Output Waveform
with
Cg
in
the
Circuit
Fig.
&70
Waveform
Point
Cg
the
in
at
with
Circuit
Output Waveform
with C Three
Steps Above
Waveform
Point
Cg
at
with
Three Steps
Above Cg
Fig.
&10
EXPERIMENT
Name
Date:
Class
Instructor
Output Waveform
With C Three
Steps Below
Waveform
Point
Cg
at
With
C Three Steps
Below Cg
Fig.
6-10
EXPERIMENT
Date:
Name
_____
Instructor
Class
First Circuit
Amplitude
=
II
1
1
Mil
Mil" 'llll
mi
Output Waveform
Second Circuit
Amplitude
MM MM
lilt
MM
II
ll
il
MM MM
II
Period
Output Waveform
Third Circuit
Amplitude
Period
=
llll
llll
Mill
1^
'llll
MM
till
Output Waveform
Fig.
7-12
The Data Tables
till
llll
Fourth Circuit
MM
till
MM
nil"
MM
lilt
Output Waveform
Fig.
7-12
II
MM-
EXPERIMENT
Name
Date:
Instructor
Class
RB
RL
V CC
E IIin
v cc
V C1
tTE
tl_E
Calculated
Measure
Output
Resistor
Clipper
r2
Ri
Calculated
Measure
Output
Diode
Emitter
Clamp
Fig.
8-9
The Data Tables
E in
EXPERIMENT
Name
Instructor
Class
Date:
Output
Input
A = +5
B=
Output Waveform
Input
A=
Output
B = +5
Output Waveform
Fig.
9-11
The Data Tables
Output
Input
A = +5
B = +5
Circuit
Type
Output Waveform
Output
Input
A = +5
B=
Output Waveform
Input
A=
Output
B = +3
Output Waveform
Fig.
9-11
EXPERIMENT
Name
Date:
Instructor
Class
Input
Output
A = +3
B = +3
Circuit
Type
Output Waveform
Circuit Diagram for
Fig.
9-11
Two
Input and Gate
The Data Tables (Cont)
INPUTS
OUTPUT
Fig.
9-11
BOOLEAN EQUATION
EXPERIMENT
10
Name
Date:
Class
V CE
No Input
V CE
Input A Only
Instructor
V CE
Input B Only
First
Circuit
Second
Circuit
Third
If
\J
1
Circuit
Fourth
Circuit
Measured Data
Fig.
10-9
The Data Table
Circuit Diagram
Fig.
10-9
The Data Table (Cont.)
V CE
A&
Input
EXPERIMENT
Name
11
Date:
Class
First Circuit
Data
Instructor
Inputs 0 or
Output
Oor
volts
Boolean Expression
Second Circuit Data

Inputs 0 or
Output
Oor
Boolean Expression
Fig. 1 1-7
The Data Tables
volts
Third Circuit Data
Inputs 0 or
AA
Output
D
D
r>
Li
flnr
u or
\/nlt<;
Boolean Expression
Fourth Circuit Data
Inputs 0 or
Output
Boolean Expression
Fig.
1-7
The Data Table (Cont'd)
Oor
volts
EXPERIMENT
Name
12
Date:
Class
Instructor
E
o
E
U
o
a? 9
+->
ca
>
<-
5 !
E
_ "
CD
3 m
8- o
Ml)
till' "llll
MM
3 >
C 03
"D
CD
<n
.
03
CD
CO
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ic
1
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tO
~>
c 5
CD
03
4->
L.
CO
03
g >
0)
T.
CD
>-
C
CD
"O
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L.
8.
III!
II
MM MM
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tin
Mil -H-H-
MM
Mil" M
II
H-H-
E
i_
C/5
4-
QJ
a
0)
ZJ
>
tO
>
(0
D >
>
-f
~3 E
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CD
II
MM
il
0-5-5
2
c "
E
3 5
c
OQ
L-
ai
>-
C
(D
4-<
"to
5 u
"O
.2
0)
co CD Q.
MM
lilt
MM
Mil
II
MM
MM
MM MM
EXPERIMENT
12
Name
Date:
Class
Instructor
L_
Cl
+-*
CD
>
>
"D
CO
+-*
CD
CD
03
~~El
ch
ea
CO
Q.
-w
O
1
MM
</i
or
CO
-C
CJ
>
CD
CO
cn
ata
i-
CD
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E c
c
eva
DO
Cl
CD
en
w
ice
i_
CD
t_
CD
H
CD
Dc
CO
T3
1.1 i
CD
CO (J Cl
CO
CD
-H-H-
tilt
Mil
Mil'
II
MM
MM mm" MM
Mil
EXPERIMENT
13
Name
Date:
Class
II
Mil
llll
Instructor
mm' -MM
llll
MM' MM
Mil
Output Waveform of
MM MM
llll
First Circuit
llll -t-H-h 'llll
Output Waveform of Second Circuit
MM
Mil
MM
EXPERIMENT
Name
14
Date:
VC
Class
Instructor
=
1
VC2
V C 1'
'C2
MM MM MM MM
MM MM
MM
MM MM mi MM
Mil" 'mm
MM
MM MM
Fig.
14-4
II
il
Mil
MM
The Data Table
II
II
MM MM
lilt
III)
II
il
II
MM
If-
-H-H-
EXPERIMENT
Name
15
Date:
Class
Instructor
ln P ut
Hit
MM mi'
't
Output
1-
llll
llll
0ut P ut
Output
Fig.
15-5
The Data Tables
EXPERIMENT
16
Name
Date:
Class
R-S
Instructor
Mode Truth Table

tn +
Inputs
Outputs
e
b1
C1
c2
Q
t
0
0
n = bit time before

clock pulse
bit
-J
= no input, terminal
left
J-K
time after
clock pulse
floating
Indeterminate
Mode Truth Table

l
Inputs
n+
Triggering Circuit Data
Outputs
S1
Cl
Inputs
Si
Fig.
1&7
Outputs
The Data Tables
EXPERIMENT
Name
17
Date:
Class
Instructor
C1 =
it
MM MM MM MM MM MM MM M il MM
Common
Emitter
V BE
Effects of varying
R1
Effects of varying
MM MM
MM MM MM MM
-H-H-
MM
'1
Common
Emitter
Vq^
*1-
MM
Common
Emitter
MM
Mil] "mm
V^g
Effect of varying trigger frequency
Effect of varying trigger amplitude
Fig. 17-8
The Data Tables
mi MM MM MM
EXPERIMENT
Date:
Name
18
______
Instructor
Class
lilt
il
MM MM
Mil
MM MM MM
MM
lilt
II
MIM MM
Fig.
HH-
III
MM MM
mi
Mil
Mil
llll
Mil' 'till
MM
Mil'
MM
llll
Mil'
MM MM MM MM MM
18-6
The Results
MM
Mil
MM MM MM MM MM MM
till
MM
Mil'
HH
H-H
H"++"
till
till. 4
MM MM' MM
Mil
MM
It
-M-H
MM MM
F/gr.
75-6 777e
ti-
MM
ll II
/?esi//fs
II
H-H-
till
+W
till
Mil
MM
H-H
(Cont'd)
EXPERIMENT
Dat e:
19
Name
Class
Fig. 19-8
Instructor
The Data Tables
Pulse Train Data

ilock
'ulse
FF 0
FF-
FF-
Time
t
= 0
Counting Data
Decimal
CP
Equivalent
FF 2
FF 1
3
4
5
6
7
Figure 19-8 The Data Tables (Cont'd)
FF 0
EXPERIMENT
Name
20
Date:
Class
Instructor
Truth Table
tp
*n
Ring Counter States

Input
Reset
FF,
FF 2
FF 4
FF5
Effect of reset
when count
< 5 was
Fig.
20-4 The Data Tables
MM
Ml)
II
MM' M
1
MM MM M MM
1
<
MM MM MM MM
MM
nil M M
Fig.
Hit"
II
MM MM
(II)
MM MM MM
MM MM
Mil;
MM MM
Mil
mm'
MM
MM MM' MM
II
EXPERIMENT
Name
21
Date:
Instructor
Class
tilt
til)
mi
1)11
lilt*
tin Mill
MM MM MM
MM MM
HII Mil
MM MM
Mill
MM
Fig.
Mil
mm' jlll
Mil'
21-12
1
1
till
MM MM
MM MM MM
The Results
MM
II
II
MM
II
MM
till
Mil
mi' "mm Mil
MM
III!
MM MM
MM
Mil
MM MM HIT
MM MM
nil
Fig.
Mil'
MM MM
till
MM
ntt'
MM MM
MM mm' MM MM MM
21-12
MM
Mil
II
MM
MM
MM
EXPERIMENT
Name
22
Instructor
Class
Date:
Switch
That
23
is
Closed
Voltage Level for
Voltage Level for 0 =
Fig.
22-6
The Data Table
EXPERIMENT
Name
23
Date:
Instructor
Class
AND
OR
Fig.
23-3
Gate
Gate
Gate Diagrams
Fig.
23-3
AND
Gate
OR
Gate
Gate Diagrams (cont'd)
EXPERIMENT
Name
23
Date:
Instructor
Class
Truth Table
Fig.
23-4
The Truth Table
EXPERIMENT 24
Name
Date:
Class
WAVESHAPES
Instructor
(FIG. 24-2)
RE
1
Calculated Frequency
kfi
2kl
8 kfi
10
kn
12 kft
14
kn
16 kfi
18 k2
20 kft
Fig.
24 3 The Data Table
Measured Frequency
EXPERIMENT
25
Name
Date:
Class
Input
Input B
Output
(pin 1)
(pin 2)
(pin 3)
3.5
3.5
3.5
3.5
Instructor
(A)
(B)
Fig.
25-6
Data for the
NOR
Logic
in
in
Frequency =
in
OJ
in
Fig.
25-7
Data Table for Multivibrator
Hz
EXPERIMENT
26
Name
Date:
Class
Instructor
Thermistor
Time
RlCglolal
P Q <l1"3 nIL<C
r*P
10 sec
30
sec
50
sec
60
sec
2 min
3 min
Fig.
26-4
The Data Table
Temperature
EXPERIMENT
Name
27
Date:
Class
Instructor
BINARY
(d)
DECIMAL
23
(b)2
(a)2
0
1
2
3
4
5
6
7
9
10
11
12
13
14
15
Fig.
27-6
The Data Tables
DECIMAL
BINARY
3
(d)2
(C)2
(b)2
(a)
n
0
2
0
1
2
3
4
5
6
7
8
9
10
11
12
To
14
15
F/flr.
27 6 The Data
Tables (Cont.)
378000

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ELECTRONICS

DELMAR PUBLISHERS, MOUNTAINVIEW AVENUE, ALBANY. NEW YORK

By Technical Education Research Centers,

claimed until Sept.

the public domain.

All rights reserved.

the copyright hereon

any form or by any means

Library of Congress Catalog Card

THE UNITED STATES OF AMERICA

Delmar Publishers, a division

Van Nostrand Reinhold,

project presented or reported herein was per-

from the U.S. Office of

The opinions expressed

by the U.S. Office of Education should be

technical personnel in today's industries.

occupations have emerged

with systems and

mechanical, hydraulic, pneumatic, thermal, and

skills is especially significant

electronics. This need for

for the youngster

preparing for a career

requirements well beyond the capability of

a series of closely related publications designed

the broadest possible introduction to technical occu-

effective use of these

laboratory guides for a full-time, post-secondary school study program that

mathematics, technical writing, and electromechanical applications.

unique feature of the manuals

technical laboratory study with mathematics

the close correlation of

and physics concepts.

studied by use of practical examples using

The reinforcement obtained from multiple applications of the concepts

college or technical school students can

satisfactory progress in a well-

coordinated program using these manuals as the primary instructional material.

core of studies for two-year

instrumentation, automation, mechanical design,

This form of technical core program has the advantage

of reducing instructional costs without the corresponding decrease in holding

power so frequently found

general core programs.

This manual, along with the others

the result of six years

by the Technical Education Research Centers,

a national nonprofit, public service corporation with head-

quarters in Cambridge, Massachusetts.

as a direct result of experience gained with students in technical schools

colleges throughout the country.

The Electromechanical Series

an on-going educational program

have been developed for this program:

program or for assistance

Cambridge, Massachusetts 02138

provide meaningful experience

portion of any technology program

The topics included provide exposure

basic principles of digital logic, logic gates,

to use the materials