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Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features (continued)
Features
2.5 A maximum peak output current
Drive IGBTs up to IC = 150A, VCE = 1200V
Optically isolated, FAULT status feedback
SO-16 package
CMOS/TTL compatible
500 ns max. switching speeds
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
HCPL - 316J
HCPL - 316J
HCPL - 316J
3-PHASE
INPUT
HCPL - 316J
HCPL - 316J
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
HV
FAULT
MICRO-CONTROLLER
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
HCPL-316J Gate Drive
HCPL-316J
C
RF
VIN+
VE
16
VIN-
VLED2+
15
VCC1
DESAT
14
GND1
VCC2
13
RESET
VC
12
FAULT
VOUT
11
VLED1+
VEE
10
VLED1-
VEE
CBLANK
100
DDESAT
+
VF
+
RG
VCE
+ *
RPULL-DOWN
VCE
* THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED.
UVLO
VIN+
VIN-
(VCC2 - VE)
X
X
Active
X
Low
X
High
X
X
High
Low
X
X
X
Not Active
Output Control
The outputs (VOUT and FAULT) of the HCPL316J are controlled by the combination of VIN, UVLO and a detected
IGBT Desat condition. As indicated in the below table, the
HCPL316J can be configured as inverting or noninverting using the VIN+ or VIN- inputs respectively. When an inverting configuration is desired, VIN+ must be held high
and VIN- toggled. When a noninverting configuration is
desired, VIN- must be held low and VIN+ toggled. Once
UVLO is not active (VCC2 VE > VUVLO), VOUT is allowed to
go high, and the DESAT (pin 14) detection feature of the
HCPL316J will be the primary source of IGBT protection.
UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- <
12.4 V. Thus, the DESAT detection and UVLO features of
the HCPL316J work in conjunction to ensure constant
IGBT protection.
Desat Condition
Detected on
Pin 14
Pin 6
(FAULT)
Output
X
Yes
X
X
No
X
Low
X
X
High
VOUT
Low
Low
Low
Low
High
VCC1
Under normal operation, the input gate control signal directly controls the IGBT gate through the isolated output
detector IC. LED2 remains off and a fault latch in the input buffer IC is disabled. When an IGBT fault is detected,
the output detector IC immediately begins a soft shutdown sequence, reducing the IGBT current to zero in a
controlled manner to avoid potential IGBT damage from
inductive overvoltages. Simultaneously, this fault status
is transmitted back to the input buffer IC via LED2, where
the fault latch disables the gate control input and the active low fault output alerts the microcontroller.
During powerup, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage
to the IGBT, by forcing the HCPL316Js output low. Once
the output is in the high state, the DESAT (VCE) detection feature of the HCPL316J provides IGBT protection.
Thus, UVLO and DESAT work in conjunction to provide
constant IGBT protection.
VLED18
13
INPUT IC
VIN+
VIN-
12
1
LED1
D
R
I
V
E
R
UVLO
11
14
9,10
LED2
16
5
FAULT
6
SHIELD
4
GND1
VOUT
DESAT
DESAT
SHIELD
RESET
FAULT
VCC2
VC
OUTPUT IC
15
VLED2+
VEE
VE
VIN+
VE
16
VIN-
VLED2+
15
VCC1
DESAT
14
GND1
VCC2
13
RESET
VC
12
FAULT
VOUT
11
VLED1+
VEE
10
VLED1-
VEE
Pin Descriptions
Symbol
Description
Symbol
VIN+
Description
Common (IGBT emitter) output supply voltage.
VIN-
Inverting gate drive voltage output
VLED2+
(VOUT ) control input.
VCC1
Positive input supply voltage. (4.5 V to 5.5 V)
DESAT
HCPL-316J Pkg Pinout
GND1
Input Ground.
RESET
FAULT
VLED1+
VLED1-
VCC2
VOUT
Ordering Information
HCPL-316J is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part number
RoHS
Compliant
Non RoHS
Compliant
-000E
No option
-500E
#500
HCPL-316J
Surface
Mount
Package
Tape
& Reel
IEC/EN/DIN EN
60747-5-2
Quantity
SO-16
45 per tube
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-316J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-316J to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-2
Safety Approval and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation #XXX is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use -XXXE.
Package Outline Drawings
16-Lead Surface Mount
0.018
(0.457)
0.050
(1.270)
16 15 14 13 12 11 10 9
TYPE NUMBER
DATE CODE
A 316J
YYWW
0.458 (11.63)
0.295 0.010
(7.493 0.254)
0.085 (2.16)
0.406 0.10
(10.312 0.254)
0.025 (0.64)
0.345 0.010
(8.763 0.254)
0.018
(0.457)
0.138 0.005
(3.505 0.127)
08
0.025 MIN.
0.408 0.010
(10.363 0.254)
ALL LEADS
TO BE
COPLANAR
0.002
0.008 0.003
(0.203 0.076)
STANDOFF
Package Characteristics
All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, VCC2 - VEE = 30 V,
VE - VEE = 0 V, and TA = +25C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Note
Input-Output Momentary
VISO
3750
Vrms
Withstand Voltage
1, 2,
3
3
Resistance (Input-Output)
RI-O
>109
Capacitance (Input-Output)
CI-O
1.3
pF
f = 1 MHz
qO9-10
30
C/W
TA = 100C
qI4
60
TEMPERATURE (C)
200
PEAK
TEMP.
245C
PEAK
TEMP.
240C
2.5C 0.5C/SEC.
30
SEC.
160C
150C
140C
SOLDERING
TIME
200C
30
SEC.
3C + 1C/0.5C
100
PREHEATING TIME
150C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
50
100
150
200
TIME (SECONDS)
tp
Tp
TEMPERATURE
TL
Tsmax
260 +0/-5 C
217 C
RAMP-UP
3 C/SEC. MAX.
150 - 200 C
RAMP-DOWN
6 C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 C to PEAK
TIME
NOTES:
THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 C, Tsmin = 150 C
PEAK
TEMP.
230C
250
Regulatory Information
The HCPL-316J has been approved by the following
organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5,
File CA 88324.
Symbol
Characteristic
Unit
I - IV
I - IV
I - III
Climatic Classification
55/100/21
VIORM
891
VPEAK
VPR
1670
VPEAK
VPR
1336
VPEAK
VIOTM
6000
VPEAK
TS
PS, INPUT
PS, OUTPUT
175
400
1200
C
mW
mW
RS
>109
*Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802.
**Refer to the optocoupler section of the Isolation and Control Components Designers Catalog, under Product Safety Regulations section IEC/
EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.
1400
PS, OUTPUT
PS, INPUT
PS POWER mW
1200
1000
800
600
400
200
0
25
50
TS CASE TEMPERATURE C
Symbol
Value
Units Conditions
Tracking Resistance
(Comparative Tracking Index)
CTI
>175
Isolation Group
Volts
IIIa
Symbol
Min.
Max.
Units
C
Note
Storage Temperature
Ts
-55
125
Operating Temperature
TA
-40
100
TJ
125
|Io(peak)|
2.5
IFAULT
8.0
mA
VCC1
-0.5
5.5
Volts
-0.5
VCC1
(VCC2 - VEE)
-0.5
35
(VE - VEE)
-0.5
15
(VCC2 - VE)
-0.5
35 - (VE - VEE)
Vo(peak)
-0.5
VCC2
Collector Voltage
VC
VEE + 5 V
VCC2
DESAT Voltage
VDESAT
VE
VE + 10
PO
600
PI
150
mW
Symbol
Min.
Max.
Units
Note
Operating Temperature
TA
-40
+100
VCC1
4.5
5.5
Volts
(VCC2 - VEE)
15
30
(VE - VEE)
15
(VCC2 - VE)
15
30 - (VE - VEE)
Collector Voltage
VC
VEE + 6
VCC2
28
Units
VIN+L, VIN-L,
VRESETL
VIN+H, VIN-H,
2.0
VRESETH
IIN+L, IIN-L,
IRESETL
-0.5
-0.4
IFAULTL
5.0
12
IFAULTH
-40
IOH
-0.5
0.8
-1.5
mA
Test Conditions
VIN = 0.4 V
VFAULT = 0.4 V
30
VFAULT = VCC1
31
VOUT = VCC2 - 4 V
3, 8,
32
-2.0
VOUT = VCC2 - 15 V
0.5
2.3
2.0
IOLF
90
160
230
VOH
VC - 3.5
VC - 2.5
VC - 1.5
VC -2.9
VC - 2.0
VC - 1.2
IOUT = -650 A
VC
IOUT = 0
IOL
Fig. Note
7
5
7
VOUT = VEE + 15 V
4, 9,
33
mA
VOUT - VEE = 14 V
5, 34
IOUT = -100 mA
6, 8,
35
9, 10, 11
7, 9,
36
26
10, 37
38
VIN+ = VIN- = 0 V,
VCC1 = 5.5 V
11, 12, 11
39, 40
ICL
0.3
1.0
IOUT = 0
15, 59 27
ICH
0.3
1.3
IOUT = 0
15,58
1.8
3.0
IOUT = -650 A
15,57
IEL
-0.7
-0.4
14, 61
IEH
-0.5
-0.14
14, 40 25
Blanking Capacitor
ICHG
-0.13
-0.25
-0.33
Charging Current
-0.18
-0.25
-0.33
VDESAT = 0 - 6 V
Blanking Capacitor
IDSCHG
10
50
Discharge Current
VDESAT = 7 V
42
UVLO Threshold
VUVLO+
VOUT > 5 V
43
13, 41 11, 12
VDESAT = 0 - 6 V,
TA = 25C - 100C
12.3
13.5
VUVLO-
11.1
12.4
VOUT < 5 V
UVLO Hysteresis
(VUVLO+ -
VUVLO-)
0.4
1.2
DESAT Threshold
VDESAT
6.5
7.0
7.5
11.6
27
9, 11, 13
9, 11, 14
16, 44 11
Min.
Typ.
Max.
Units
Note
Rg = 10
Cg = 10 nF,
17,18,19, 15
20,21,22,
f = 10 kHz,
Duty Cycle = 50%
45,54,55
PWD
-0.30
0.02
0.30
16,17
(tPHL - tPLH)
PDD
-0.35
0.35
17,18
tr
0.1
tf
0.1
Rg = 10 ,
Cg = 10 nF
45
23,56
19
24,28,
46,56
25,47,
56
20
56
21
26,27,
56
22
49
13
tDESAT(LOW)
0.25
PWRESET
tUVLO ON
4.0
VCC2 = 1.0 ms
tUVLO OFF
6.0
ramp
14
TA = 25C,
VCM = 1500 V,
VCC2 = 30 V
23
TA = 25C,
VCM = 1500 V,
VCC2 = 30 V
10
0.1
50,51,
52,53
24
Notes:
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit,
II-O 5 A). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table, if applicable.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation
Characteristics Table.
3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
4. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power
dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB
Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/C above 90C.
Input IC power dissipation does not require derating.
5. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO
peak minimum = 2.0 A. See Applications section for additional details on IOH peak. Derate linearly from 3.0 A at +25C to 2.5 A at +100C. This
compensates for increased IOPEAK due to changes in VOL over temperature.
6. This supply is optional. Required only when negative gate drive is implemented.
7. Maximum pulse width = 50 s, maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
9. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH
will approach VCC as IOH approaches zero units.
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once VOUT of the HCPL-316J is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the HCPL-316J will be the primary
source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- <
12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection.
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the increasing (i.e. turn-on or positive going direction) of VCC2-VE.
14. This is the decreasing (i.e. turn-off or negative going direction) of VCC2-VE.
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
17. As measured from VIN+, VIN- to VOUT.
18. The difference between tPHL and tPLH between any two HCPL-316J parts under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low.
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 s is the guaranteed minimum FAULT signal pulse width when the HCPL-316J is configured for Auto-Reset. See the Auto-Reset section in the applications
notes at the end of this data sheet for further details.
23. Common mode transient immunity in the high state is the maximum tolerable
dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and
a 3K pull-up resistor is needed in fault detection mode.
24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650
A while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pulldown resistor is not used.
27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE.
28. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control
of the IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper
operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
11
Performance Plots
1.6
1.4
1.2
1.0
-40 -20
20
40
60
80
5
VOUT = VEE + 15 V
VOUT = VEE + 2.5 V
4
3
2
1
0
-40 -20
100
80
100
-1
-2
-3
20
40
60
80
IOUT = 100 mA
0.15
0.10
0.05
0
-40 -20
100
20
40
60
80
100
3
2
1
2.0
HCPL-316J fig 9
10
2.5
15
20
25
30
+100C
+25C
-40C
28.8
28.6
28.4
28.2
28.0
27.8
27.6
27.4
0.2
HCPL-316J fig 7
ICC1H
ICC1L
10
20
0.6
0.8
1.0
HCPL-316J fig 08
15
0
-40 -20
0.4
20
1.5
25
+100C
+25C
-40C
1.0
50
TA TEMPERATURE C
0.5
-40C
25C
100C
75
HCPL-316J fig 5
0.20
HCPL-316J fig 6
0
0.1
100
29.0
TA TEMPERATURE C
125
IOUT = -650 A
IOUT = -100 mA
-4
-40 -20
150
0.25
0
VOL OUTPUT LOW VOLTAGE V
60
175
HCPL-316J fig 4
40
HCPL-316J fig 3
12
20
200
TA TEMPERATURE C
TA TEMPERATURE C
40
60
80
TA TEMPERATURE C
100
1.8
2.0
2.6
2.5
2.4
ICC2H
ICC2L
2.3
2.2
-40 -20
20
40
60
80
TA TEMPERATURE C
100
-0.15
2.55
2.50
2.45
ICC2H
ICC2L
2.40
2.35
15
20
25
0.50
IE -VE SUPPLY CURRENT mA
-0.20
-0.25
-0.30
-40 -20
30
2
-40C
+25C
+100C
0.5
1.0
1.5
2.0
6.0
-40 -20
0.45
PROPAGATION DELAY s
tPHL
tPLH
0.35
0.30
0.25
25
30
0.40
20
40
60
80
80
100
0.4
0.3
0.2
-40 -20
100
20
40
60
80
100
0.50
VCC1 = 5.5 V
VCC1 = 5.0 V
VCC1 = 4.5 V
0.30
TA TEMPERATURE C
0.35
0.25
-50
60
tPHL
tPLH
HCPL-316J fig 16
0.40
40
0.5
6.5
HCPL-316J fig 15
20
HCPL-316J fig 14
HCPL-316J fig 18
TA TEMPERATURE C
20
0.35
TA TEMPERATURE C
7.0
IOUT (mA)
0.20
15
0.40
0.30
-40 -20
100
TP PROPAGATION DELAY s
IC (mA)
80
7.5
TP PROPAGATION DELAY s
60
0.45
HCPL-316J fig 13
13
40
HCPL-316J fig 12
20
IEH
IEL
TA TEMPERATURE C
PROPAGATION DELAY s
2.60
50
100
TEMPERATURE C
0.45
VCC1 = 5.5 V
VCC1 = 5.0 V
VCC1 = 4.5 V
0.40
0.35
0.30
0.25
-50
50
100
TEMPERATURE C
0.40
0.45
0.40
tPLH
tPHL
tPLH
tPHL
0.25
DELAY s
0.30
0.20
0.40
0.35
DELAY s
DELAY s
0.35
0.30
0.30
0.25
20
40
60
80
0.20
100
10
DELAY s
2.0
1.5
50
0.008
VCC2 = 15 V
VCC2 = 30 V
0.006
2.2
2.0
TEMPERATURE C
50
100
HCPL-316J fig 25
12
0.0030
VCC1 = 5.5 V
VCC1 = 5.0 V
VCC1 = 4.5 V
VCC2 = 15 V
VCC2 = 30 V
10
DELAY s
0.0025
0.0020
0.0015
20
30
40
LOAD RESISTANCE
50
4
-50
50
100
150
TEMPERATURE C
10
20
30
40
LOAD CAPACITANCE nF
HCPL-316J fig 24
0.004
0.002
TEMPERATURE C
100
HCPL-316J fig 23
VEE = 0 V
VEE = -5 V
VEE = -10 V
VEE = -15 V
1.6
-50
100
50
1.8
TEMPERATURE C
DELAY ms
2.4
2.5
DELAY s
0.25
-50
50
2.6
VCC2 = 15 V
VCC2 = 30 V
DELAY s
40
HCPL-316J fig 22
3.0
14
30
HCPL-316J fig 21
0.0010
10
20
LOAD RESISTANCE
LOAD CAPACITANCE nF
1.0
-50
0.35
50
IFAULT
VIN-
VLED2+
VCC1
GND1
VIN+
VE
VIN-
VLED2+
DESAT
VCC1
DESAT
VCC2
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VLED1-
0.1 F
0.1
F
10 mA
5V
RESET
VC
FAULT
VOUT
VEE
VLED1+
VEE
VEE
VLED1-
VEE
5V
IFAULT
HCPL-316J fig 30
0.1
F
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
0.1 F
30 V
0.1 F
15 V
PULSED
IOUT
30 V
0.1 F
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
15
30 V
0.1 F
0.1 F
+
IOUT
30 V
+
15 V
PULSED
HCPL-316J fig 33
0.1 F
5V
0.1
F
0.1 F
HCPL-316J fig 32
HCPL-316J fig 31
VE
VIN+
+
5V
VIN+
5V
30 V
0.1 F
IOUT
+
14 V
0.1
F
30 V
0.1
F
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
HCPL-316J fig 34
HCPL-316J fig 35
0.1 F
VE
0.4 V
VIN+
4.5 V
0.1
F
30 V
0.1 F
VOUT
2A
PULSED
0.1
F
30 V
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
0.1 F
VOUT
VLED1+
VEE
VLED1-
VEE
ICC1
0.1 F
100
mA
VC
FAULT
5.5 V
30 V
0.1
F
VOUT
30 V
0.1
F
ICC1
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
HCPL-316J fig 37
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
0.1
F
5V
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
RESET
VC
FAULT
VOUT
FAULT
VOUT
VLED1+
VEE
VLED1+
VEE
VLED1-
VEE
VLED1-
VEE
30 V
ICC2
0.1 F
0.1 F
30 V
HCPL-316J fig 38
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VLED1-
HCPL-316J fig 39
0.1 F
VIN+
0.1
F
5V
30 V
ICC2
0.1 F
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VEE
VLED1+
VEE
VEE
VLED1-
VEE
0.1 F
30 V
HCPL-316J fig 40
HCPL-316J fig 41
16
0.1
F
ICHG
0.1
F
5.5 V
VE
VIN-
HCPL-316J fig 36
0.1
F
VIN+
VIN+
5V
0.1
F
30 V
0.1 F
0.1 F
30 V
VE
VLED2+
GND1
VCC2
RESET
IDSCHG
0.1
F
5V
30 V
0.1 F
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VEE
VLED1+
VEE
VEE
VLED1-
VEE
FAULT
VOUT
VLED1+
VLED1-
0.1 F
30 V
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VLED1-
VIN
SWEEP
0.1
F
0.1
F
15 V
+
VE
+
VIN+
0.1
F
0.1 F
5V
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
VC
FAULT
VOUT
VEE
VLED1+
VEE
VEE
VLED1-
VEE
0.1 F
15 V
3k
3k
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
0.1 F
0.1
F
VOUT
10
30 V
10
nF
VIN
VOUT
10
10
nF
0.1
F
0.1
F
30 V
5V
0.1
F
0.1
F
3k
VFAULT
30 V
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
HCPL-316J fig 46
17
30 V
HCPL-316J fig 45
5V
0.1 F
HCPL-316J fig 44
VIN+
0.1 F
HCPL-316J fig 43
VIN+
RESET
0.1
F
VOUT
HCPL-316J fig 42
10 mA
SWEEP
+
VC
HCPL-316J fig 47
VIN
0.1
F
0.1
F
10
10
nF
DESAT
0.1
F
VCC1
VIN-
7V
VIN+
30 V
0.1
F
+
30 V
3k
VIN HIGH
TO LOW
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VFAULT
0.1
STROBE F
8V
VOUT
VLED1+
VEE
VLED1-
VEE
30 V
0.1
F
5V
0.1
F
VC
FAULT
5V
0.1
F
0.1
F
10
30 V
3k
10
nF
1
5V
VIN+
VE
16
VIN-
VLED2+
15
VCC1
DESAT
14
GND1
VCC2
13
RESET
VC
12
0.1
F
100 pF
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
25 V
0.1 F
SCOPE
100 pF
FAULT
VOUT
11
VLED1+
VEE
10
VLED1
VEE
VIN+
10
5V
0.1
F
HCPL-316J fig 49
VE
16
VLED2+
15
VIN-
VCC1
DESAT
14
GND1
VCC2
13
RESET
VC
12
FAULT
VOUT
11
VLED1+
VEE
10
VLED1
VEE
25 V
0.1 F
10
10 nF
9V
VCm
HCPL-316J fig 50
VE
16
VIN-
VLED2+
15
VCC1
DESAT
14
GND1
VCC2
10
nF
750
10 nF
VIN+
RAMP
10
VCm
0.1
F
VOUT
3 k
3 k
SCOPE
VIN-
0.1
F
VE
HCPL-316J fig 48
5V
VIN+
1
5V
0.1 F
25 V
0.1
F
13
3 k
VIN+
VE
16
VIN-
HCPL-316J fig 51
VLED2+
15
VCC1
DESAT
14
GND1
VCC2
13
RESET
VC
12
FAULT
VOUT
11
VLED1+
VEE
10
VLED1
VEE
3 k
5
RESET
VC
12
FAULT
VOUT
11
VLED1+
VEE
10
VLED1
VEE
25 V
0.1 F
SCOPE
100
pF
10
10 nF
100 pF
VCm
VCm
18
SCOPE
10
10 nF
VINVIN-
0V
VIN+
2.5 V
2.5 V
VIN+
2.5 V
5.0 V
2.5 V
tr
tf
tr
90%
90%
50%
50%
10%
VOUT
tPLH
tf
10%
VOUT
tPHL
tPLH
tPHL
tDESAT (FAULT)
HCPL-316J fig 54
tDESAT (10%)
HCPL-316J fig 55
tDESAT (LOW)
7V
VDESAT
50%
tDESAT (90%)
VOUT
90%
10%
FAULT
50% (2.5 V)
tRESET (FAULT)
RESET
50%
HCPL-316J fig 56
19
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VLED1-
0.1 F
5V
0.1
F
30 V
0.1 F
IC
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VEE
VLED1+
VEE
VEE
VLED1-
VEE
0.1 F
650 A
30 V
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
VC
0.1 F
5V
0.1
F
30 V
0.1 F
IC
+
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
FAULT
VOUT
VLED1+
VEE
VLED1+
VEE
VLED1-
VEE
VLED1-
VEE
0.1 F
30 V
HCPL-316J fig 60
HCPL-316J fig 59
0.1
F
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
20
HCPL-316J fig 61
IE
0.1
F
0.1 F
IC
+
0.1 F
30 V
HCPL-316J fig 58
VIN+
5V
30 V
HCPL-316J fig 57
RESET
0.1 F
30 V
0.1 F
0.1 F
30 V
IE
0.1
F
VE
5V
VIN+
0.1
F
30 V
0.1 F
0.1 F
30 V
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are
potentially destructive to the power IGBTs. These failure
modes can be grouped into four basic categories: phase
and/or rail supply short circuits due to user misconnect
or bad wiring, control signal failures due to noise or computational errors, overload conditions induced by the
load, and component failures in the gate drive circuitry.
Under any of these fault conditions, the current through
the IGBTs can increase rapidly, causing excessive power
dissipation and heating. The IGBTs become damaged
when the current load approaches the saturation current of the device, and the collector to emitter voltage
rises above the saturation voltage level. The drastically
increased power dissipation very quickly overheats the
power device and destroys it. To prevent damage to the
drive, fault protection must be implemented to reduce
or turnoff the overcurrents during a fault condition.
A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required
components, board space consumed, cost, and complexity have until now limited its use to high performance
drives. The features which this circuit must have are high
speed, low cost, low resolution, low power dissipation,
and small size.
Applications InformationThe HCPL316J satisfies these criteria by combining a high speed, high output current
driver, high voltage optical isolation between the input
and output, local IGBT desaturation detection and shut
down, and an optically isolated fault status feedback signal into a single 16pin surface mount package.
The fault detection method, which is adopted in the
HCPL316J, is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined
threshold. A small gate discharge device slowly reduces
the high short circuit IGBT current to prevent damaging
voltage spikes. Before the dissipated energy can reach
destructive levels, the IGBT is shut off. During the off
state of the IGBT, the fault detect circuitry is simply disabled to prevent false fault signals.
21
HCPL-316J
5V +
3.3
k
0.1
F
330 pF
VIN+
VE
16
VIN-
VLED2+
15
VCC1
DESAT
14
GND1
VCC2
13
RESET
VC
12
FAULT
VOUT
11
VLED1+
VEE
10
VLED1-
VEE
0.1
F
0.1
F
100 pF
DDESAT
100
VF
VCC2 = 18 V
Q1
VCE
Rg
47
k
0.1
F
+
3-PHASE
OUTPUT
VEE = -5 V
Q2
+
VCE
Description of Operation/Timing
Fault Condition
Normal Operation
During normal operation, VOUT of the HCPL-316J is controlled by either VIN+ or VIN-, with the IGBT collector-toemitter voltage being monitored through DDESAT. The
FAULT output is high and the RESET input should be held
high. See Figure63.
NORMAL
OPERATION
VINNON-INVERTING
CONFIGURED
INPUTS
INVERTING
CONFIGURED
INPUTS
FAULT
CONDITION
0V
5V
VIN+
VIN-
5V
VIN+
5V
VDESAT
7V
VOUT
FAULT
RESET
22
Reset
The FAULT output remains low until RESET is brought
low. See Figure 63. While asserting the RESET pin (LOW),
the input pins must be asserted for an output low state
(VIN+ is LOW or VIN- is HIGH). This may be accomplished
either by software control (i.e. of the microcontroller) or
hardware control (see Figures 73 and 74).
RESET
23
Output IC
Three internal signals control the state of the driver output: the state of the signal LED, as well as the UVLO and
Fault signals. If no fault on the IGBT collector is detected,
and the supply voltage is above the UVLO threshold,
the LED signal will control the driver output state. The
driver stage logic includes an interlock to ensure that the
pull-up and pull-down devices in the output stage are
never on at the same time. If an undervoltage condition
is detected, the output will be actively pulled low by the
50x DMOS device, regardless of the LED state. If an IGBT
desaturation fault is detected while the signal LED is on,
the Fault signal will latch in the high state. The triple darlington AND the 50x DMOS device are disabled, and a
smaller 1x DMOS pulldown device is activated to slowly
discharge the IGBT gate. When the output drops below
two volts, the 50x DMOS device again turns on, clamping the IGBT gate firmly to Vee. The Fault signal remains
latched in the high state until the signal LED turns off.
Input IC
In the normal switching mode, no output fault has been
detected, and the low state of the fault latch allows the
input signals to control the signal LED. The fault output
is in the opencollector state, and the state of the Reset
pin does not affect the control of the IGBT gate. When a
fault is detected, the FAULT output and signal input are
both latched. The fault output changes to an active low
state, and the signal LED is forced off (output LOW). The
latched condition will persist until the Reset pin is pulled
low.
250 A
LED
VCC1 (3)
UVLO
DELAY
7V
VCC2 (13)
12 V
VC (12)
FAULT
FAULT (6)
DESAT (14)
VIN+ (1)
VIN (2)
GND (4)
VE (16)
VOUT (11)
R S
RESET (5)
50 x
FAULT
VEE (9,10)
1x
HCPL-316J fig 64
24
HCPL-316J
1
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
HCPL-316J
VE
16
VE
16
VLED2+
15
VLED2+
15
DESAT
14
DESAT
14
VCC2
13
VCC2
13
VC
12
VC
12
VOUT
11
VOUT
11
VEE
10
VEE
10
VEE
VEE
Rg
RPULL-DOWN
100 pF
C
100
DDESAT
Rg
3.3
k
330 pF
25
HCPL-316J
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J fig 68
HCPL-316J
VIN+
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J fig 69
HCPL-316J
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J fig 70
26
Auto-Reset
HCPL-316J
HCPL-316J
CONNECT
TO OTHER
RESETS
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
CONNECT
TO OTHER
FAULTS
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
VIN+
VIN-
HCPL-316J fig 72
HCPL-316J
VCC
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VCC
3
VCC1
C
VIN+/
RESET
FAULT
GND1
RESET
RESET
FAULT
FAULT
VLED1+
VLED1+
VLED1-
VLED1-
27
HCPL-316J
VIN+
HCPL-316J
VCC
1
VIN+
VIN-
HCPL-316J
VCC
VIN-
VIN-
VCC
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VCC
3
VCC1
C
4
GND1
RESET
RESET
FAULT
RESET
FAULT
VLED1+
VLED1+
VLED1-
VLED1-
FAULT
HCPL-316J
VE
16
VLED2+
15
DESAT
14
VCC2
13
VC
12
VOUT
11
VEE
10
VEE
100 pF
RC 8
10
10 nF
15 V
28
Figure 73d. Safe hardware reset for inverting input configuration (automatically resets for every VIN- input).
-5 V
To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown
in Figure 75) may be used. Inverting types are not compatible with the desatura-tion fault protection circuitry
and should be avoided. To preserve the slow IGBT turnoff feature during a fault condition, a 10 nF capacitor
should be connected from the buffer input to VEE and
a 10 W resistor inserted between the output and the
common npn/pnp base. The MJD44H11/MJD45H11
pair is appropriate for currents up to 8A maximum. The
D44VH10/D45VH10 pair is appropriate for currents up
to 15 A maximum.
The DESAT diodes function is to conduct forward current, allowing sensing of the IGBTs saturated collectorto-emitter voltage, VCESAT, (when the IGBT is on) and to
block high voltages (when the IGBT is off). During the
short period of time when the IGBT is switching, there is
commonly a very high dVCE/dt voltage ramp rate across
the IGBTs collector-to-emitter. This results in ICHARGE (=
CD-DESAT x dVCE/dt) charging current which will charge
the blanking capacitor, CBLANK. In order to minimize this
charging current and avoid false DESAT triggering, it
is best to use fast response diodes. Listed in the below
table are fast-recovery diodes that are suitable for use
as a DESAT diode (DDESAT ). In the recommended application circuit shown in Figure 62, the voltage on pin 14
(DESAT) is VDESAT = VF + VCE, (where VF is the forward ON
voltage of DDESAT and VCE is the IGBT collector-to-emitter voltage). The value of VCE which triggers DESAT to
signal a FAULT condition, is nominally 7V VF. If desired,
this DESAT threshold voltage can be decreased by using
multiple DESAT diodes in series. If n is the number of DESAT diodes then the nominal threshold value becomes
VCE,FAULT(TH) = 7 V n x VF. In the case of using two diodes
instead of one, diodes with half of the total required
maximum reverse-voltage rating may be chosen.
HCPL-316J
VE
16
VLED2+
15
DESAT
14
VCC2
13
VC
12
VOUT
11
VEE
10
VEE
100 pF
MJD44H11 or
D44VH10
4.5
10
2.5
10 nF
MJD45H11 or
D45VH10
15 V
-5 V
Part Number
Manufacturer
trr (ns)
MUR1100E
Motorola
75
1000
MURS160T3
Motorola
75
600
UF4007
General Semi.
75
1000
BYM26E
Philips
75
1000
BYV26E
Philips
75
1000
BYV99
Philips
75
600
Power/Layout Considerations
Operating Within the Maximum Allowable Power Ratings
(Adjusting Value of RG):
When choosing the value of RG, it is important to confirm that the power dissipation of the HCPL316J is
within the maximum allowable power rating.
The steps for doing this are:
1. Calculate the minimum desired RG;
29
As an example, the total input and output power dissipation can be calculated given the following conditions:
ION, MAX ~ 2.0 A
VCC2 = 18 V
VEE = -5 V
fCARRIER = 15 kHz
Step 1: Calculate RG minimum from IOL peak specification:
To find the peak charging lOL assume that the gate is
initially charged the steadystate value of VEE. Therefore
apply the following relationship:
[VOH@650 A (VOL+VEE)]
RG =
IOL,PEAK
[VCC2 1 (VOL + VEE )]
=
IOL,PEAK
PO(BIAS) = steadystate power dissipation in the HCPL316J due to biasing the device.
PO(SWITCH) = transient power dissipation in the HCPL316J due to charging and discharging power device
gate.
ESWITCH = Average Energy dissipated in HCPL316J due
to switching of the power device over one switching
cycle (J/cycle).
fSWITCH = average carrier signal frequency.
For RG = 10.5, the value read from Figure 77 is ESWITCH
= 6.05 J. Assume a worstcase average ICC1 = 16.5 mA
(which is given by the average of ICC1H and ICC1L ). Similarly the average ICC2 = 5.5 mA.
PI = 16.5 mA * 5.5 V = 90.8 mW
PO = PO(BIAS) + PO,SWITCH
18 V 1 V (1.5 V + (5 V))
=
2.0 A
= 10.25 W
= 217.3 mW
= 126.5 mW + 90.8 mW
Step 3: Compare the calculated power dissipation with the absolute maximum values for the HCPL-316J:
For the example,
6
IOFF (MAX.)
0
-1
ION (MAX.)
4
3
1
0 20 40 60 80 100 120 140 160 180 200
Rg ()
Figure 76. Typical peak ION and IOFF currents vs. Rg (for HCPL316J output driving an IGBT rated at 600 V/100 A.
HCPL-316J fig 76
30
-2
-3
Ess (J)
50
100
150
200
Rg ()
Thermal Model
The HCPL-316J is designed to dissipate the majority of
the heat through pins 4 for the input IC and pins 9 and 10
for the output IC. (There are two VEE pins on the output
side, pins 9 and 10, for this purpose.) Heat flow through
other pins or through the package directly into ambient
are considered negligible and not modeled here.
Tjo
i4 = 60C/W
O9,10 = 30C/W
TP4
TP9,10
4A = 50C/W*
9,10A = 50C/W*
TA
HCPL-316J fig 78
31
= 110C
= 119C
Tji
= 115C
= 131C
The output IC junction temperature exceeds the absolute maximum specification of 125C. In this case, PCB
layout and airflow will need to be designed so that the
junction temperature of the output IC does not exceed
125C.
If the calculated junction temperatures for the thermal
model in Figure 78 is higher than 125C, the pin temperature for pins 9 and 10 should be measured (at the package edge) under worst case operating environment for a
more accurate estimate of the junction temperatures.
32
System Considerations
Propagation Delay Difference (PDD)
The HCPL-316J includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
dead time in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 62) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between
the high and low voltage motor rails, a potentially catastrophic condition that must be prevented.
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
0.1
F
VOUT
VLED1+
VEE
VLED1-
VEE
30 V
0.1 F
VC
FAULT
VE
0.1
F
0.1 F
30 V
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
HCPL-316J fig 60
HCPL-316J fig 61
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Data subject to change. Copyright 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0579EN
AV02-0717EN - May 21, 2008
IE
0.1
F
5V +
0.1
F
VIN+
5V +
IE
VIN+
30 V
0.1 F
0.1 F
30 V