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High Voltage
DC Bus
Main Battery Array
Low Power
Loads
14V DC Bus
12V Battery
Bidirectional
DC-DC
Converter
Supercap
Low
Power
Power
Loads
Train
I.
INTRODUCTION
II.
S3
is5
D3
D1
D5
NS
S.C.
S5
NP
vs
Vb
vp
R1
Ldc
D6
iL
NS
D2 Cr1
S2
S4
D4 Cr2
S6
is6
S1 ,S4
Ton1
S2 ,S3
S5/D5
S6/D6
Vb
Vp
Vb
Dc =
is5
Ia/2
Ia
iL
T
Fig. 3: S.C. charge mode operation waveforms (basically PWM control)
T
= on1
T
(1).
Es =
Ns
Vb
Np
(2).
S1
S2
Ddischarge =
T2
T
(4).
NT =
NP
Vb
=
N S VC _ max
(5).
Toph
Gate signal
S2
S3
S4
Vp
(3).
T /2
is6
Dcharge
Toph
Vb
Vb
Delay
D Q
Gate signal
S5
Secondary side
Transformer
Voltage Vs
Es
T/2
Fig. 4: S.C. charge mode operation waveforms (phase shift PWM control)
S5
Ton2
S6
vc
Vs
vc
is5
Ia/2
is6
Ia
iL
T
Fig. 6: S.C. discharge mode operation waveforms
TABLE I.
CHARACTERISTICS OF THE SPERCAPACITOR
Capacitance
340 F
Maximum Voltage
10.8 V
60 A
Maximum ESR
1.5 m
Energy Density
6.5 Wh/kg
5.5 kW/kg
Vg(S2)25V/Div
iL
10A/Div
is5
TABLE II.
CIRCUIT CONFIGULATIONS
Item
Symbol
Value
DC Source Voltage
Vb
50 V
Inductor
Ldc
60 H
Switching Frequency
Fs
60 kHz
Np:Ns:Ns
5:1:1
Crx
4.7 nF
III.
35 m
PERFORMANCE ANALYSIS
10A/Div
Vc2.5V/Div
4s/Div
iL
2A/Div
is5
2A/Div
Vc2.5V/Div
4s/Div
is5
10A/Div
Vc
5V/Div
2s/Div
Vg(S5) 10V/Div
is5
10A/Div
Vc
5V/Div
Vg(S1)Vg(S2)
2s/Div
vs110V/Div
is11A/Div
2s/Div
16
Vg(S)
14
12
without S.R.
10
with S.R.
vs110V/Div
8
6
is11A/Div
4
2
0
0
10
20
30
40
2s/Div
Vg(S1)Vg(S3)
vs110V/Div
is11A/Div
0.3
Duty=0.6
Duty=0.7
Duty=0.8
Duty=0.9
0.25
0.2
0.15
0.1
0.05
0
3
10
IV.
CONCLUSION
REFERENCES
2s/Div
[1]
[3]
[4]
vs110V/Div
is11A/Div
[5]
[6]
2s/Div