`timescale 1ns / 1ps

module counter99(
input clk,rst,
// output reg clkdiv=1'b1,
output reg [3:0] count1,
output reg [3:0] count2,
output reg [3:0] select,
input up_down,
// output reg [6:0] ssd1,
output reg [6:0] ssd);
// output reg [6:0] ssd2 );
reg s1,s2;
reg [6:0] ssd1; // to assign to individual seven segment displays
reg [6:0] ssd2;
reg clkdiv=1'b1;
initial begin
s1=0;
s2=1;
end
integer t=1'b0;
integer t1=1'b0;
always @ (posedge(clk))
begin
t=t+1;
if (t==25)
begin
clkdiv=~clkdiv;
t=1'b0;
//
s1=~s1;
//
s2=~s2;
end
end
always @ (posedge(clk)) // to toggle seven segments at avery very high speed
begin
t1=t1+1;
if (t1==2)
begin
t1=1'b0;
s1=~s1;
s2=~s2;
end
end
//assign clkdivo=clkdivi;
always @(posedge (clkdiv))
begin
if (rst==0)
begin
count1=4'b0000;
count2=4'b0000;
end
else
begin
if (up_down==0) begin
// UP COUNTER
count1= count1 + 1;
if (count1==4'b1010)

begin
count2=count2+1;
count1=4'b0000;
end
if (count1==4'b1001 && count2==4'b1001)
begin
count1=4'b0000;
count2=4'b0000;
end
end
if (up_down==1) begin
DOWN COUNTER
count1= count1-1;

//

if (count1==4'b1111)
begin
count2=count2-1;
count1=4'b1001;
end
if (count2==4'b1111)
begin
count2=4'b1001;
end
if (count1==4'b0000 && count2==4'b0000)
begin
count1=4'b1001;
count2=4'b1001;
end
end
end
end

always @ (count1,count2)
begin
case (count1)
4'b0000 :
begin
ssd1=7'b0000001;
end
4'b0001 :
begin
ssd1=7'b1001111;
end
4'b0010 :
begin
ssd1=7'b0010010;
end
4'b0011 :
begin
ssd1=7'b0000110;
end

4'b0100 :
begin
ssd1=7'b1001100;
end
4'b0101 :
begin
ssd1=7'b0100100;
end
4'b0110 :
begin
ssd1=7'b0100000;
end
4'b0111 :
begin
ssd1=7'b0001111;
end
4'b1000:
begin
ssd1=7'b0000000;
end
4'b1001 :
begin
ssd1=7'b0000100;
end
endcase
case (count2)
4'b0000 :
begin
ssd2=7'b0000001;
end
4'b0001 :
begin
ssd2=7'b1001111;
end
4'b0010 :
begin
ssd2=7'b0010010;
end
4'b0011 :
begin
ssd2=7'b0000110;
end
4'b0100 :
begin
ssd2=7'b1001100;
end

4'b0101 :
begin
ssd2=7'b0100100;
end
4'b0110 :
begin
ssd2=7'b0100000;
end
4'b0111 :
begin
ssd2=7'b0001111;
end
4'b1000:
begin
ssd2=7'b0000000;
end
4'b1001 :
begin
ssd2=7'b0000100;
end
endcase
if (s1==1 && s2==0) // to select the seven segment to display
// connected in common cathode configuration
begin
select=4'b1110; // last 7-seg ON
ssd=ssd1;
end
else if (s1==0 && s2==1)
begin
select=4'b1101; // Second last 7-seg ON
ssd=ssd2;
end
end
endmodule