TFT Design Flow

Silvaco provides a complete, well integrated simulation software for all aspects of TFT technology. Our TFT specific software
includes technology simulation, SPICE model extraction, interconnect parasitic analysis, SPICE circuit simulation, and traditional
CAD. TCAD Driven CAD approach provides the most accurate models to both device engineers and circuit designers.

ATHENA

CELEBRITY

ATLAS

SmartSpice

UTMOST

Fab or Test Lab

Measured Data

SmartSpice/Verilog-A

CLEVER

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ATHENA/ATLAS for Technology Simulation

TFT is an advanced device technology simulator equipped with physical
models and specialized numerical techniques to simulate amorphous or
polysilicon devices.
Sophisticated algorithms permits the device engineer to simulate general TFT
devices through to the next generation of high performance devices. Typical applications include:
Active matrix liquid crystal displays (AMLCD) used in large area
flat-panel displays
Electrical characterization of non-planar or multi-gate TFT devices
Static random access memory (SRAM) cells
Polysilicon single grain channel TFTs
Evaluating multi or single grain boundary effects
Evaluating influential parameters on carrier transport
Software packages for process simulation of TFTs are:
SSuprem4 simulates geometric deposition and etch, implantation
and diffusion
MC Implant enables simulation of TFT ion implant species such as
PH+, PH+2
DevEdit allows users to draw the geometry of simple TFT structures
and add analytical doping profiles

Shown here (above and lower left) are a typical back-gated amorphous
silicon TFT, a co-planar polysilicon TFT, a dual gated TFT and a high performance TFT including LDD regions.

TFT specific device simulation features in ATLAS/TFT include:

Planar and non-planar device modeling implementing
advanced models focusing on defects and defect states
Mobility models
Trap assisted tunneling and band-to-band tunneling models
Poole-Frenkel effect models to simulate phonon assisted
tunneling at low electric fields
Impact ionization
Ability to combine TFTs into a circuit environment in MixedMode
3D simulation in TFT3D
Ability to combine TFTs into the self heating effect with Giga

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ATLAS/TFT Module
In-house developed density of states occupied within the
materials bandgap can be easily implemented within ATLAS
using an ANSI C-Interpreter. Shown here are typical expression for the DOS along with their corresponding pictorial
representation.

Simulation of a TFT used in AMLCD technologies shown in green plotted on top of actual
real time experimental data shown in red. Excellent agreement is clearly seen.
Typical expressions of density of states are shown here. These can be implemented using the
C-Interpreter module with ease.

Continued simulation showing leakage current properties. It can be seen that by

including the Poole Frenkel effect the leakage current has been increased with an
improvement in the simulation as shown in blue.

Real time device measurement and simulations of actual active

matrix liquid crystal display TFT device technology is shown here.
Excellent agreement is clearly seen. By including advanced tunneling models including coulombic potential well lowering using
the Poole Frenkel effect improvements between the simulation
and measurement of the leakage current is observed.

Shown here is the temperature distribution through the device channel using the self heating
effect within Giga. Temperature field lines are also seen to extend deep into the SiO2 region
accurately characterizing a real device.

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ATLAS/TFT/Luminous Optical Simulation

Shown above is the back light incident beam on a TFT device with corresponding
photogeneration rate distribution.

The corresponding actual ray trace from exterior to interior is also shown.

TFT module can be coupled with Luminous to investigate the optical response due to incident light. Luminous device simulator can model
light absorption and photogeneration in planar and in this case non-planar semiconductor devices using ray tracing. The photogeneration is
shown here due to an incident back light illumination of a typical TFT device. The corresponding ray trace of the actual light is also shown.
It is clear complex refraction occurs throughout the device with accurate calculation of photogeneration.

Transient simulation showing TFT response to various gate and drain voltage pulse trains.
Shown here is the off current dependence on the incident beam intensity. As the intensity is
increased the off current is also seen to increase.

Typical electrical investigations can also be easily performed to investigate such effects as variation of beam intensity or response time.
Shown here is the off current dependence on the incident beam intensity which is seen to increase as the intensity is increased. In
addition a transient simulation is shown giving the user the ability to investigate intricate response switching times.

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SmartSpice - Circuit Simulator

TFT circuits pose unique problems for reliable and accurate circuit
simulation. SPICE-like programs are not designed to handle negative conductances forcing designers to simulate circuits for only
positive gate voltages. SmartSpice however can accept any bias
conditions resulting in accurate and reliable TFT simulations.
SmartSpice Analog Circuit Simulator delivers the highest performance and accuracy required to design complex analog
circuits, analyze critical nets, characterize cell libraries, and
verify analog mixed-signal designs. SmartSpice is compatible
with popular analog design flows and foundry-supplied device
models. The four supported models for TFT device simulation
allow accurate modeling of TFT devices over wide temperature
ranges and with physically based capacitance models provide
for accurate time domain simulations. SmartSpice coupled with
Gateway Schematic Editor delivers a powerful easy to use circuit
simulation platform.

Gateway Schematic Editor showing circuit diagram for a TFT arrangement.

Gateway Schematic Editor is the front-end of the Analog/Mixed Signal/

RF IC Design Environment. It is tightly integrated with Silvacos circuit
simulation, digital simulation, layout, DRC, ERC, LVS, and parasitic extraction tools. Seamless integration with SmartSpice Circuit Simulator that
creates an interactive design environment with behavioral models,
cross-probing, wave form display, and analysis.
Shown here is a TFT pixel arrangement using Gateway Schematic Editor
coupled with SmartSpice Analog Circuit Simulator. Various simulations on
such an arrangement can be easily performed.

TFTs are also used for logic circuits around the display area. SmartSpice can simulate complex circuits such as this decoder example.

A more advanced example is a 3-Bit-Decoder encompassing

a complete TFT arrangement used in logic circuits surrounding a display area. The response to several transient pulses
can easily be investigated.

Pixel switching in a 4000 cell array using SmartSpice.

TFT pixel array is also shown coupled with parasitic elements. This
can be extended to investigate advanced circuits such as pixel
switching in a 4000 cell array.
Circuit of a TFT pixel with parasitics.

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SmartSpice/Verilog-A
SmartSpice Verilog-A Interface provides designers with an easy to use, comprehensive environment for the design and verification of complex analog and
mixed-signal circuits. It provides an executable specification for design integrity
and powerful optimization capabilities for achieving those specifications.

SmartSpice Simulation using Verilog A.

Verilog-A has the most capability of any behavior modeling software for circuit and device as a part of Verilog AMS 2.2 based on IEEE1364). Even if you
find unknown behavior device ( i.e Liquid Crystal and photodiode ) You can
have behavior modeling using verilog-A and do circuit simulation.

UTMOST III - Parameter Extraction

UTMOST III is a completely integrated software package to provide
for automatic data acquisition, parameter fitting and extraction,
optimization, simulation and model validation.
UTMOST III, SPICE parameter extractor and SmartSpice, circuit
simulator, support the following models:
LEVEL=35,
LEVEL=36,

RPI Amorphous model

RPI Polysilicon model

A typical model optimization window where measured data is fitted to a selected model.

Custom IC CAD

CELEBRITY for Layout and DRC

CELEBRITY products provide complete layout and verification needs for TFT circuit and layout designers. The CELEBRITY line of
products include the group of Expert and Guardian DRC/LVS/LPE.
Expert Layout Editor enables mask designers to achieve maximum density and performance in analog and digital layouts. Experts highproductivity design environment offers fast layout viewing, full editing features, large capacity, and powerful scripting for automation
with parameterized cells (Pcells).
Guardian DRC/LVS/LPE Physical Verification products provide interactive and batch mode verification of analog, digital, and mixedsignal IC designs. Seamlessly integrated with Silvaco schematic capture and layout editor, these tools efficiently perform design rule
checks (DRC), electrical rule checks (ERC), and layout vs. schematic (LVS) comparison.
Key features include:
Hierarchical design
Multi-million transistor layouts
Arbitrary shapes
Full chip and local DRC
Script language
GDS-II and CIF import/export
Optimized automated routing
Support for all angles, 45 degrees and 90 degree
objects
Interactive and batch mode operations
Client-server design and library management
Seamless integration with Expert Layout and Gateway
Schematic Editors to provide a complete entry-toverification design flow for analog and mixed-signal
designs.
Productive layout environment for analog, RF, microwave, and digital layouts with integrated DRC/LVS/
LPE for interactive or batch operation

Typical cell array layout designed hierarchically in Expert.

Shown here is the hierarchical structure of a

several thousand TFT pixel arrangement. Such
an arrangement is well characterized with Expert.
A simplified view is further shown taken using a
cross section view of a reduced area. A detailed
view of individual call layouts is clearly seen.

Cross section viewer using Cross section view.

I nterconnect M odeling

Interconnect Parasitic Extraction from Layout

Accurate extraction of the interconnect parasitics is vital for successful TFT
circuit design. In pixel arrays, long overlapping metal tracks are used. To accurately design TFT logic circuits, extraction of interconnect delays is important.
TFT technology presents special challenges because of the lack of substrate
ground plane and the presence of multiple materials.
CLEVER solves the above problems by performing physical simulation of interconnect geometry and extracting resistance and capacitance from a 3D structure. CLEVER Physics-based Parasitic Extractor uses 3D field solvers to directly
convert the mask data of a cell and relevant process information into a SPICE
netlist, back annotated with the most accurate interconnect capacitance and
resistance parasitics. This direct, one step process completely removes inaccuracies resulting from traditional, rule-based parasitic extractors.
CLEVER includes features for:
Conformal deposition
Lithography
Multiple metals
Multiple dielectrics
User-defined material permittivities and conductivities
Ability to locate active TFT
transistors and apply correct
connectivity

3D geometry of a TFT pixel created in CLEVER.

CLEVER simulates the 3D geometry

(above) of a TFT pixel including active
device and interconnect based on the
original pixel layout. From this accurate
representation of geometry, the parasitic
resistance and capacitance are calculated and saved to a SPICE netlist for further
circuit simulation.
Original pixel layout.

3D TFT pixel structure.

2D cutplane through a 3D TFT pixel structure showing potential distribution for an interconnect.

MaskViews is integrated with Silvaco products.

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