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A Course Material on

EC6504 MICROPROCESSOR AND MICROCONTROLLER

By

Mr. P.MALK MOHAMED SULAIMAN MALIK


ASSISTANT PROFESSOR
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
M.E.T OF ENGINEERING COLLEGE

UNIT I
(THE 8086 MICRO PROCESSOR)
Introduction to 8086 Microprocessor architecture Addressing Modes Instruction
set and assembler directives Assembly language programming Modular programming
Linking and Relocation Stacks Procedures Macros Interrupts and interrupts service
routines Byte and string manipulation.

Introduction to 8086 microprocessor:


It was launched during the year 1978.
Actually the evolution of microprocessor is
Intel

4004

(4 bit microprocessor)

8085

(8 bit microprocessor)

8086

(16 bit microprocessor)

80286
80386
80486
Pentium
Pentium Dual core
i3
i5
i7
When probing about microprocessor 8086,
Definition of Microprocessor:
It is single chip CPU. Where CPU contains
i.

Memory unit (RAM)

ii.

Arithmetic logic unit (ALU)

iii.

Control Unit

8086 has got HMOS technology.


Advantages:
All internal register of 8086 is 1 bit and it has 16 bit data line so it is called 16
bit microprocessor.
From In port and Out port read and write 16 bit data
It has 20 address lines. So it can map 220-1
The frequency is
i.

10 MHz

8086 1

ii.

8 MHz

8086 2

It runs under Minimum and Maximum mode


Minimum Mode:
It has only one 8086 microprocessor
Maximum Mode:

It has more than one 8086 microprocessor

Question and Answers


2 Mark questions:
1. Differentiate between 8085, 8086?
Ans:
8085
i.

8 bit processor

ii.

8086
i.

16

bit

processor
Address ii. 19 Address lines

16
Lines

2. Define Microprocessor?
Ans:
It is single chip CPU where as CPU contains
i.

Memory unit (RAM)

ii.

Arithmetic Logic unit (ALU)

iii.

Control Unit

3. Describe the frequencies of 8086?


Ans:
i.

10 MHz

8086 1

ii.

8 MHz

8086 2

4. Differentiate Min mode and Max mode?


Ans:
Min Mode
It has only one 8086 micro processor

Max Mode
It has more than one 8086 micro
processor

Essay Questions:
1. Describe the evolution of microprocessor?
Ans:
Intel 4004 (4 bit microprocessor)

Objective Questions:
i. 8086 was launched during ___________
i. 8086

ii. 1978

iii. 1986

ii. Intel 4004 is _________ microprocessor


i.

4 bit

ii. 8 bit

iii. 6 bit

iii. The another name for Main memory is _____________


i.

RAM

ii. ROM

iv. 8086 has got ____________ technology


i.

CMOS

ii. HMOS

v. 8086 is ____________ bit microprocessor


i. 8 bit

ii. 16 bit

vi. The address lines 20 can map:


i. 220 1

ii. 220 + 1

vii. The frequency of 8086 1 is _______________


i. 10 MHz

ii. 8 MHz

viii. The frequency of 8086 2 is ___________


i. 10 Mhz

ii. 8 MHz

ix. Min Mode needs ____________


i. Only one 8086

ii. Two 8086

x. Max Mode needs _____________


i. Only one 8086

ii. More than one 8086

Result Analysis
1. ii

2.i

3.i

4.ii

5.ii

6.i

7.i

8.ii

In objective answers
If your score greater than 8 then only you can go to Day 2.

9.i

x.ii

Architecture of 8086
8086 has 20 address lines and 16 data lines. Due to the presence of 16 data lines it is
called 16 bit microprocessor. So 8086 has in port (or) out port has 16 bit.
The general block diagram of 8086 is,
We know microprocessor is a single chip CPU. CPU contains
i.

Memory (RAM)

ii.

ALU

iii.

Control Unit

Keeping the above three units it refers 16 bit microprocessor 8086.


8086 has two logical units
i.

Execution unit

ii.

Bus Interface Unit

The simplified 8086 Architecture has

Execution Unit

DATA,
IR
PRINTER

ALU
FLAGS

BIU

SEGMENT REG
AND
INSTRUCTION
POINTER

&

I
N
T
E
R
N
A
L
B
U
S

Timing and
Control

Bus Control Logic

Instruction Queue

So analysing of CPU it contains memory. Memory is in the form of register (On chip
RAM)
The register:
The another name for GPR is scratchpad register
8086 Contains
Address register
Segment register
Data register
Flag register
1. The scratchpad registers:
X Indicates 16 bit register. There are four 16 bit GPR (General Purpose
register)
Ax, Bx, Cx, Dx
Ax 16 bit register is bifurcated.
AH and AL which is two light bit register. This AH, AL or AX is called
accumulator which is used vehemently in arithmetic operation.

Question and Answers


2 Mark questions
1. 8086 has got how many address lines and how many data lines?
Ans:
8086 has 20 address lines and 16 data line
2. 8086 has what are the two logical units
Ans:
i. Execution Unit
ii. Bus interface unit
3. What are the 4 types of 8086 register?
Ans:
Address register
Segment register
Data register
Flag register
4. What are the 4 sixteen bit GPR?
Ans:
AX
BX
CX
DX
Essay questions:
i.

Draw the basic block diagram of 8086?


Ans:
Execution Unit

BIU

Objective type questions:


i.

8086 has _____________ address lines


i. 16

ii. 20

ii. 8086 has ______ Data lines


i. 8

ii. 16

iii. 8086 is called 16 bit processor because of ___________


i. Address lines

ii. Data lines

iv. The two logical units in 8086 __________


i.

Execution Unit, I/O Unit

ii.

Execution Unit, Bus Interface unit

v. The another name for GPR is _________


i. Register

ii. Scratch pad register

vi. 8086 contains __________ register


i. 2

ii. 4

vii. AX, DX, CX, DX are called


i. GPR ii. Special register
viii. AX is ___________ bit register
i. 16 bit

ii. 8 bit

ix. AX is bifurcated into _________


i. AH, AL

ii. CH, AH

x. The another name for AX is _________


i. Flag

ii. Accumulator

Result Analysis
1. ii

2. ii

3. ii

4. ii

5. ii

6. ii

If your score greater than 80 % go to Day III

7. i

8. i

9.i

10.ii

Regarding register the following info.


AX
BX
CX
DX

AH
BH
CH
DH

AL
BL
CL
DL

Accumulator
Base register
Count register
Data register

BX, CX, DX are temporary storage and also for arithmetic operation. It can be used as
BH, BL, 8 bit or BX 16 bit
The next is pointer and index register
SP
BP
SI
DI

Stack pointer
Base pointer
Source index
Destination index

The another name of above register is Address Register. It helps in addressing modes
SP points top of stack (TOS)
BP points any location of stack
SI & DT: For addressing
Flag register:
It is a 16 bit register
7 bit Un used
6 bit Conditional flags
3 bits Control flag
Conditional flag has:
i. Carry (CF)

ii. Zero (ZF)

When addition overflow comes zero flag.


After the arithmetic operation if result is zero.
iii. Parity flag
if even number is the counter of one

iv. Sign flag:


Check the MSB if
1 Negative
0 Positive
v. Auxiliary carry flag
after the 4th bit addition if carry comes
vi. Overflow flag
MSB (8 bit or 16 bit) over flow
vii. Control flags:
it has
i.

Trap flag: Step by step debug

ii.

Interrupt flag: Enable interrupt

iii.

Directional flag: String operation

Arithmetic logic unit:


It does arithmetic and logic operation.

Question and Answers


2 Mark questions:
1. What are the four GPR in 8086?
Ans:
AX AH AL
Accumulator
BX BH BL
Base register
CX CH CL
Count register
DX DH DL
Data register
2. What are the pointers and index registers in 8086?
Ans:
SP
BP
SI
DI

Stack pointer
Base pointer
Source index
Destination index

Essay question:
1. Explain 8086 flag register?
Ans:
16 bit representation.
Objective type questions:
i.

The another name for AX is _______


i. Auxiliary

ii.

ii. Accumulator

The another name for BX is ________


i. Base register

iii.

ii. No such register

The another name for CX is _________


i. Counter register

iv.

ii. No such register.

The another name for Data register is _______


i. DX

ii. AX

v.

The two pointers in 8086 _______


i. SP, BP

vi.

ii. SI, DI

The two index register in 8086 _______


i. SP, BP

vii.

ii. SI, DI

Flag register in 8086 is __________


i. 8 bit

ii. 16 bit

Result Analysis
1. ii

2. i

3.i

4.i

5.i

6.ii

7.ii

If your score greater than 6 is allowed to day 4

In Architecture of 8086 we had bus interface unit


Performing address calculation, pre fetching instruction for queing and sequence one by
one
i.

The instruction queue:


It has 6 bytes of instruction in queue in FIFO.

ii.

Memory segmentation:
it has 20 bit address line.
All register are only 8 bit or 16 bit for 20 bit segments are used segments are

various size of memory.


20 Address lines in 8086. So it can map 220 addresses.
Memory divided by the following four segments
Data Segment:
Logical address to physical address mapping is done. The flow (mechanism) is
Physical address = Base address + OFF set
Code segment:
It points instruction by instruction pointer
iii.

The stack segment and stack pointer:


Stack is consequently storing data in same data type in a special way. It performs
PUSH and POP operation. Actually it picks the data LIFO
Stack pointer points the top of stack.

Extra segment:
It uses upper 16 bits of base address in ES
Advantage of segment:
Map 220 address lines
Address memory is relocatable

Referring above points the detailed architecture

BIU

EU

GPR

AH

AL

BH

BL

CH

CL

DH

DL

ES

SP

CS

BP

SS

SI

DS

DI

IT

16 bit
bus
Temporary
Register
ALU
Flags

Address
bus

1
EU
Control
System

Instructor
Queue
2 3 4 5

Bus
Control
logic

8086 Flag register is

P8

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0
Carry flag
Unused
Parity flag
Unused
Auxiliary carry
flag

Overflow flag

Unused
Zero flag

Direction flag

Sign flag
Tref flag
Interrupt flag

Question and Answers


2 Mark questions
1. Define physical address?
Ans:
Physical address = Base Address + OFF set
2. What are the operation for stack?
i. PUSH

ii. POP

LIFO operation.
Essay questions:
1. Explain the architecture of 8086?
Ans:
Day 2, Day 3, Day 4
2. Draw the flag register of 8086?
Objective type questions:
1. BIU has ________
i. No operation

ii. Address

Calculation, Pre fetching instruction


2. The instruction queue has ______ bytes of instruction in queue
i. 6 bytes

ii. 4 bytes

3. ________ it points instruction


i. BP

ii. Instruction point

4. _________ continuous consequently storing same type data is


i. Stack

ii. Queue

5. Stack performs _______


i. LIFO

ii. FIFO

Result Analysis
1. ii

2. i

3. ii

4. i

5.i

If your score greater than 4 is allowed to go day 5

Addressing Modes (8086)

Direct
Address
Mode

Indirect
Based
Address Address
Mode
Mode

Based
Indexed
Address
Mode

String
Address
Mode

i. Direct Addressing:
consider the instruction MOV AL, [000H]
the content is accessed by
2000

Data Segment X 10
100
0

10,00
0

12,000

1A

I/O ports
accessing
by
Address
Mode

Stack
Memory
Address
Mode

Now AL contains 1 A
Actually in 8086 has 4 segments. In that data segment always multiplied by 10
ii. Register indirect:
consider the following instruction
MOV BX, (CX)
Here indirect says content of content

X 10
DS

1000

10,00
0
1A

+
12,00
0
CX

1B

2000

BX

1B

1A

iii. Base plus indexed address mode:


analysis the following X
instruction
10
MOV
1000(BX + DI)
DS CX,

10,00
0
+

BX

12,00
0

2000
+

DI

1F

3000
15,00
0
CX = I F I F

1F

Here data segment calculated then base & index content added finally that contents data is accessed.
4. Register relative addressing:
By considering the following instruction
MOV CX,

[BX + 004H]
10
X

So
DS

50,000
5000

51,004
BX

1000

10

4
CX
=

20

20

10

5. Base, Relative plus index addressing:


By considering the following instruction
MOV AL [ BX, SI + 04H]
Hence

BX

1000
2,000
+

SI

1000
+
20,000

DS

2000

04

1F
22,00
4
AL = 1 F

1F

22,00
4

Here always consider data segment DS content multiplied by 10. The remain values added. The result points the address of result.
6. String Addressing Mode:
Consider the follows instruction
MOV S

BYTE

7. I/O ports accessing by address mode:


The meaning of port means carry from that either in port or out port
i.

Direct
Consider the instruction
IN AY, 10 H Device number 10 give the data to AY.

ii.

Indirect:
Consider the instruction
IN

AL, DX Content of DX is the device number from that give the data to AL

8. STACK memory addressing mode:


It has two instruction
i.

PUSH:
Enter the data on stack

ii.

POP:
Access the data LIFO method from stack.

Question and Answers


2 Mark question
1. What is direct addressing mode?
Ans:
The content of operand is accessed.
2. What is indirect addressing mode?
Ans:
The content of content in operand is accessed.
3. What is base plug indexed addressing mode?
BX + DI
4. What is register relative addressing mode?
Ans:
Content of Base + Offset
5. What is port?
Ans:
Port means carry. It is used to read by In port write OUT port.
Essay question
1. Discuss the different addition modes of 8086?
Ans: Day 5

Objective questions:
1. The main aim of addressing mode is _______
i.

Map Memory efficiently

ii.

Map memory in efficiently

2. MOV AL, [2000 H] is _________


i.

Direct Addressing mode

ii.

In direct addressing mode

3. MOV AY, (CX) is ___ addressing mode


i.

Indirect

ii.

Register Indirect

4. MOV CX, [BX + DI] is ________


i.

Based addressing mode

ii.

Base plug indexed addressing mode

5. MOV CY, [BX + 004A] here 004H is _______


i.

Offset

ii. Non offset

6. MOV AL, [BX, SI + 04H] is ________ addressing mode


i.

Base, relative plug indexed addressing mode

ii.

Based addressing mode

7. In AY, 10H is ______ addressing mode


i.

Input port

ii. Out put port

Result analysis
1. i

2. i

3.i

4.ii

5.i

6.i

If your score is greater than 6 go to Day 6

7.i

Instruction Set
(8086)

Data
Moveme
nt MOV

Add sub
compare

Multiply
DIV

BCD &
ASCII

Logic
Instructio
n NOT
DAA

ADD

MUL

MOV

ADC

MOV

INC

IMU
L
DIV

MOV

SUB

XOR

MOV

SBB

TES
T

DEC
NEG
CMP

DAS

String
Compar
e REP
SAL

SHIFT &
ROTATE

AND

SHR

OR

SAR

MOV
S
CMP
S

Jump

CAL
L
RET
JUM
P
JCON
D

MC
Interrupt
CONTRO
Instructio
L
n
STC
INT

CLC
CMC
STD
CLD

INT
O
RET

I. Data Transfer (8086 instruction)


i.

MOV

BX,

AX

Here the general syntax is


MOV

dstin, source

Actually in intel MOV

dest, src

Hence from AX the data transferred to BX

1F
AX

1A

1F

So

BX

1A

Similarly data transfer instruction has got five high frequency addressing modes
ii. PUSH:
in stack PUSH value enter the data when PUSH stack pointer Top of stack
decremented by one. But here in conventional maths the address will be incremented.
PUSH BX is the example
iii. POP
in stack POP value accessed from the data. When POP Top of stack incremented
by one. But here in conventional maths the address will be decremented.
iv. XCHG:
Exchange
X CHG

BX, CX

Here BX data and CX data are swapped

II. Arithmetic instruction:


i.

ADD
Add

desn, src

Here by intel
ADD AX,

BX

AX AX + BX
ii.

ADC: (Add with Carry)


For example
ADC DY, BX
So
DX DX + BX + CY

iii.

INC BX
The BX will be incremented by 1.

iv.

2 eight bit addition


For example
AX

AH

AL

ADD AL, BL
AL (AL) + (BL)

v.

(AL) 1

(BL)

DAA: Decimal adjust accumulator


III. Subtract instruction:
i.

SUB

AX, BX

So

AX AX BX

RESULT

ii.

SBB

DX, BX

D DX BX Borrow
iii.

DEC

BX:

The BX value decremented by 4.


iv.

NEG AL:
AL value is ones complement

AL

1100 1100

NEG AL
0011 0011

v.

CMP BX
It is nothing but
SUB

AX, BX

DAS:
Decimal after sub
AL

0010

0011

CL

0101

1000

Question and Answers


2 Mark question
1. What is data transfer instruction?
Ans:
The data transferred from one place to another
Eg. MOV

AX, BX

2. What is stack transfer instruction?


Ans:
i.

PUSH to transfer the data to inside the stack

ii.

POP to take the data to outside of stack

3. What for XCHG instruction meant for?


Ans:
Exchange the registers BX, CX. Both are swapped
Eg:
XCHG BX, CX
4. What add instruction?
Ans:
ADD AX, BX
So

AX (AX) + (BX)

5. What is ADC instruction?


Ans:
ADC DX, BX
D (DX) + (BX) + cy carry
6. What INC BX?
The BX content incremented by 1.
7. What is SUB instructin?
Ans:
SUB

AX, BX

So
AX (AX) (BX)

8. What is SBB DX, BX meant for?


DX DX BX Borrow
9. How to computer 1s complement?
Ans:
NEG AL
Objective question
1. For intel MOV BX, CX which is source _________ which is destination _________
Ans:
i. CX, BX

ii. BX, CX

2. For entering & retrieving the stack operations are ______, ________
i. PUSH, POP

ii. POP, PUSH

3. XCHG meant for ________


i. Interchange to register
ii. clear the accumulator
4. ADC meant for ________
i. ADD with carry

ii. ADD with complement

5. SBB meant for ______


i. SUB with borrow

ii. No such instruction

6. NEG AL meant for ________


i. 1s complement

ii. 2s complement

Result Analysis
1. i

2.i

3.i

4.i

5.i

6.i

III
a. Multiplication
MUL AX dest,

BX src

It is
AX

0002

BX

0002

AX

Similarly we can say


I MUL also
And also
MUL BX is some as previous instruction.
b. Division
DIV

AX,

BX

Quotient in AX
Remainder in BX
DIV

AX,

BX

AX

0004

BX

0002

AX =

0005

BX =

0000

0004

IV. Logical operation: (Pre for 8 bit data)


i.

NOT CL
CL 1100 1100
CL = 0011 0011

ii.

AND:
Actually AND is
X

Lamp

X
0
0
1
1

Y
0
1
0
1

AND AL,

Lamp
0
0
0
1

BL

For example
AL

1A

0001 1010

BL

0A

0000 1010

Result in AL =

0000 1010

iv. OR operation:

in logical

Y
Lamp

X
0
0
1
1

Y
0
1
0
1

Z
0
1
0
1

OR:

OR

AL

0000 1010

BL

1010 0000

AL, BL =

1010 1010

AL 1010

1010

iv. XOR:
when the inputs are different output is one
Considering the above

example
XOR AL, BL

0000 1010
1010 0000

1010 1010

Question and Answers


2 mark question
1. Give instruction in 8086 for multiplication
Ans:
MUL AX, BX
AX AX * BX
And also
IMUL for integer multiplication.
2. Give instruction in 8086 for division?
Ans:
DIV

AX, BX

After division
AX

quotient

BX

Remainder

3. What are the four logical operation?


i.

NOT

ii.

AND

iii.

OR

iv.

XOR

Objective questions:
1. In Intel MUL AX, BX which is source and destination

i. AX src BX destn
ii. BX src

AX destn

2. In DIV AX, BX which is quotient and which is remainder


i. AX quotient

BX remainder

ii. No such instruction


3. NOT CT
i. 1s complement ii. 2s complement
4. Logical AND:
i. Bit wise multiplication

ii. Natural multiplication

5. Logical OR:
i. Bit wise addition

ii. Natural addition

Result analysis:
1. ii

2.i

3.i

4.i

5.i

if your score is equal to 5 you can go to day 8

V. Shift and rotate


i.

Shift:
SHR

So one bit shift right is divide by two. 2 bit shift right is divide by 4. 3 bit is divided by
8
Similarly
One bit shift left is multiply by two. 2 bit shift left is multiply by 4. 3 bit shift left is
multiply by 8.
ii.

Rotate:
i.

RAL:

Rotate left through carry

iii. RAR:
Rotate right through carry

Question and Answers


2 mark questions
1. What are the two operation in shift?
Ans:
Shift right
Shift left
2. What is the arithmetic operation happens in shift?
Ans:
Shift right one bit is divide by two.
Shift left one bit is multiply by two
3. What is the command for rotate?
i.

RAL, RAR

VI. Call Instruction:


It is near, for near intra segment far inter segment
1. JMP:
Unconditional jump
JMP

1000

2. J (Conditional)
JNZ

(Jump non zero)

JZ

(Jump zero)

JNC

(Jump no carry)

JC

(Jump carry)

JP

(Jump positive)

VII. Processor control instruction:


i.

STC:
Set the status in flag carry is 1

ii.

CLC:
Reset the carry flag to zero

iii.

CMC:
Complement carry flag

iv.

STD:
Set direction flag

v.

CLD:
Reset to direction flag to zero

VIII. Interrupt instruction:


INT

(0 255 Type)
IX. String instruction:
i.

REP

CX = 0

ii.

MOV S

BX, CX

iii.

CMP BX,

CX

Question and Answers


2 Mark questions
1. What are two segment calling?
Ans:
Near

intra segment

Far

inter segment

2. What are the two jump?


i. Unconditional jump
JMP

1000
ii.

J (Conditional)

JNZ

(Jump non zero)

JZ

(Jump zero)

JNC

(Jump no carry)

JC

(Jump carry)

JP

(Jump positive)

3. What are the processor control instruction?


Ans:
i.

STC:

ii.

CLC:

iii.

CMC:

iv.

STD:

v.

CLD:

Essay question:
1. Explain instruction set of 8086?
Ans:
Day 6,7,8,9

Objective type question:


1. What are two calling procedures ________
i. Near, far

ii. None

2. The jumps are _______i. Conditional, unconditional


3. MOV S

ii. No such

BX, CX is _________

i. String movement

ii. String complement

Result Analysis:
1.i

2.i

3.i

4.i

5.i

6.i

If your score greater than 7 go to day X

7.i

8.i

(i)

ALIGN

(ii)

ASSUME

(iii)

CODE (Instruction Segment)

(iv)

DATA
DB

Define byte

BW

Define word

DD

Define double

End of program

DQ
DT
(v)

DUP

(vi)

END

(vii)

EQV

(viii)

EXTRN

(ix)

GROUP All segments of same data type

(x)

Label

(xi)

MACRO Open sub routine END

(xii)

Name of each module

(xiii)

OFF Set

Question Answers
Essay question
1. Explain the assembler directives (pseudo codes) in 8086?
Ans: Day 10

Modular Programming
For example by considering a big task is divided into small sub tasks (modules)
execute paralelly and integrate the output
Program
modules

Sub module 1

Sub module 2

...
..

Sub module n

output

Different assembly files are tested individually but they have to be linked together. For
successful linking and execution
Different modules that together solution may be in different code segments
Depends on permission the data is shared by different modules.
Label can be inter segment also
For that the following assembly directives are
1. PUBLIC:
It shares data different modules. It is called PUBLIC.
Example 1:
PUBLIC num1, num2, num 3
(or)
PUBLIC num1
PUBLIC num2

PUBLIC num3
Example 2:
Sharing procedure
PUBLIC mult
2. EXTRN:
If you want to share initialize EXTRN
Eg 1:
EXTRN

name 1: type

Password checking:
Stored password (PW1)
Entered second password (PW2)
Password accessed PUBLIC in module
Now check the matches without echo

Questions and Answers


2 mark question:
1. Define modular program?
Ans:
Divide a big task into so many sub tasks and executed parallerly.
2. What is the assembler direction PUBLIC?
Ans:
It shares data in different modules.
3. What is the assembler directive EXTRN?
Ans:
If you want to share initialize EXTRN

PROCEDURES
In C, or C++ flashes about function. Similarly a sub task repeatedly occurred we
elicited that named procedure.
A main program calls different procedure
Main Program
.....
.....
CALL ABC
.....
.....
CALL BCC
.....
.....
CALL CCD
.....
.....
END
But this example only one procedure called repeatedly
Main Program
.....
.....
CALL ABC
.....
.....
CALL ABC
.....
.....
CALL ABC
.....
.....
END
This ABC sub procedure can be in main which is called near procedure.

This ABC sub procedure can be in from other places for procedure.
So near is intra
Far is iner
IP (Instruction Pointer) will be pointing to the next instruction in the main
program.
i.
5.2.1

While returning IP uses next of call

Writing a procedure:
While execution
CALL ABC
.
.
.
PROC ABC NEAR
.
.
RET

I.

Call and Return instruction


DIRECT CALL
It directly jump instruction
Indirect CALL
CALL BX
BX contains some value. There it will jump. The reason is calling content of
content.

II.

Intersegment or far call


Direct for Call:
A far call is an intersegment call.
Indirect far call:
Content of content calls an intersegment call.

III.

The RET instruction


When a procedure is called the current value of IP is pushed on to the stack.

RET n

From poping stack with n time that value returns.


RET 3
1013
1012
1011
1010

POP 3 so
1010 address
It returns
IV.

The use of the stack in procedure calls.


Stack meant for saving return address.
MULTI

PROC

NEAR

USES

DX

MUL

BX

MOV

DX, 4500 H

ADD

AX, DX

ADD

AX, DX

MOV

CX, 5000 H

ADD

AX, CX

CX

RET
MULTI

END
END

V.

Parameter passing mechanism.


a. Passing parameter through register:
A, B, C

Values

DATA
A

DB

10

DB

05

DB

15

. CODE
. START UP
MOV BL, A
MOV CL, B
.
.
. EXIT
NTH TERM AP

PROC

NEAR

MUL CL
ADD BX, AX
RET
NTH TERM AP

END P

END
b. Passing parameter through memory:
. DATA
N

WORD

0009

NUMBER BYTE 10, 20, 30, 40, 50, 60, 70, 80, 90
. CODE
. START UP
c. Passing parameter through stack
. MODEL
. STACK 10 H
. DATA
A

DW

0987 H

DW

0012 H

RESULT
. CODE
. START UP

DW

PUSH A
PUSH B
.

Question and Answers


2 Mark question
1. Define procedure?
Ans:
A sub task repeatedly occurred we elicited that named procedure.
2. What is near and far procedure?
Ans:
The sub procedure can be in main which is called near procedure.
But the ABC sub procedure can be in from other places far procedure.
So
Near is intra
Far is inter
3. What is the instruction execution in instruction pointer?
Ans:
Instruction pointer (IP) points the next instruction in the main program.
4. Define CALL and RET instruction.
Ans:
CALL BX
BX contains some value then it will jump
Ret returns to main. When a procedure is called the current value of IP
is pushed on to stack.
RET n
From popping stack will n time that value returns
RET 3 or POP 3 are same
1013
1012

1011
1010

Essay question:
1. Explain above procedure.
Ans: Day XII
2. Discuss different parameter passing mechanism in procedure?
Ans:
i.

Passing parameter through register

ii.

Passing parameter through memory

iii.

Passing parameter through stack

In the concept of subroutine there is open subroutine and closed sub routine. Close sub
routine is like function and it returns value. But open subroutine it wont return a value
but passes parameters. Wherever the open subroutine called it is inserted on that place.
The another name for open subroutine is MACROs
Example 1:
Writing a Macro the general format of MACRO is
MACRO NAME MACRO [Parameter List]
INSTRUCTION
. (BODY)
.
END M
For example
. MODEL SMALL
. CODE
. START UP
. ENTR MACRO
MOV AX, [1000]

Macro definiton

ADD AX
END M
MACRO ENTR
EXIT
END
A some number of statements repeatedly occurring. For making programmer easy first
the series of line named. Whenever they are called in main the macro routine inserted so
no jump, return work SHA MACRO & Arg 1 & Arg 2.
Here parameters we can pass in open sub routine (MACRO)
Even we can use nested MACRO

For example
MACRO 1
.
.
MACRO 2
.
.
2 END
1 END
So it is like box in box. Even we can say 2D also.
Essay question
1.

Explain about MACRO (open sub routine) ?

Let us have good concept in interrupt in 8086


Interrupt brings meaning of temporary step. In computer handling it is handling
of peripherals when key pressed then interrupt service routine (ISR) is called.
Interrupt of 8086:
Interrupts are hardware and software interrupt.
After executing one cycle the processor checks is there any interrupt.
So
ISR

MAIN PROG
.....................
......
.....................
......
.....................
......

PUSH F
CLEAR IF
PUSH CS
.
.

......................
......

POP IF
POP CS
POP F

2. Interrupt service routine and interrupt vector


ISR when executing man program if interrupt comes then it jumps ISR
Address of particular ISR is interrupt vector
3. Interrupt vector table
256 interrupt vector is available in 8086
So RAM location
00000
.

.
.
.
.
IRET

.
003FFH
In vector it contains code segment and instruction pointer. So
Interrupt vector table in 8086

CS
IP

INT 255 Vector

CS
INT 1 Vector
IP
CS
IP

Still in 4 bytes
CS HIGH
CS LOW
IP HIGH
IP LOW

INT 0 Vector

Dedicated Interrupt Types:


They are for CPU operation
i.

INT 0 (Divide by zero error)


In this interrupt also called exception

ii.

INT 1 (Single stepping)


It is like tracing which is an important idea in debugging

iii.

INT 2 (Non mask able interrupt)

iv.

INT 3 (Break point interrupt)

v.

INT 4 (Overflow interrupt)

III. Software interrupts:


The general syntax is
INT type number
Interrupt vector table alloc
INT type no.
0
1
2
3
4
5 to 31
32 to 255

LOC
0000:0000
0000:0004
0000 0008
0000 0000
0000 0010

ii. DOS and BIOS interrupt routine


DOS:
INT 21H
BIOS:
Basic input output system

Appn
divide by zero
single step interrupt
NMI
Break
overflow
reserved by
available to user

Question and Answer


2 Mark question
1. Define interrupt? What is ISR?
Ans:
Interrupt brings meaning of temporary step. In computer handling it is
handling of peripherals when key pressed then interrupt service routine (ISR) is
called.
2. Define ISR and IV?
Ans:
ISR when executing main program if interrupt comes then it jumps ISR.
Address of particular ISR is IV (interrupt vector)
3. Define IVT in 8086.
Ans:
256 interrupt vector is available in 8086 while in vector it contains code
segment and instruction pointer.
4. What are the functions of dedicated interrupt types?
Ans:
i.

INT 0 (Divide by zero error)

ii.

INT 1 (Single stepping)

iii.

INT 2 (Non mask able interrupt)

iv.

INT 3 (Break point interrupt)

v.

INT 4 (Overflow interrupt)

5. What are the DOS and BIOS interrupt routines?


Ans:
i.

In DOS INT 21 H

ii.

BIOS: Basic input output system.

Objective type question


1. Interrupt means _______
i.

Temporary stop

ii. Permanent stop

2. ISR is __________
i.

Interrupt stack register

ii.

Interrupt service routine

3. Interrupts are _____. _______


i.

Software, hardware

ii. No such

4. When executing main program it jumps to _____


i.

ISR

ii. No such

5. INT 0 meant for ______


i.

Divide by zero error

ii.

Single step error

6. INT 1 meant for _____


i.

Single step error

ii.

Divide by zero error

7. INT 2 means for __


i.

NMI

ii. MI

8. INT 3 meant for ______


i.

Break point interrupt

ii.

NMI

9. INT 4 _______
i.

NMI

ii. Overflow interrupt

10. BIOS is __________


i.

Basic input output system

ii.

No such

Result analysis
1.i

2.ii

3.i

4.i

5.i

If your score is greater than 9 go to day 15

6.i

7.i

8.i

9.ii

10.i

Hardware Interrupts
8086 has INTR pin NMI pin
i.

NMI (Non maskable interrupt)

ii.

INTR (Non vectored interrupt in 8086


INTR high priority interrupt
Generation of a type number.
It is to processor. When INTR pin is given the processor responds by

lowers the INTA line.


There is 74LS244 tristate buffer (ON, OFF, High impedance)
Input given by switches depends on that, that types processor (8086) gets
interrupts.

D0
D1
8
0
8
6

7
4
L
S
2
4
4

D2
D3
D4
D5
D6
D7

IN TA

Generation of type number

OE

OC

VI.

Priority of interrupts
i. Internal interrupts and software interrupts
ii. NMI
iii. INTR

Question and answers


2 mark question
1. Explain hardware interrupt?
Ans:
8086 has INTR pin and NMI pin
i.

NMI (Non maskable interrupt)

ii.

INTR (Non vectored interrupt in 8086


INTR high priority interrupt

2. Explain tri state buffer?


Ans:
For example
74LS244 - Tri state buffer
i.

State 1: ON
State 2 : OFF
State 3: high impedance

3. What are the priority interrupts?


Ans:
i.

Internal interrupts and software interrupts

ii.

NMI (non maskable interrupt)

iii.

INTR

Essay question
1. Explain in detail about interrupts?
Ans:
Day 14 day 15

Objective type question:


1. 8086 has __, ____
i.

INTR, NMI

ii. No such

2. NMI is ____
i.

New maskable interrupt

ii.

Non maskable interrupt

3. Non vectored interrupt pin _____


i.

INTR

ii. No such

4. Tri state buffer is _______


i.

74LS200 ii. 74LS244

Result analysis
1.i

2.ii

3.i

4.ii

If score is greater than 4 you can go to day 16th

List of instruction (String)


SI.No

instruction format

function performed

MOV SB / MOV SW

move byte or word string

CMP SB / CMP SW

compare byte or lord string

SCASB / SCA SW

scan byte or word string

LOD SB / LOD SW

load byte or word string

STO SB / STO SW

store byte or word string

CLD

clear direction flag

SID

set direction flag

REP

REP E / REP 2

10

REP NE / REP NZ

Question and Answer


Essay question
1. Explain about 8086 string instruction?
Ans: 16th day
Objective type question:
1. MOV SB / MOV SW is _______
i.

Move byte or word string

ii. Compare

2. CMP SB / SMP SW ______i.

Move byte or word string

ii Compare

3. SCA SB / SCA SW _______i.

Scan byte or word string

ii. No such

4. LOD SB / LOD SW ________


i.

Load byte (or) word string

ii. No such

5. STOSB / STO SW _____


i.

Store byte or word string

ii. Set byte or string

6. CLD _____
i.

Call

ii. Clear direction flag

7. STD ______
i.

Store ii. Set direction flag

8. REP ________
i.

Repetitive

ii. Jump

Result analysis
1.i

2.ii

3.i

4.i

5.i

6.ii

7.ii

If your score greater than 7 you can go to Unit II

8.i

ANNEXURE
UNIT I
(PROGRAMMING 8086)

1. Addition of 60 & 40:


Program:
. MODEL

SMALL

. CODE
. START UP
MOV AL, 60 H
MOV BL, 40 H
ADD AL, BL
MOV DL, AL
. EXIT
. END
Explanation:
The name of program is small. The main program startup first enter value 60 to
AL (Accumulator lower byte)
Second enter value 40 to BL
Now ADD 60, 40 i.e. AL, BL store the result in AL.
MOV AL value to DL. Then exit
2. Describe with an example DATA segment and CODE segment.
Program:
.MODEL

TIN 4

. DATA
NUM 1

DB

50 H

NUM 2

DW

0060 H

NUM 3

DW

0070 H

.CODE
.START UP
MOV AL, NUM 1
BOV

BX, NUM 2

MOV CX, AX
MOV BX, NUM 3
.EXIT
.END

Here data segment defines Num 1 DB (Data byte) so 8 bit register.


Num 2, NUM are define word (16 bit) word means the size of the
microprocessor.
In startup main program Num 1 only 8 bit others are 16 bit so it relats BX, CX.
3. Start the ORG program 0020H?
Program:
.MODEL

TIN 4

. DATA
ORG 0020 H
4. Write a program to use MOV instruction?
Program:
. MODEL

TIN 4

. DATA
COST DB

10 H

SELL DB
.CODE
.START UP
PROFIT

EQU 25 H
MOV AL, COST
ADD AL, PROFIT
MOV SELL, AL
EXIT
.END

5. Add 5 numbers in an array?


Program:
.MODEL

TIN 4

. DATA
ARRAY DB 10 H
.CODE
.START UP
MOV CL, 5

20 H

30 H

40 H

50 H

MOV AL, 0
MOV DL, 0
LOOP 1

ADD AL,
INC

ARRAY [DI]

DL

DCR CL
JNZ

LOOP

MOV RESULT, AL
6. Subtract 40 from 60
Program:
.MODEL

SMALL

.CODE
.START UP
MOV AL, 60 H
MOV BL, 40 H
SUB

AL, DL

MOV DL, AL
EXIT
END
7. Multiply program? OB x OF6H
Program:
.MODEL

TIN 4

. DATA
MULT DB

OBH / MULTIPLI

MULP DB

OF6H

PROD DW
.CODE
.START UP
MOV AL, MULP
MUL

MULP

MOV PROD, AX
.EXIT
.END
Explanation:

The main instruction is


MVL
MVL A, B = A * B

8. Find factorial of 51?


Program:
.MODEL

TIN 4

.DATA
FACT DW

0
.CODE
.START UP

MOV A4, 01
MOV CL, 05
LOOP MUL AL, CL
DEC CL
JNZ

LOOP1

MOV FACT, AL
9. Division
MOV AX,

4444 H

MOV CL, 02
DIV

CL

Here
AX

CL

02

AX / CL = 4444 / 2 = 2222
Quotient in AX
Remainder in CL
10. Consider AX = 009CH

BX = 0002 H CX = 000AH

Find various logical instruction?


Ans:
i.

AND operation:
AND AX, BX

Example
0000
0000
0000

0000
0000
0000

0000
0000
0000

1001
0010
0000

Result is 0000H
ii.

OR operation:
OR

AX, BX

Example
0000
0000
0000

0000
0000
0000

0000
0000
0000

1001
0010
1011

0000
0000
0000

1001
0010
1011

Ans: 000BH
iii.

XOR:
0000 0000
0000 0000
0000 0000
Ans: 000BH

iv.

TEST, AX, BX
0000 0000
0000 0000
0000 0000
Ans: 0007H

0000
0000
0000

1001
0010
0111

This logical instruction mainly applicable in mask; in image processing

11. Shift one bit right and left say what is the mathematical result?
Program:
SHL

AX, 1

For example
AX

0000
0

0000
0

0000
0

0010
2

0000
0

0010
4

Now shift left one bit


0000
0

0000
0

So shift left is one bit replies multiply by 2. If shift left by 2 bits is multiply by 4
Similarly SHR is shift right in bit divide by two. Shift right in two bit n divide by four.
Program 13:
Rotate left or right is making interface CPU with 8255 and display the LED eight left to
right or right to left
Program 14:
REP

MOV SB

This is the high frequency move the type string.


Program 15:
CMPSB
Compare the string byte.
Port operation:
Port means carry. In port from input device to CPU. Output CPU to output device
IN AL, 27 H device number
MOV 27 to AL
OUT AL, 28 H device number
MOV CPU buffer (or) accumulator to 28

Ex. No: 1

32 BIT ADDITION AND SUBTRACTON

AIM:
To write an assembly language program to add and subtract two 32-bit numbers using
8086 microprocessor kit.
APPARATUS REQUIRED:

8086 Microprocessor Kit

Power Chord

Key Board

33 - BIT ADDITION:
ALGORITHM:
Step1: Start the program.
Step2: Move immediately the number 0000H to CX register.
Step3: Copy the contents of the memory 3000 to AX register.
Step4: Add the content of the memory 3004 with the content of AX register.
Step5: Copy the content to AX register to two memories from 2000.
Step6: Copy the contents of the memory 3002 to AX register.
Step7: Add the content of the memory 3006 with the content of AX register.
Step8: Jump to specified memory location if there is no carry i.e. CF=0. Step9:
Increment the content of CX register once.
Step10: Copy the content to AX register to two memories from 2002.
Step11: Copy the content to CX register to two memories from 2004.
Step12: End.

MNEMONICS:
MOV CX, 0000
MOV AX, [3000]
ADD AX, [3004]

MOV [2000], AX
MOV AX, [3002]
ADC AX, [3006]
JNC

loop1

INC

CX

Loop1 MOV [2002], AX


MOV [2004], CX
HLT
TABLE: 1
Mnemonics
Memory

Label

Description
Instruction Operand

1000

MOV

CX,0000

Move immediately 0000H to CX


register

1004

MOV

AX, [3000]

Copy contents of 3000 to AX register

1008

ADD

AX, [3004]

Add content of memory 3004 with


content of AX register
Copy content to AX register to two
100C

MOV

[2000], AX
memories from 2000
Copy contents of memory 3002 to

1010

MOV

AX, [3002]
AX register
Add content of memory 3006 with

1014

ADC

AX, [3006]
content of AX register

1018

JNC

loop1

Jump to specified memory CF=0


Increment content of CX register

101A

INC

CX
once
Copy content to AX register to two

101B

Loop1 MOV

[2002], AX
memories from 2002
Copy content to CX register to two

101F

MOV

[2004], CX
memories from 2004

1023

HLT

Halt

OUTPUT:
INPUT DATA:

OUTPUT DATA:

3000:

9999

2000:

3332

3002:

9999

2002:

3333

3004:

9999

2004:

3006:

9999

32 - BIT SUBTRACTION:
ALGORITHM:
Step1: Start the program.
Step2: Move immediately the number 0000H to CX register.
Step3: Copy the contents of the memory 3000 to AX register.
Step4: Add the content of the memory 3004 with the content of AX register.
Step5: Copy the content to AX register to two memories from 2000.
Step6: Copy the contents of the memory 3002 to AX register. Step7:
Subtract the content of the memory 3006 from AX register.
Step8: Jump to specified memory location if there is no carry i.e. CF=0.
Step9: Increment the content of CX register once.
Step10: Copy the content to AX register to two memories from 2002.
Step11: Copy the content to CX register to two memories from 2004.
Step12: End.
MNEMONICS:
MOV CX, 0000
MOV AX, [3000]
ADD AX, [3004]
MOV [2000], AX
MOV AX, [3002]
SBB AX, [3006]
JNC

loop1

INC

CX

Loop1 MOV [2002], AX


MOV [2004], CX
HLT

TABLE: 2
LMnemonics
Memory

label

Description
Instruction Operand

1000

MOV

CX,0000

Move immediately 0000H to CX


register

1004

MOV

AX, [3000]

Copy contents of 3000 to AX register

1008

ADD

AX, [3004]

Add content of memory 3004 with


content of AX register
Copy content to AX register to two
100C

MOV

[2000], AX
memories from 2000
Copy contents of memory 3002 to

1010

MOV

AX, [3002]
AX register
Subtract content

1014

SBB

of memory 3006

AX, [3006]
from content of AX register

1018

JNC

loop1

Jump to specified memory CF=0


Increment content of CX register

101A

INC

CX
once
Copy content to AX register to two

101B

Loop1 MOV

[2002], AX
memories from 2002
Copy content to CX register to two

101F

MOV

[2004], CX
memories from 2004

1023

HLT

Halt

OUTPUT:
INPUT DATA:

OUTPUT DATA:

3000:

9999

2000:

0000

3002:

9799

2002:

FE00

3004:

9999

3006:

9999

RESULT:
Thus an assembly language program to add and subtract two 32-bit numbers
was written and executed using 8086 microprocessor kit.

Ex. No: 2

16 BIT MULTIPLICATION AND DIVISION

AIM:
To write an assembly language program to multiply and divide two unsigned 16-bit
numbers using 8086 microprocessor kit.
APPARATUS REQUIRED:

8086 Microprocessor Kit

Power Chord

Key Board

MULTIPLICATION:

ALGORITHM:
Step 1: Start the program.
Step2: Copy the contents of the memory 3000 to AX
register. Step3: Copy the contents of the memory 3002 to
CX register.
Step4: Multiply the content of the CX register with the content of
accumulator. Step5: Copy the content to AX register to the memory 2000.
Step6: Copy the contents of DX register to the memory
2002. Step7: End.
MNEMONICS:
MOV AX, [3000]
MOV CX, [3002]
MUL CX
MOV [2000], AX
MOV [2002], DX
HLT
TABLE: 1

L
Memory

Mnemonics

label

Description
Instruction Operand

1000

MOV

AX, [3000]

Copy contents of 3000 to AX register

1004

MOV

CX, [3002]

Copy contents of 3002 to CX register


Multiply the content of the CX register
with the content of
accumulator

1008

MUL

CX

100A

MOV

[2000], AX

Copy content to AX register to the


memory 2000
Copy content to DX register to the
100E

MOV

[2004], DX
memory 2002

1012

HLT

Halt

OUTPUT:
INPUT DATA:

OUTPUT DATA:

3000:

1234

2000:

0060

3002:

5678

2002:

0626

DIVISION:
ALGORITHM:

Step 1: Start the program.


Step2: Copy the contents of the memory 3000 to AX
register. Step3: Copy the contents of the memory 3002 to
CX register.
Step4: Divide the content of the CX register from the content of
accumulator. Step5: Copy the content to AX register to the memory 2000.
Step6: Copy the contents of DX register to the memory
2002. Step7: End.
MNEMONICS:
MOV AX, [3000]
MOV CX, [3002]
DIV CX
MOV [2000], AX
MOV [2002], DX
HLT

TABLE: 2
L
Memory

Mnemonics

label

Description
Instruction Operand

1000

MOV

AX, [3000]

Copy contents of 3000 to AX register

1004

MOV

CX, [3002]

1008

DIV

CX

Copy contents of 3002 to CX register


Divide the
content
of the CX register
with the content of
accumulator

100A

MOV

[2000], AX

Copy content to AX register to the


memory 2000
Copy content to DX register to the
100E

MOV

[2004], DX
memory 2002

1012

HLT

Halt

OUTPUT:
INPUT DATA:

OUTPUT DATA:

3000:

1234

2000:

0000

3002:

5678

2002:

4444

RESULT:

Thus an assembly language program to multiply and divide two unsigned 16-bit
numbers was written and executed using 8086 microprocessor kit.

Ex. No: 3

FACTORIAL

AIM:
To write an assembly language program to calculate factorial of n-numbers using
8086 microprocessor kit.
APPARATUS REQUIRED:

8086 Microprocessor Kit

Power Chord

Key Board

ALGORITHM:
Step 1: Start the program.
Step2: Move immediately the number 0000H to AX
register. Step3: Copy the contents of the memory 3000 to
CX register. Step4: Move immediately the number 0001H
to AX register.
Step5: Multiply the content of the CX register with the content of
accumulator. Step6: Decrement the content of CX register once.
Step7: Jump to specified memory location if there is no zero in CX
register. Step8: Copy the content to AX register to two memories from
2000. Step10: End.
MNEMONICS:
MOV AX, 0001
MOV CX, [3000]
MOV AX, 0001
Loop1 MUL CX
DEC CX

JNZ loop1
MOV [2000], AX
HLT
TABLE: 1
L
Memory

Mnemonics

label

Description
Instruction Operand
Move

1000

MOV

immediately

the

number

AX, 0001
0001H to AX register
Copy the contents of memory 3000 to

1004

MOV

CX, [3000]
CX register
Move

1006

MOV

immediately

the

number

AX, 0001
0000H to AX register
Multiply content of CX register
with

100A

loop1

MUL

CX
content of accumulator
Decrement content of CX register

100B

DEC

CX
once
Jump to specified memory location if

100C

JNZ

loop1
there is no zero in CX register
Copy content to AX register to

100E

MOV

[2000], AX
memory 2000

1012

HLT

Halt

OUTPUT:

INPUT DATA:

OUTPUT DATA:

3000: 0008

2000: 9d80

RESULT:

Thus an assembly language program to calculate factorial of n-numbers was


written and executed using 8086 microprocessor kit.

Ex. No: 4

SORTING IN ASCENDING ORDER

AIM:
To write an assembly language program to sort n-numbers in ascending order using
8086 microprocessor kit.
APPARATUS REQUIRED:

8086 Microprocessor Kit

Power Chord

Key Board

ALGORITHM:
Step 1: Start the program.
Step2: Load datas into the memory.
Step3: Set the conditions to sort n-numbers in ascending order.
Step4: Sort the n given numbers in ascending order.
Step5: Store the result in the memory.
Step6: Display the sorted result from memory.
Step7: End.

MNEMONICS:

MOV BX, 2000


MOV CX, [BX]
MOV CH, CL
Loop2 INC

BX

INC

BX

MOV AX, [BX]


INC

BX

INC

BX

CMP AX, [BX]


JC

loop1

MOV DX, [BX]


MOV [BX], AX
DEC BX
DEC BX
MOV [BX], DX
INC

BX

INC

BX

Loop1 DEC BX
DEC BX
DEC CL
JNZ loop2
MOV BX, 2000
MOV CH, CL
DEC CH
JNZ loop2
HLT

Memory

TABLE: 1
L
label
Instruction

Mnemonics

Description

Operand

1000

MOV

BX, 2000

Move2000 to BX register

1004

MOV

CX, [BX]

Move BX memory data to CX register

1006

MOV

CH, CL

Move data from CL to CH

1008

Loop2 INC

BX

Increment BX register content once

1009

INC

BX

Increment BX register content once

100A

MOV

AX, [BX]

Move BX memory data to AX


register
100C

INC

BX

Increment BX register content once

100D

INC

BX

Increment BX register content once

100E

CMP

AX, [BX]

Compare AX register content and


BX memory
Jump to specified memory location
1011

JC

loop1
if carry is 1
Move BX memory data to DX

1013

MOV

DX, [BX]
register
Move data from AX register to BX

1015

MOV

[BX], AX
memory data

1017

DEC

BX

Decrement BX register content once

1018

DEC

BX

Decrement BX register content once

1019

MOV

[BX], DX

Move data from DX register to BX


memory data
101B

INC

BX

Increment BX register content once

101C

INC

BX

Increment BX register content once

101D

Loop1 DEC

BX

Decrement BX register content once

101E

DEC

BX

Decrement BX register content once

101F

DEC

CL

Decrement CL register content once

1020

JNZ

loop2

Jump to specified memory location


if there is no zero in CX register

1022

MOV

BX, 2000

1026

MOV

CH, CL

1028

DEC

CH

Move2000 to BX register
Copy CL register data to CH register
Decrement CH register content once
Jump to specified memory location

1029

JNZ

loop2
if there is no zero in CX register

102B

HLT

Halt

OUTPUT:
INPUT DATA:

OUTPUT DATA:

2000:

0004

2002:

0001

2002:

0003

2004:

0002

2004:

0005

2006:

0003

2006:

0004

2008:

0004

2008:

0002

200A: 0005

200A: 0001

RESULT:

Thus an assembly language program to sort n-numbers in ascending order was


written and executed using 8086 microprocessor kit.

Ex. No: 5

SOLVING AN EXPRESSION

AIM:
To write an assembly language program for solving an expression using 8086
microprocessor kit.
APPARATUS REQUIRED:

8086 Microprocessor Kit

Power Chord

Key Board

ALGORITHM:
Step 1: Start the program.
Step2: Load datas from memory to AX
register. Step3: Set the conditions to solve an
expression.
Step4: Solve the expression given below using the conditions
assumed. Step5: Store the result in the memory.
Step6: Display the sorted result from
memory. Step7: End.

MNEMONICS:
MOV BX, [2000]
MUL AX
MOV BX, [2002]
MUL BX
MOV [3000], AX
MOV AX, [2000]
MOV BX, [2004]
MUL BX
ADD AX, [3000]
ADD AX, 0001
MOV [2006], AX
HLT

TABLE: 1
L
Memory

Mnemonics

label

Description
Instruction

Operand
Move data from memory 2000 to

1000

MOV

AX, [2000]
AX register
Multiply content of AX register with

1004

MUL

AX
content of AX register
Move data from memory 2002 to

1005

MOV

BX, [2002]
BX register
Multiply content of BX register
with

1009

MUL

BX
content of AX register
Copy content to AX register to

100A

MOV

[3000], AX
memory 3000
Move data from memory 2000 to

100E

MOV

AX, [2000]
AX register
Move data from memory 2004 to

1012

MOV

BX, [2004]
BX register
Multiply content of BX register
with

1016

MUL

BX
content of AX register
Add content of memory 3000 with

1017

ADD

AX, [3000]
content of AX register
Add the number 0001 to AX

101B

ADD

AX, 0001
register
Copy content to AX register to

101F

MOV

[2006], AX
memory 2006

1023

HLT

Halt

OUTPUT:
INPUT DATA:

OUTPUT DATA:

2000:

0002

2006: 1F

2002:

0004

2004:

0007

RESULT:

Thus an assembly language program for solving an expression was written and
executed using 8086 microprocessor kit.

Ex No: 6

SUM OF N NUMBERS IN AN ARRAY

AIM:
To write a program to find sum of n numbers in an array.

APPARATUS REQUIRED:

8085 Microprocessor Kit

Power Chord

ALGORITHM:
Step1: Start the program.
Step2: Initialize the counter.
Step3: Get the first number.
Step4: Decrement the counter.
Step5: Load the base address of an array in to BX
Step6: By using the loop get the next number in to DX and add it with AX.
Step7: Increment the pointer and decrement the counter.
Step8: If the counter value is not equal to zero then go to step6
Step9: Else store the result.
Step10:Stop the program.

MNEMONICS:
MOV CL,[2000]
MOV AX,[2002]
DEC CL
XOR D1,D1
LEA BX,[2004]
LOOP1 MOV DX,[BX+D1]
ADD AX,BX
INC D1
INC D1
DEC CL
JNZ LOOP1
MOV [3000],AX
HLT

TABLE:
LABEL

LOOP 1

OPCODE

OPERAND

DESCRIPTION

MOV

CL,[2000]

Move the memory content to CL.

MOV

AX,[2002]

Move the memory content to AX

DEC

CL

Decrement the CL register.

XOR

D1,D1

XOR,D1 registers

LEA

BX,[2004]

MOV

DX,[BX+DI]

Move the content of 2004 to BX


Move the content of BX+D1 to
DX

ADD

AX,BX

Add AX with DX content.

INC

DI

Increment D1

INC

DI

Increment D1

DEC

CL

Decrement CL

JNZ

LOOP 1

MOV

[3000],AX

If zero flag is reseted go to loop1


Move the content to
memory
location

HLT

Halt

OUTPUT:
INPUT DATA:

OUTPUT DATA:

2000:0003

3000:0006

2002:0002
2004:0003
2006:0001

RESULT:
Thus the sum of n numbers in an array has been done using 8086 microprocessor and the
output is verified.

Unit II
8086 SYSTEM BUS STRUCTURE
8086 Signals basic configuration system bus timing system design using 8086 I/O
programming Introduction to multiprogramming system bus structure multiprocessor
configurations coprocessor, closely coupled and loosely coupled configurations
introduction to advanced processors.

8086 signals
The advantage of 8086 has 16 bit data bus. Instruction queue is 6 byte. It has memory and I/O
interfacing has got pin M/IO. And also it has BHE / S7 for 8086.
8086 has two mode operation
i.

Minimum mode

ii.

Maximum mode
Min mode for only one processor whereas max mode is multiprocessor

1. Minimum mode pins


In 8086

B HE / S 7
8
0
8
6

BH E
L
A
T
C
H

A16-A19
S3
S6
AD0-

A0-A19

AD15

ALE

D0-D15

Here ALE is address latch enables filters by latch to filter address and data lines.
There are 3 types of signal
i.

Common mode for min and max

ii.

Only min mode

iii.

Only max mode

I.

Only min mode:


i.

ALE
AD0 AD15
ALE filters address and data lines

A19/ S6 A16 / S3

ii.

S4
0
0
1
1

S3
0
1
0
1

extra segment
stack segment
code segment
data segment

Four segments can be accessed through S3 & S4 signals


ii.

RD

: it is when signal is low we can go for I/O read or memory read.

iii.

WR

: when the signal is low from buffer (latch) to memory or output device

iv. Clock: it is used to set the frequency


v. Reset
vi. Ready
vii. Test:
it check whether arithmetic coprocessor in the system
viii. ALE : Address latch enable
ix.

D EN

: Data available or not

x.

DT / R :

xi.

M / IO

data received or transmitted

: Memory and I/O operation

xii. HOLD: when it is high DMA (direct memory access) taken place
xiii. HLDA: Acknowledgement in DMA
xiv:

MN / M X

: it is min and max. In min mode only one processor max mode has more than

one processor.
xv:

B HE / ST

xvi: GND: Ground signal


xvii: Vcc: The power supply
xviii: INTR: Interrupt
xix: INTA: Interrupt acknowledgement
xx: NMI: non maskable interrupt

The demultiplex of address (or) data bus is by latch


74LS373:
And also it uses 74LS245 for octal tri state bi directional buffer.

A1

B1

A2
A3
A4
A5

7
4
L
S
2
4
5

A6
A7

DIR

Control signals for read and write


While read it needs tristate buffer and write it needs latch
It does
MEMR Memory read
MEMW Memory write
IOR IO read
IOW IO write

B3
B4
B5
B6

A8

Memory and I/O:

B2

B7
B8

Clock generation:
Processor is synchronized with clock.
Ready:
8284 ready output pin is connected to READY input pin of 8086

7
4
L
S
244

M / IO

RD
WR
8
0
8
6

AD15

.
.
.
.

7
4
L
S
245

AD8

AD7

AD0

M / IO

RD
WR
D15

D8

.
.
.
.

7
4
L
S
245

Buffer
contro
l
bus

D7

D0

Buffer
data
bus

So generally

WR

W RD

I ORD

IMEM R
M / IO

MEM R

IOWR
The four signals IO read, IO write, Memory read and Memory write is given
In 8086 Read machine cycle timing diagram
T1

T2

T3

T4

Clock
AD0AD10
ALE

DT / R

RD
D EN

READY

AD0-A17

Data in

Similarly write cycle

T1

Address
data

W R

T2

T3

Address

Status

Address

Data

T4

Question and Answers


2 Mark questions
1. What are the advantages of 8086?
Ans:
16 bit data bus
Instruction queue is 6 byte
It has memory and I/O interface pin
It has

M / IO

BHE / S 7

2. What are the two modes of operations in 8086?


Ans:
i.

Minimum mode

ii.

Maximum mode

Minimum mode for only one processor


Maximum mode is for multiprocessor
3. Define ALE?
Ans:
Address latch enable, the latch filters address and data lines.
4. What are 3 types of signals in 8086?
Ans:
Only Min mode
Only Max mode
Common mode for min and max.
5. Explain briefly control signals for read and write?
Ans:
While read it needs tristate buffer and write in needs latch.
In

M / IO

it does

Memory Read MEMR


Memory Write MEMW
IO read

IOR

IO write

IOW

Essay question
1. a. Describe signals of 8086?
b. In 8086 read & write machine cycle timing diagram?
Ans: Day XVI & XVII
Objective question:
1. BHE is ___________
i.

Bus high enable

ii. Bus high interrupt

2. 8086 has _______, ______


i.

Minimum mode, max mode

ii.

No such

3. Min mode for ______


i.

One processor

ii. Two or more processor

4. Max mode for _________


i.

One processor

ii. Two or more processor

5. HOLD when it is high _______


i.

DMA taken place ii. PIC taken place

6. INTR meant for ______


i.

Interrupt

ii. Non interrupt

7. The demultiplexer of address (or) data is by batch ______


i.

74LS373

ii. 741

Result analysis
1.i

2.i

3.i

4.ii

5.i

6.i

If your score is 6 or more go to Day 17

7.i

It is dedicated for multiprocessor configuration. In multiprocessor it has inter processor


communication and bus contention.
The max mode 8086 with numeric coprocessor (8087) and I/O processor (8089). In
that loosely couples multiprocessor system.
The 8288 bus controller how lock control signal generated and compatible with 8086.
i.

Queue status pins


QS0,QS1

ii.

Lock

iii.

Instruction cycle has


a. FI Fetch instruction (opcode fetch)
DI Decode instruction
CO Calculate the operand address
FO Fetch operand
EI Execute instruction
WO write in memory

So max mode has

8
0
8
6

8288
Bus
controller

MR
MW
I OR
I OW

In Max mode
QS1
0
0
1
1

QS0
0
1
0
1

No operation
First byte of an opcode
Queue is Empty
Subsequence byte of

an

opcode

S2

S1

S0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

M/C cycle
interrupt
IO Read
IO write
Half
instruction factor
memory read
memory write
in active

Question and Answers


Essay questions
1. What are the signals for Max mode only?
Ans:

Day XVII

I/O Programming:
8086 need I/O as well as memory for inter connection so memory read and memory
write also I/O read (kbd) and I/O write (VDU).
There are so many I/O devices connected to the processor.
For that we need port. The meaning of port is carry. So transport has occurred.
For In port keyboard give data. For out port to printer etc.

Tri state
buffer

8086

I/P

(Input port)

Tri state
buffer

8086

O/
P

(output port)

Keeping the I/O ports with address bus and data bus and read and write control signals

D0-D15
8086

Output
Port

Input
Port

RD

Here relating (mapping) processor to I/O is


Memory mapped I/O
Peripheral or Isolated I/O
i.

Memory mapped I/O.

MR
EPRAM
8086

M
W

Here interfacing EPROM, EPROM by memory read and memory write


ii.

I/O mapped I/O:

kbd

Inpu
t

VDU

Outpu
t

8086

Question and Answers


2 Mark questions
1. 8086 need what inter connection
Ans:
i.

Memory interconnection

ii.

I/O inter connection

2. What are the four connection?


Ans:
i.

I/O read

ii.

I/O write

iii.

Memory read

iv.

Memory write

3. What is attached between I/P and processor and also O/P and processor?
Ans:

8086

Tri state
buffer

I/P

(Input port)

8086

Tri state
buffer

O/
P

(output port)

Essay question:
1. Explain in brief I/O programming in that I/O interfacing memory interfacing?
Ans: Day XVIII.

Multiprogramming:
More than one program executed by one processor is called multiprogramming. In
DOS it is elicited that only one program. In UNIX more than one program
i.e.
RAM
OS
Program 1

Program 2

Executed. It is also called static partition and another is dynamic partition.


Multiprocessor:
It is more than one processor executing single job is called multi processor.

Task
. . . .
.
Sub task
1

Processor
1
executes

. .
. .
.
. .
. .
.

Sub task
2

Processor
2
executes

Output

And also coprocessor augmentation is called multiprocessor


Bus contension:
More than one processor shares system memory and I/O through a common system
bus.

IPC means inter processor communicate


i.

Closely coupled configuration because 8086 augmented with 8087 numeric


coprocessor. Hence 8087 32 bit floating point operation does (executes) very
easily
System
Bus

8086

Bus
control
logic

Clock

8087
M

ii.

IO

Loosely coupled configuration:


It contains different modules. Each module may consist of an 8086

Local I/O
devices

Local
memory

Local bus
memory
control logic

Local Bus

Clock

Module 1
Module 2

8086 &
8087

System bus
control logic

While in loosely coupled system each processor runs independently. If more than one
processor shares common resources it is possible by
i.

Daisy chining:
The bus was requested. If bus is granted bus busy will be set. Hence other
masters have to wait. The masters are selected by if 4 markers are their 2 address
lines.

Master 0

Master 1

Master 2

Master 3

Hence

Module 1

Module 2
Bus access
log

Bus access
log

Bus
Controller

Bus request
Bus busy

ii.

Polling method:
If for example 4 masters are their the 2 address lines
Address line
0

Master 0

Master 1

Master 2

Master 3

Module n
Bus access
log

Module 0

Module
1

Module n

Module
2

0
Bus
Controller

iii.

0
0
1
Bus request
Bus busy

1
1

Independent priority method:

Module 1

Bus
Controller

1
0

Bus
start

Module
2

. . . . .
..

Bus request
1
Bus request Bus request
2
2

All masters get individual bus

Module
n

. . . . .
..

Question Answers
2 mark questions
1. Define multiprogramming?
Ans:
More

than

one

program

executed

by

one

processor

is

called

multiprogramming
2. Define multiprocessor?
Ans:
It is more than one processor executes single job is called multiprocessor
Task
. . . .
.
Sub task
1

Processor
1
executes

. .
. .
.
. .
. .
.

Sub task
2

Processor
2
executes

Output

Augmentation of coprocessor is called multiprocessor.


3. Say bus contension?
Ans:
More than one processor shares system memory and I/O through a common
system bus.
4. Define closely coupled configuration?
Ans:
8086 augment with 8087 numeric coprocessor.

5. Say loosely coupled configuration?


Ans:
It contains different modules.
Each module may consist of on 8086.
6. What are the methods for bus controlling?
i.

Daisy chaining

ii. Polling method

iii. Independent priority method


Essay question:
1. Explain bus contention?
Ans: Day XIX
2. Explain closely coupled and loosely coupled?
Ans: Day XIX
Objective questions:
1. More than one program execution by a processor is called ______
i.

Multiprogramming

ii. Multiprocessor

2. More than one processor execute single job is called


i.

Multiprogramming

ii. Multiprocessor

3. More than one processor shares system memory and I/O through a common system
bus _____
i.

Bus contension

ii. No such

4. 8087 is ______
i.

Ordinary processor

ii. Numeric co processor

Result analysis
1.i

2.ii

3.i

4.ii

If your score is equal to 4 you can go to XX

8087:
It is a numeric coprocessor. The main aim is in 8086 16 bit processor but 8087
support 32 bit floating point accuracy.

8086

sys

8087

I/O

8087 supports 32 bit accuracy. The 8087 has 8 register instruction queue. A co processor must
have ALU. Hence it contains floating point arithmetic module.
Status register and control register is also available.
Instruction pointer and operand pointers are available. It has address line AD0-AD15.

8 register

Clk

TAG

Reg
INT 0

0
1

AD0-

AD15
BHE

S0-S7

RW / GTO
RW / GT

Busy
Read

Instructio
n queue

Floatin
g point
arithm
etic

Next

Status reg
Control
reg
I Pointer
Operand
pointer

I/O processor
Transferring data with I/O ports

8251
USART

Memor
y

8272

CPU

8255 PPI

8237 DMA

It is impossible to have single CPU to nexusued. (interconnected). So IO processor is


available. It is like junction box. To make many connection
Hence
8272
8086

IOP
8089

8255
8257

This IO processor 8089 has the above mentioned connection.


PRQL

EXTL

SNTR

Rese
t

Channel 2

GA

SM

CS

Channel 1

GA

Control Logic

GB

GB

GC

GC

TP

TP
CCP

PP

IX

PP

ALU

IX

BC

BC

MC

MC

CS

CS
Bus Control
and Interface
PS
W

clk

Read
y

PS
W

B HG

AD0AD15

S0-S2

Question and Answers


1. Explain numeric coprocessor 8087?
Ans: Day XX
2. Explain I/O processor?
Ans: Day XX

Unit III
I/O Interfacing
Memory interfacing and I/O interfacing Parallel communication interface Serial
communication interface D/A and A/D interface Timer Keyboard / display controller
Interrupt controller DMA Controller Programming and applications case studies: Traffic
light control, LED display, LCD display, keyboard display interface and alarm controller.

Memory interfacing
Port:
The meaning of port is carry. Transport is carry across in etymology. Similarly in
microprocessor to I/O or memory must be interfaced, for that it needs port. Using the port
pins we can transmit (or) receive data from 8086 p to memory or I/O. So transmit and
receive data by the port command out (port) and in (port)
Generally the interfacing has the following type demands on the mechanism
i)
ii)

Serial communication interface


Parallel communication interface

In memory interfacing we can read and write in the some memory it is a combination of
registers which were selected by address. Memory is generally bifurcated into RAM
(Random Access Memory) and ROM (Read only Memory).
For ROM example is
EPROM (Erasable Programmable Read only Memory)
For example considering the EPROM
Output data

O/P
Buffer

A9

1K
EPROM
A0
Internal
Decoder

A0A1A2A3A4A5A6A7A8A9
Totally 10 add ress lines map
210 = 1 K
Similarly 11 address lines map
211 = 2 x 210 = 2 x 1 K = 2 K EPROM
12 Address Lines

CS
RD

212 = 22 x 210 = 4 x 1 K = 4 K EPROM


Similarly RAM:
It has not only read but also write

O/P
Buffer

A9

CS
RD

1K RAM
A0
Internal
Decoder

I/P
Buffer

W
R

Input data

CS is meant for ship select


For write or Read memory interfacing we need address
Decoding technique
i. Absolute decoding
ii. Linear decoding
i. Absolute Decoding
After addressing the size of RAM/ROM the remaining address lines are meant for CS
(Chip select)
Ex:
Interface 8086 with
2 K EPROM
1K EPROM
2 K EPROM = 211 lines A0 A10
1 K RAM = 210 lines A0 A9

Interfacing Memory
A0 A10

LATCH
8086

I /O/ M

RD

W /R

D0 D17

IOR
IOW
MR
MW

Decoder
74LS138

A0 A10

2K EPROM
A13

74LS138
Decoder

A14
A15

A12
A11

1K RAM

ii) Linear decoding:

Address calculation only used for chip select


A0 A10

8
0
8
6

LATCH
D0 D17

I /O/ M
RD
W /R

MR

74
LS138

MW
IOR
IOW

2K EPROM

A15

1K RAM

So address mapping 2K EPROM


A19 ........................A0
0......................0
Starting address
1.....................1
Ending address

Question and Answers


2 Mark questions
1.

Define port?
Ans:
The port meaning is carry. We can in port through keyboard. We can out port

the printer.
2.

What are the two communication interface?


Ans:
Serial communication interface
Parallel communication interface

3.

What are the two types of memory?


Ans:
RAM
ROM

4.

For mapping 1K how many address lines?


Ans:
210 = 1024 bytes = 1 K
So A0 A9 Address lines

5.

For interface the map remains address lines is used for what purpose?
Ans:
For mapping 1K map A0 A9 = 10 Address lines remains address lines are

used for decoder to go for chip select.


6.

Using decoder for chip select what are the decoding technique?
Ans:
Absolute decoding
Linear decoding

Essay Questions
i) Explain with example about memory interfacing of 2K ROM?
Ans: XXI
ii) Explain with example about differing decoding technique?
Ans: XXI

Objective questions
1. The two jobs of port is ________-i) In, Out

ii) Nil

2. The two types of memory is _______


i) RAM, ROMii) Nil
3. 2K EPROM how many address lines? _________
i) 11 line

ii) 12 lines

4. Decoding techniques used for _________


i) Chip select ii) Nil
Result Analysis
1)

2) i

3) i

4) i

if result is score is 4 then you can go to XXII

I/O Interfacing:
It is the communication between microprocessor between microprocessor and I/O. For the
input keyboard to port similarly port to display devices.
For input

kbd

Translate
buffer

8086 p

LATCH

Output

For output
8086

I/O Interfacing techniques:


It is mainly of two byte
i.

Memory mapped I/O

ii.

I/O Mapped I/O

For example:
I/O mapped I/O only input is

Read Tri
slot
buffer

S0

S1
8086 D0
D15

.
.
.
.
.
.
.

S15

A0
.
.
.
.

Decoder

IO / M

RD

A1
9

Here for input 16 pins will be given. The data in form of pin goes through tri state buffer.
Address line is meant for address decode.
Similarly the output mechanism is

D0
808
6

Output port
Latch

D15

A0
.
.
.
A19

Decoder

IO / M
WR

Combining Input and Output mapped I/O is create

Combining Input and Output mapped I/O is created

D0
8086 p

Input Port

D15

RD
IO R

I /O/ M
IOW
W
Output Port
A0
.
.
.
.
A19

Y0
Decoder

Y1

Similarly memory mapped I/O

S0
D0
Input Port

8086

D10

S15

Y0

Decoder

Output
Port
Y1

RD

I /O/ M
W

M R
MW

Questions and Answers


2 Mark Questions
1. What is I/O interfacing?
It is the communication between microprocessor and Input.
It is
Memory mapped I/O
I/O mapped I/O
Essay question
1.

Explain with example memory mapped I/O?


Ans: XXII

2.

Explain with example I/O mapped I/O?


Ans: XXII

In parallel communication interface. All the data lines connected paralelly. For
example programmable peripheral interface (PPI) 8255. And also it has named parallel port
chip. Here the mechanism is parallel data transfer. 16 bit connection and communication
between 8086 and PPT (8255). The 8255A is more advanced than 8255.
The 8255:
It has three ports. They are port A, Port B and Port C
Port A, Port B both are eight bits.
Port upper 4 bits
Port lower 4 bits
From the port keyboard, display devices, and printer is connected.
It is interfacing chip but it does not have any processing capability. For example
Port A
8
0
8
6

D0-D7

8
2
5
5
PPI

Keyboard
Port B

Port
C

Printer
LED
Display

The pin diagram has


i.

Data Bus buffer:


It has three state bi directional 8 bit buffer which is used to interface the chip to the

data bus of the system.


ii.

Read / Write control logic:


Data transfer bet wean the chip and the processor.

iii.

Group A and Group B controls:


The lower data line of D0 D7

connected to

I ORD

and

connected to data bus buffer. Read, write is

IOW R

Lower eight bit address line is used for chip select otherwise 16 bit address line is
used. A0 A1 for 4 separate entities.
Hence the block diagram of 8255 (Programmable peripheral interface)

Internal Block Diagram of 8255

Group A
Control

D0-D7
Data bus
buffer

Group A
Port A

Group A
Port C upper

PA0-A7

PC4PC3

Group B
Port C lower

PC0-C3

Group B
Port B

PB0-B3

Read
Write
Control
Logic

Cs

Group B
Control

The pin diagram of 8255 3 Ports = 3 x 8 = 24 Pin


Data buffer = 8 lines = 8 pin remains, 8 has Vcc, Gnd etc.
PA3

PA4

PA2
PA3
PA0

PA5
PA6

RD

PA5

CS

GND
A1
A2
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2

D0
8
2
5
5

D1
D2
D3
D4
D5
D6
D7
Vcc
PB7
PB6
PB5
PB4
PB3

Hence address decoding and connections between the 8086 and the 8255

IOW RIO RD

RD
WR

Port A

8255

A2

A1

A1

A0

8086

Data
Bus

Port B

Port C

D0D7
A7
A6
A5
SEL

A4
A3
A0

The port selection is possible in 8255 by used Pin A0 A1 of 8255


A1
0
0
1
1

A0
0
1
0
1

Status
Port A Selected
Port B Selected
Port C Selected
Control register

Question and Answers


2 Mark Questions
1.

Give example parallel communication interface?

Ans: Programmable peripheral interface 8255


2.

How many ports in 8255?


Ans: 3 Ports
i. Port A
ii. Port B
iii. Port C upper
iv. Port C lower

3.

What is Group A and Group B controls?


Ans: The lower data lines of D0 D7 connected to data bus buffer. Read, write

is

I OR

I OW

Essay questions
1.

Draw the block diagram of 8255?

2.

Interface between 8086 and 8255?

3.

Draw the pin diagram of 8255?


Ans: XXXIII

Objective questions
1.

8255 is ___________
i. Parallel port chip

ii. None

2. Port A, Port B, Port C Upper number of pins are ___, ____, _____
i. 8,8,4 ii) 8,8,8
3.Data buffer is ________
i. 8 lines

ii. 4 lines

4. Ports are initialized by _______


i. CWR

ii. IR

5. In ports input is read by by CWR says _______i. 1

ii. 0

6. In Ports output is write CWR says ____-

i. 1

ii. 0

Result Analysis
1. i

2. i

3. i

4. i

5. i

6. Ii

If the score greater than 5 is allowed to go for Day XXIV

Programming the chip involves only the writing of a particular word called controlled word
register (CWR) which is used to configuring the ports
1 Input, 0 - Output

D2
1
=
Mode
0 =
Mode

D6

D5

D4

D3

I/O

D2

D1

D0
Port
lower
Port B

BSR

Mode selection
0 = Mode 0
1 = Mode 1
Mode selection
00 = Mode 0
01 = Mode 1
10 = Mode 2

Port
upper
Port A

BSR (Bit Set/Reset) is used for initialize port C.


Modes of operation:
Mode 0

Basic input / Output

Mode 1

Strobed input / output

Mode 2

Bidirectional bus

Interfacing 16 bits I/O ports to the 8255


Two programmable peripheral interface with 16 bit port. 16 bit relations that 8086.

A2

01

A1

A0
D0
D7

Low byte of
data

A3
A7

Port A0 A7

8255 (LOW)

A0

Port B0 B7

CS

Port C0 C7

CS

Port A0 A7

S EC

Address
Decoder

A2
A1

01
00

BHC
8255 (HIGH)

Port B0 B7

D8
D15
High byte
of
data

Port C0 C7

Question and Answers


Essay question
1. Explain with example about initialize the ports of PPI (8255) in CWR?
Ans: XXXIV Day
2. How to interface 16 bits I/O prots to 8255 (PPI)?
Ans: XXXIV Day

ADC:
Analog to digital interfaced with 8086 is can be serial (or) parallel interface.
Import and application in parallel port (PPI 8255 Programmable peripheral interface).
Actually the analog signal is converted into digital form for further reference.
ADC 0808 / 0809:
Parallel interfacing. The advantage is
Resolution good
Total unadjusted error
Single supply
Low power
Conversion time
Hence the block diagram draws the operation

8
0
8
6

D0 D 7

8
2
5
5

Input
Port
Control
signal

A
D
C

Analog
input

Control
signal

This analog to digital conversion has following pin diagram IN 0 to IN7 pin (8 pin) Data lines
(D0 D7) Vcc, GND, etc.

IN0

GN
D

Cloc
k

D0

Vcc

D1

IN1

D2

IN2
IN3
I

D3

ADC 0808 / 0809

N4

D5

IN5

D6

IN6

N7

Eoc

Vref

(+)
O

LSB

ref (-)
W
R

Read

ALG

EOC

Clock

WR
(SC)
RD(OE)

ALE

ADDR
EOC
D0-D7
START CONVERSION

Timing diagram for 0809 / 0808

So referring the first figure the block diagram detailed by follows pin diagram

PC0
PC1

D0-

8
0
8
6

D7

A
A2

8
2
5
5

A1
A0

PC7

SO
C

PA0

EO
C

PA1

D0

PA2

D1

PA3

D2

PA4

D3

PA5

PB0
PB2

AL
E

A
D
C
0
8
0
9

D4

PA6

D5

PCc

D6
OE

ANALOG
INPUTS
A

Question and Answer


Essay Questions
1. Interface ADC with 8086?
Ans: Day XXV
Objective Question
1. 0808 / 0809 is ___________
i. ADC

ii. DAC

DAC:
Interfacing digital to analog conversion:
By using 8255 the 8086 is interfaced with 0800.
Hence conversion mechanism is digital to analog. It alludes
V = RI
I = V/R
From the pin D0 to D7
D7
D
D
D
D
D
D
D
I o I ref
6 5 4 3 2 1 0
2
4
8
16
32
64 128 256

D7

I ref

D6
4

D5
8

D4
16

D3
32

D2
64

D1
128

D0
256

The pin diagram elicts

VLC
1

IOUT2
V3
IOUT4
B1

0
8
0
0

16
configuration
Vref
(-)
Vref (+)
V4
B7

B2

B6

B3

B5

B4

Iref is the reference input current corresponding to Vref,


DAC (0800/0802)
The output of the DAC is current which is converted to a voltage by the opamp at the
output. If opamp is used in a difference configuration, both positive and negative values may
be obtained.
DAC connected with 8255 is

+5
V
5K

+5
V

PA0

PA1

PA2

D
1

PA3

PA4

PA5
PA6
PA7

V
+

1+
Vref
5.6
K

0
8
0
0

IO
W
TO
CR
O

15V
(-)

5K

V-

D
5

12V
D
6

D
7

Com
p
16.1f

GN
D

Question and Answers

Essay question
1. Explain interface DAC with 8086?
Ans: XXVI

The chip 8253 is a programmable timer chip used for timing application 8254 works
in higher frequencies. Both timer chips 8253/54 provide three independent 16-bit timers.
8253 execute frequency 2.6 MHz 8254 execute frequency 10 MHz. There are three
independent counters controlled by contro l register.
So
CS

0
0
0
0

A1
0
0
1
1

A0
0
1
0
1

Status
Counter 0
Counter 1
Counter 2
Control register

So the detailed pin diagram of 8253 is

Vcc

D
7

D
6

D
5

8
2
5
3

D
4

D
3

D
2
GATE
0
GND
D
1

D
0

The detailed functional block diagram of 8253 / 54

A1
A0
Clk 2
OUT2
GATE 2
Clk1
GATE 1
001

D0-D7

RD
WR
A0

Data Bus
Buffer

Read /
Write
Logic

A1

Clk
0
Gate
0
Out 0

COUNTER
1

Clk
1
Gate
1
Out 1

B
U
S

Control
word
register

Counter :

I
N
T
E
R
N
A
L

COUNTER
0

COUNTER
2

Clk
2
Gate
2
Out 2

Every counter has three pins clk, gate and out


i. Clk:
It is measuring frequency T = 1/f
Frequency of 8253

2.6 Mhz

8254

10 Mhz

ii. GATE
Counter pin always status = 1
iii. OUT: output response in wave from obtained
Data and Counter pin:
Data
R D

W R

D0-D7
lower by data

Especially

I/O read
I/O write

Pin diagram is
A1
0
0
1
1

A0
0
1
0
1

Status
Counter 0
Counter 1
Counter 2
Control register

Operation Modes from CWR:


1. Mode 0

2. Mode 1 :

Programmable one shot

3. Mode 2 :

Rate generator

4. Mode 3 :

Square wave generator

5. Mode 4 :

Software triggered mode

6. Mode 5:

Hardware triggered mode

Interfacing 8254 with 8086

Interrupt on terminal count

I/O interfacing is

Memory
I/O

I/O Mapped I/O

Mapped

I/O Mapped I/O

D0 D 7

Clk 0
Gate 0

A0

OUT 0

A1

8086

IO R
IOW

8254

Clk 1

RD

Gate 1

WR

OUT 1
Clk 2
Gate 2
OUT 2

A2
.
.

CS

A15

I/O Interfacing is very good in inter connection 8254 interfaced with data lines and
time measurement done by 3 counters. Address lines A2 to A15 is meant for chip select.

Memory Mapped I/O:


I/O interfacing very good in interconnection. That is 3 counter. Address line A2 to A19
is for chip select.
So memory mapped I/O is

D0 D 7

Clk 0
Gate 0

A0

OUT 0

A1

8086

MR
MW

8254

Clk 1

RD

Gate 1

WR

OUT 1
Clk 2
Gate 2
OUT 2

A2
.
.
A19

CS

Essay question:
1. a. Explain the block diagram 8253/54?
b. Pin diagram 8253/54?
c. Operation modes from CWR?
d. Explain I/O interface 8254 with 8086?
i. I/O Mapped I/O
ii. Memory Mapped I/O
Ans:
Day XXVII
Objective questions
1. 8253 is _____________
i. Programmable timer chip ii. PPI
2. 8253/54 has __________
i. 16 bit

ii. 8 bit

3. 8253 executes frequency _________


i. 2.6 MHz

ii. 10 MHz

4. _________________ in 8253 / 54
i. 3 Counter

ii. None

5. ____, ____, ____ pins in counter


i. Clk, Gate and out

ii. No such

6. Operation modes from CWR in mode 0, Mode 1 is _______


i. Interrupt on terminal counter programmable one shot
ii. Rate generator, square wave generator
7. Operation modes from clk in mode 2, Mode 3 is ___, ____
i. Nil , Nil

ii. Rate generator , square wave generator

8. Operation modes from CWR in mode 4 and mode 5 i s_______________


i. Software triggered mode, Hardware triggered mode
ii. Nil, Nil.
Result Analysis
1. i.

2. i

3.i

4.ii

5.i

6.i

7.i

If your score greater than 8 than go to XXVIII

8.ii

9.i

8279 Keyboard display interface


The 8086 microprocessor has keyboard is the input and display the output
When key is pressed

+5V
Level

*****

R
Logic 0
Output

So simply keyboard interface is

K1
K2
D0-D7

K3
Input Port

K4
K5
K6
K7
T8

When K1 is pressed
D1 is O others are y
+5V

For reducing size in keyboard input is


C3

C2

C0

C1

R3
Input
Port A

R2
R1
R0

Instead of one dimension if you use matrix 2D representation the size is less but coverage of
key (number of keys are) more. So numbers of key increases.
Display interface:
Consider 7 Segment display

b
g

c
h
d

They are two types


i. Common Anode:

ii. Common Cathode

We need multiplexed display


We need port A and Port B

Vc
c

A
B
C
D

Output
Port A

D
E
C
O
D
E
R

a b c d e
f

Q4

Output
Port B

a b c d e
f

a b c d e
f

Q3

Q2

a b c d e
f

Q1

CS

The programmable keyboard display interface 8279s pin diagram is

IRQ

RLO-7

Key Data

Shift

Data
bus

8
2
7
9

CPU
interface

Contro
l
SLO-3

A0

A0-3

Reset
Clk

B0-3

Scan
Display
Data

Interfacing 8279 in I/O maped I/O with 8086:


Here address lines A2...A15

address lines available they are used for chip select

D0

Shift

D7
A0

8
0
8
6

IO R
IOW

Rest
Out
Clk Out

RD
WR

8
2
7
9

CNT
L
RL0L7

Display
Lines

II NT
A1
.
.
A15

Reset
Lines

CS

Interfacing 8279 in Memory mapped I/O with 8086:


Address lines A1...A19
They are used for chip select

D0

Shift

D7

CNT
L
RL0-

A0

8
0
8
6

MR
MW
Rest
Out
Clk Out

8
2
7
9

L7
SL0L7
Display
Lines

II NT
A1
.
.
A15

CS

Essay question:
i.

Explain keyboard and display interface?

ii.

Explain 8279?

iii.

Interfaced 8279 in I/O mapped I/O with 8086?

iv.

Interfacing 8279 in memory mapped I/O with 8086?

Ans:
XXVIII
Objective question
i.

8279 ____________
i.

PPI

ii. Keyboard, Display interface

ii. In 8279 has __________ display


i.

3 segment

ii. 7 Segment

iii. Display are ________


i.

Common anode, common cathode

ii.

Nil, Nil

Result Analysis
1. ii

2. Ii

3.i

8259 Programmable interrupt controller.


8259 has eight interrupt request IR0 IR7. Depends on the priority the interrupt is
called Nexus (interconnection) between a PTC 8259 and the 8086.

D0-D7

IR0
IR1
IR2

8086

8259

IN TA

IN TA

INTR

INT

IR3
IR4
IR5
IR6
IR7

Actually the functional block diagram of the PTC


Vcc

GND

D0-D7

RD
WR
CS
A0

INT
INTA

8259
Interrupt
inputs
IR0 IR7

Cascad
Interface
CASO CASL
SP/CN

Here eight vectored priority interrupts for the CPU. It can case cade up to 64 vectored
priority interrupts without additional circuitry. It is in NMOS technology.

Internal Block Diagram of PIC

INTA
D0 D7

RO
WR

RO

Data Bus
Buffer

Read / Write
logic

CS

CAS 0
CAS 1
CAS 2

INT
Control Logic

In
Service
Register
(ISR)

Priority
Register

Cascade
Buffer
Comparator
Interrupt Master Register (IMR)

SP / EN

Internal Bus

Interrupte
d
requested
register
(IRR)

IR0
.
.
.
.
.
IR7

8259 has 8 blocks


It has eight interrupt lines IR0 IR7
i. INT (Interrupt):
this output goes directly to process

or interrupt input and causes the processor to

send back the INTA.


ii. Interrupt request register (IRR) and Interrupt service register (ISR):
ISR to store all interrupt which are requested service, and ISR is used to store the
interrupt levels which are serviced.
iii. Priority Resolver:
priority in IRR. During INTA pulse highest priority is called
iv. Interrupt Mask Register (IMR):
It will mask the particular interrupt
v. CAS 0 CAS 7:
Cascading maximum 64 interrupt pins
vi. SP/EN:
Slave program / Enable buffer (Buffer transceiver)
vii. R/W logic:
A0 determine address of register. RD, WR means for read and write
III. Interrupt sequence of an 8086 based system.
80 x 86 family interface with 8259

IR0

ISR

PR

IRR

IMR

IR7

By select is possible by IMR among IR. The needed IR n only selected. If so many priority
with help which IR should be selected.

Essay question:
1. Interface 8086 to 8259?
2. Explain 8259?
3. Draw the block diagram of 8259.
Ans:
Day XXIX
Objective types
1. 8259 is __________
i. PIC ii. PPC
2. 8259 has _________
i. IR0-IR7 (8 interrupt)
ii. 4 interrupt
3. By cascading more numbers of 8259 is giving _______ pins
i. 8 pin
Result Analysis
1. i

2. i

3.ii

ii. 64 pin

i. Serial Communication Principle:


instead of parallel communication which is complicated is replaced by serial
communication
i. Simplex communication:
Data flows only one connection (eg Processor to Printer)
ii. Half Duplex:
Both can communicate but at a time only one eg (Walkie Talkie)
iii. Full Duplex:
Both (or) communicate at any time (PC common)
DMA (Direct Memory Access)
Data transfer between peripherals and memory is a frequent activity in any computer.
Direct memory access means the data can be transferred between peripheral and memory
without the intervention of the processor

CPU

I/O

DMA

This is called cycle stealing


Hence DMA cycle timing

CLK
HOLD

DMA cycle

Or T1

T4

HOLD A

1. DMA controller
The Central dogma is transferring data in one of the following cases.
i. From memory to a peripheral
ii. From peripheral to memory
iii. From memory to memory DMA operation.

Address
Bus

Address
8086 CPU

Data
Data
Bus

Hold P
Hold

Bus
Control
Bus

Memory

Control
Bus
HRa
Data
Bus

DMA
Controller
HLDA

Control
Bus

Peripheral
Device

There must be a DMA controller to coordinate all the activities.


DMA Controller attributes:
The general block diagram of DMA controller

DRQ 0
Data Bus
Buffer

Counter
Channel
DACK
0

I OR
I OW

clk

Channel 1

Read / Write
logic

A0
.
A3

A4
A7

Channel 2

Control
logic and
mode set
register

Channel 3

Priority
Resolve

Not only block diagram says channel but also priority resolver.

8257 interfaced with 8086


I/O mapped I/O:
It is on I/O Interface

A0 A19
D0 D7
8086

RD
WR
IO / M

I OR
IOW
MR
MW

Decoder

MW
MR

I OR
IOW

Dev 0

8257
Dev 1

HOLD
HOLD A
Clk

Dev 2

Dev 3

A4
.
.
.
A15

CS

8257 interface memory mapped I/O:

A0 A19
D0 D7
8086

RD
WR
IO / M

I OR
IOW
MR
MW

Decoder

Dev 0

Dev 1
8257
Dev 2

Dev 3

A1
A2
.
A15

In I/O Mapped I/O Address IOR, IOW


In Memory Mapped I/O MR, MW

CS

Question and Answer


1. Define Simplex communication?
Ans: Data flows only one direction
Example: Processor to printer
2. Define Half duplex?
Ans: Both can communicate but a time only one eg (Walkie Talkie)
3. Define full duplex?
Ans: Both can communicate in both direction. Eg (PC Communication)
4. What is DMA?
Ans: Direct Memory Access means the data can be transferred between peripheral and
memory without the intervention of the processor. This is called cycle stealing.

CPU

IO

Essay Question
1. Explain the DMA connection?
2. Explain the block diagram?
3. 8257 (DMP) interfaced with 8086?

Objective Question:
1. DMA is _____________
i. Direct Memory Access

ii. No such

2. DMAs process is __________


i. none

ii. Cycle stealing

3. Example for simplex common ___________


i. Process to printer

ii. Printer to Kbd

4. Walkie Talkie works under __________i. Simplex

ii. Half duplex

5. Both direction communication at a time is ________i. Simplex

ii. Full duplex

6. What is the chip number for DMA? _______


i. 8257

ii. 8255

Result Analysis
1. i.

2.ii

3.i

4.ii

5.ii

6.i

If your score greather than 5 then go to step XXXI

ANNEXURE
UNIT III
INTERFACING

1. Design the control word register (CWR) to configure the ports of an 8255 chip in
Mode 0, with Port A and PC u as as inputs and Port B and Port C lower (PC L) as
output?
Ans:
We know that 1 input, 0 output. According to CWR
9

1
Mode
selection

0
PC
PB
Mode
Solution

Port A
Port C upper

The CWR is 98H


2. General a square wave of 33 % duty cycle at the lowest bit of port A. The clock
frequency of the processor is 4.77 Mhz?
Am
PA

EQU 0C0

CR

EQU OC6

MOV AL,

80H

OUT CR,

AL

LOOP1:

MOV AL,

OUT PA,

AL

CALL Delay
MOV AL,

FFH

OUT PA,

AL

CALL Delay
JMP

LOOP 1

/
OOH

(WR

P, O/P)

Delay NOP
NOP
RET
END
Explanation:
00

The output it 00 port given


The next command if FF port gives
1 1 1
1

1 1 1
1
F

1111
F

So

1111 1111

F
F
0 0 0
0

3. Stepper Motor:

A
C

09 H

05 H

06 H

0A H

This is clockwise rotation


If you reversely keep the data anti clockwise rotation
Ans:
CR

EQU OC6 H

PB

EQU OC2 H

MOV AL

80 H

OUT CR,

AL

MOV AL,

66H

LOOP OUT PB,


ROR AL,

AL
1

CALL Delay
JMP

LOOP

Delay NOP
NOP
RET
END
4. Write into the base register and count register of channel 1, given that 4KB of data are to
be transferred from a memory location 1323 HO to C peripheral?
Ans:
MOV AL,

30H

OUT OC2H,
MOV AL,

AL
32H

OUT OC2H, AL
MOV AX,

4096

OUT OCO3H, AL

MOV AL,

AH

OUT OCO3H,

AL

UNIT IV
Unit IV
MICRO CONTROLLER
Architecture of 8051 Special function register (SFQS) I/O pins, ports and circuits
Instruction set Addressing mode Assembly language programming.

Introduction:
Definition of Microcontroller:
It is single chip computer.
The difference between microprocessor and micro controller is
Microprocessor General Purpose
Data bus

CPU
GPR

RAM

ROM

I/O
ports

Timer

Serial com
port

Address Bus

Micro controller
CPU RAM
C/O Timer

ROM
Serial

Com

port
Architecture of 8051:
i. History:
In 1981 intel launched 8 bit micro controller. It has 128 byts of RAM 4 kb of ROM,
two timers, one serial port, and four ports all in a single chip. Another name is system on a
chip. If more than 8 lines comes it is cut into the from of 8 bit lengths.
8051 MCS 51 Microcontroller
8052 MC (8051 + 128 bytes RAM + timer)
8031

MC

8051 Analysis
Attribute
ROM
RAM
Timers
I/O pins
Serial Port
Interrupt sources

8051
4k
128
2
32
1
6

8052
8k
256
3
32
1
8

8031
0k
128
2
32
1
6

Architecture 8051 is

Reg
ister A

Te
mp reg

S.P

Latch 0
Buffer 0

.
.
.

P.
Counter

Te
mp reg

PC
Incrementer

Latch 1
Buffer 1

Port 1
O/P driv

.
.
.

DPTR

A
LU

Latch 2
Buffer 2
R
A
ddress
register

Pr
ogram
A
ddress
register

P
SW

Port 0
O/P driv

AM

Latch 3
Buffer 3

Port 2
O/P driv

.
.
.

Port 3
O/P driv

.
.
.

A
LE

SP

Ti
ming
and
R
Control

AM

O
SC

OM

I
R

P
S
CON T CON T
H0 S H1 I
BUF
E

T
MJD T
L0 T

T
CON T
L1

Special function
register 5

Interru
pt, serial
port, timer
and mr/mw
control

-CPU

1. I/O ports:
4 I/O ports
Port 0 (8 bits)
Port 1 (8 bits)
Port 2 (8 bits)
Port 3 (8 bits)
2. Register Set:
It is meant for storing data. They include

B7

i.

Accumulator

ii.

B register GPR to multiply and divide

iii.

PSW
B6

B5

B4

B3

B2

B1

B0

Parity
Reserved
Overflow

Bank 0 - 3

Flag zero
Auxiliary carry
Carry flag

F Stack and Stack pointer

Top
Stack

PUSH:
SP = SP 1
(Stack Pointer)
POP:
SP = SP + 1
G DPT:
It is 16 bit so it must be bifurcated
DP (H)

DP (L)

Special function register

of

Memory organization in 8051:

ROM/EPROM

PSEN

It is read only memory


RAM
FFFC

0001

RD

WR

Read and write in a memory.


C. I/O pins, ports and C.
i. External Program memory:

P1

P3

8
0
5
1

PU

D0
L
A
T
C
H

P2

D7
A0
A ROM
7

A8

A15

If frequency = 1/12 x frequency


i.e. if crystal frequency 12 MHz then clock frequency is
= 1/12 x 12 MHz
= 1 MHz

8051 full duplex communicate


Mode 0 :
8 bits transmitted

Mode 1 :
10 bits transmitted start + 8 bit + stop
Mode 2 :
11 bits are transmitted start + 8 bit data + Programmable data bit + stop
Mode 3 :
11 bits are transmitted

ALC

WR

Port 0
A0-A7

MOV X,

A,

Extend
memory

@ R
data

Timer / Counters and their program:

Data
out

A0-A7

2 Timers (Timer 0 & Timer 1)


It counts m/c cycle

GL

E0

ES

ET1

E1X

ET0 E X0
Enable
interrupt
Enable timer 0
Enable
interrupt

External

Enable timer 1
Serial port Control bit
Reserved
Enable all control
bit

Pin diagram of 8051

Vcc

P1.0

Port
1

.
.

P1.7
RST
P3.0

Port
3

P0.0

.
.

.
.
P3.7
GND

8057

P0.7

Port
0

EA
ALE
PSEN
P2.0
.
.
P2.7

Port
2

internal

Internal RAM has


i.

Working register

ii.

Bit addressable register

iii.

GPR

Working Register

Bank 3

Bank 2

Bank 1
R7

Bank 0

.
.
.
R0
8 bit

Similarly 16 bit is bifurcated into 2 eight bits

Questions and Answers


2 Mark questions
1. Define Microcontroller?
Ans:
A single chip computer. Eg. 8051
2. What are the ports in 8051?
Ans:
Port 0 (8 bits)
Port 1 (8 bits)
Port 2 (8 bits)
Port 3 (8 bits)
Essay question
i.

Architecture of 8051?

ii.

Compare 8051, 8052, 8031

iii.

Explain 8051 interface with ROM?

iv.

Explain Timer

v.

Explain pin diagram of 8051

Objective questions
1. A single chip computer is _______i. Microprocessor

ii. Microcontroller

Push
Pop

2. _______ year intel launched 8 bit micro controller


i. 1982

ii. 1981

3. Initial 1981 microcontroller contains ___________


i. 128 byte of RAM, 4kb ROM, 2 times, 4 Ports
4. Register sets are _________
i. Accumulatorii. Accumulator, B register, PSW
Result Analysis
1. ii

2. Ii

3. I

4. ii

ii. Nothing

Instruction Set
(8051)

Data
Transfer

ADD
MOV
(Immediate)
MOV
(Register)

Immediat
e
Register

Flag affecting
Jmp (Uncondition)
Instruction
Label
ADD
JZ
Registe
r

ADDC

JNZ

SUB

JC

SUBB

JNC

MUL
DIV
RAC
RLC
ANL C, bit
ORL c,
bit

Stack

Conditi
on

I/O Port
Push
Pop

Call
sub
routine

MOV A,
P0
(Input
Port)
MOV
P0 , A
(output
Port)

Registers:
In 8051 the most widely used register is accumulator, B, R 0, R1, R2, R3, R4, R5, R6, R7,
DPTR, and program counter.
MOV Instruction:
Here it is
i. Immediate instruction:
MOV 5511
Here 55 is the data transferred to accumulator.
ii. Direct MOV instruction:
MOV R0, A
A is accumulator content of A goes to R0
iii. ADD instruction:
ADD A, B
Here register
(A) (A) + (B)
Content of
This is direct for immediate
ADD A, 32H
32 is added with A stored in A
3. Label:
(Label) mnemonic [operands] (comments)
Here

SJMP HERE

PSW (Program Status word)

AC

F0

RS

RS

OV

P
Parity

GPR
carry

Auxiliary
carry

Over flow flag


Register Bank

V) Flag affecting instruction :


i. ADD
ii. ADD C
ADDC

A, B

(A) (A) + CB + CY
A
B

10
11

ii. SUB
eg. SUB

A, B

(A) (A) (B)


(B) 10-11= 1
iii. SUB B:
SUB B

A, B

(A) (A) (B) Borrow


iv. MUL: Multiply
MUL A,B
(A) (A) * (B)
DIV

A, B

(A) Quotient
(B) Remainder
vi. RRC:
C
Y

vii. RLC:
C
Y

ix) ANL C
AND Operation:
A

A
0
0
1
1

B
0
1
0
1

G
0
0
0
1
A

A
0
0
1
1

ix.

B
0
1
0
1

G
0
0
0
1
Conditiona
l

Jump

Uncondition
al

a. Unconditional:
JMP

2000

b. Conditional Jump:
i. JZ

Jump ON zero

ii. JNZ -

Jump non zero

iii. JC -

Jump on Carry

iv. JNC-

Jump no carry.

Stack:
PUSH mechanism to enter the data
POP mechanism to rewrite data
x. CALL:
Call subroutine
MAIN:
.
.
Call
1
.
.
Reset

sub

Nested Sub routine:


MAIN
Call
1
.
.

sub

Call
2

sub
.
.

Reset 2
Reset 1

xii) I/O port operation:


Port is carry for input port
MOV A, P0
Port 0
From output port
MOV P0, A

Question and Answer:


2 Mark question:
1. In 8051 what are the most widely used register?
Ans:
Accumulator, B, R0 R7, DPTR and PC (Program Counter)
2. What is immediate instructed?
Eg:
MOV 66 H
Here 66 is data transferred to accumulator
3. Define PSW?
Program status work.
4. Flag affection, Instruction.
Ans:
i.

ADD

ii.

ADDC (Add with carry)

Similarly
i.

SUB

ii.

SUB B

5. What are the two jump in 8051?


i.

Conditional, Unconditional jump

ii.

No Jump command

Essay question:
i.

Explain the instruction set of 8051 microcontroller?


Ans:
XXXII

Addressing
modes

Immediat
e

Register

Direct

Stack
direct

i. Immediate addressing mode:


Source operand is a data (constant). For example

MOV A,
Opcod
e

25 H

Operand 1
destination

Operand 2
(source)

Opcode Instruction Code

Source
Operand
Destinati
on

MOV DPTR, 4251 H


DPTR:
Data pointer it is 16 it size. So data 4251 is 16 bit
2. Register Addressing Mode:
To manipulate the data
MOV A, R0
And
ADD A, R7
Etc.
Similarly

Register
indirect

Indexed

MOV DPRT 1550 H


MOV R7, DPL
MOV R6, DPH
3. Direct Addressing Mode:
Content out of it is accessed.
MOV R0, 40 H
Content of 40 accessed and moved to R0
MOV A, B
(A) (B)
Special function register is selected for store
4. Stack and direct addressing mode
PUSH 04
Register R04 is push on stack
POP

03

Register R03 is popped out


5. Register indirect addressing mode:
Content of content is addressed.
MOV A, @ R0
Content of R0
We can map much memory
6.

Indexed addressing mode


MOV C

A, @ A + DPTR

Question and Answers


Essay question:
1. Discuss different types of addressing modes in micro controller 8051?
Ans: XXXIII

PROGRAMING THE 8051


MICROCONTROLLERS
(UNIT IV)
ANNEXURE

8051 has following flavours


ORG 1000 H
MOV R5,

25 H

MOV R7,

34 H

MOV A, 0
ADD R5
ADD R7
ADD A,
HERE:

12 H

SJMP HERE
END

Just anatomy about the program. Starting address is 1000. Immediate data transfer is R 5
25H.
Similarly R7 34H Accu 0
ADD R5

RDD A,

R5

SJMP HERE IS 1001 Destinatio Source


n

Example 1:
Use assembler direction to place constant OFCH, 05H, 76H, 28 D and character string
MAS in consecutive program memory location beginning from the location 0050 H?
ANS:
ORG 5000
DB

OFCH, 05H, 76 H, 28 D

DB

MAS

So it has data address


5000

FC

5001

05

5002

76

5003

1C

5004

4D;

ASCII of M

5005

41;

5006

53;

Example 2:
Multiply 25 by 20 using the technique of repeated addition?
Solution:
25 X 20

= 500

MOV A,

#0

ADD R2,

#? 0

AGAIN

ADD A,

#25

DCR R2,
DJNZ R2

AGAIN

MOV R4,

Example 3:
Write a program to determine if the content of R1 is EE, if so move EEL to R5?
Ans:
MOV A,
INC

A,

IF

R1

MOV R5,

R1
==

F0

EEL

Example 4:
Multiply OECH by 20 H using repeated addition
Ans:
MOV R1,

#0

MOV A,

#0

MOV R0,

20 H

AGAIN

ADD A,

JNC

HERE

INC

R1

HERE DJNZ R0,

OECH

AGAIN

MOV R0, A
Example 5:
Show the stack and stack pointer for the follow
MOV R6,

#20 H

MOV R1,

#10 H

MOV R2,

#OF FH

PUSH 6

PUSH 1
PUSH 4
Solution:

Start
Sp

07
00

Addres
s
OA

Sp = 8

0A

09
08

Sp
OA

00

00

09

09

08

09

Sp = 9

20

08

10
20

0A
FF
09

10

08
20

Example 6:
POP

3;

POP stack into R3

POP

5;

POP stack into R1

3
5

POP
3

POP
5

While PUSH instructions to push the content of the register on stack after the execute of the
following
Example 7:
Write a program to add first 5 natural number?

Solution:
MOV A,

#0

MOV R3,

#05

MOV R0,

#0

LOOP 1

INC

R0

ADD A,

R0

DJNZ R2,

LOOP 1

MOV 1000, A
Example 8:
Write a program to complement the accuracy for time?
Ans:
MOV A,

#50 H

MOV R3,

10

LOOP1

MOV R2,

LOOP2

CPL

#7

DJNZ R2,

LOOP 2

DJNZ R3,

LOOP 1

Example 9: Write a program to determine the content of R0 is FF. If so move


Ans:
MOV A,
INC

A,

JNZ

NEXT

MOV R4,

R0

OFF H

Example 10:
Multiply OFF by repeated addition?
Ans:

L1

MOV R1,

#20

MOV A,

#0

MOV R0

#25

ADD A,

#OFF H

JNC

L2

DCR R1
L2

DJNZ R0,

L1

FF to R4

MOV R0,

Example 11. Write a program to toggle all the bits port 1 by sending to it the values FFH and
AAH continuously. Put the time delay between each data port.
ORG 0
L1

MOV A,

#FFH

MOV P1,

LCALL

DELAY

MOV A,

#AAH

MOV P1,

L CALL

DELAY

SJMP L1
ORG 300
DELAY

MOV R5,

# OFF H

AGAIN

DJNZ R5,

AGAIN

RET
GND
Example 12: Port 0 as input? Write a program to send P0 to P1
Ans:
MOV A,

#OFFH

MOV P0,

BACK MOV A,

P0

MOV P1,

SJMP BACK
Example 13: Two numbers are stored in R2, and R3. Verify their sum is greater than EEH?
Ans:
MOV A,

RL

ADD A,

R3

SUB

A,

FF

JNP

LOOP

MOV A,

#4

MOV P,

LOOP NOP
END
Example 14:
In RAM location 40 44 has the following values find sum store in 45th location?
Ans:
MOV R0,

#40

MOV R2,

#5

CLR

MOV R7,
LOOP ADD A @
INC

A
R0

R0

DCR R2
JNZ

LOOP

Example 15:
i.

Two 16 bit addition?

Ans:
MOV C,

#0;

MOV A,

#45 H

ADD A,

#OE CH

MOV R0,

MOV A,

#02 H

ADD C

A,

MOV R1,

#0F CH

Example 16: Sub 45 from 65


Ans:
MOV C,

00

MOV A,

#45H

MOV B,

#65 H

SUB B A,

Example 17: Multiply two numbers


Ans:
MOV A,

#10H

MOV B,

#20 H

MOV A,

Example 18:
Division of two numbers
Ans:
MOV A,

#061

MOV B,

#03

DIV

A,

MOV P1,

MOV P2,

Example 19:
Use logical
Ans:
MOV A,

#4 H

AND L

A,

OR L A,

OEH; A

XRL

OEH;

A,

OEH; A
OR

Example 20:
Find the 2s complement of 75H
Solution:
MOV A,
CPL

#75 H

ADD A,

#1

Example 21:
Use rotate right
Ans:
MOV A,
RR

A,

#3AH
;

0011

1010

0111

0100

It is used in serial to 11p conversion.

AND OE
OE

Unit V
Interfacing microcontroller
Programming 8051 Timers Serial port programming Interrupt programming LCD &
Keyboard interfacing ADC, DAC & sensor interfacing External memory interface
stopper motor and waveform generation.

8051 has two timers / counters


Timer 0 Registers:
TLO Low byte
Timer 1 Registers:
THO High byte register
TL1 Timer 1 low high
TH1 Timer 1 high byter
TMOD (timer mode) register:
8 bit register lower
4 bit for timer 0 higher
4 bit for timer 1
M0 and M1 select the timer mode
Clock / Timer
Delay generator or an event counter
TCON: Timer / Counter Control register
II Interrupts programming:
Interrupt Vs Polling:
Interrupt is called then only CPU suspends the job.
Polling always CPU checks.
Interrupt can use many devices.
Interrupt works under priority where as polls is not.
Polling it checks round robin.
ISR
Interrupts service routine steps in executing an interrupt
1. It saves next instructions address in stack
2. Save current status of all interrupts
3. It jumps to ISR and IVR also
4. RET 1 instruction returns to PC
Interrupts vector table 8051 interrupt
i.

Reset

ii.

External hardware interrupt 0

iii.

Timer 0 interrupt

iv.

External hardware interrupt 1

v.

Timer 1 interrupt

vi.

Serial com interrupt

Enabling and Disabling interrupt


Enabling unmasking the interrupt
Disabling masking the interrupt
EA Enable All
Steps in EI:
E0

ET

ES

ET1

E1X

ET0 E X0

Enable
or
disable
external interrupt
timer
overflow
Interrupt 1
timer 1
Serial port
Timer 2

Programming Timer Interrupts


Roll over timer flag and interrupt
Programming External Hardware Interrupt:
EI INTO and INT 1
Level triggered interrupt
Sampling the low level triggered interrupt
Edge triggered interrupts
Sampling edge triggered interrupt
DAC Digital to Analog interfacing

RD
0808

WR
D0

D2

8051

This DAC is
V = RI
I = V/R

I0

Vref A1
A
A

2 ...... 8
4
256
Rref 2

So
Re
f

S7

Vref

A8

V0

So

D0

S7

DAC

8051
A8

D7

V0

ADC:
Analog to digital conversion

ADC
0804

Digital
output

Analog
interfa
ce

Interfacing Kpd

Port
0
8051

Scan
lines

External memory interface


4K x 8 interface with 8051

D
A11
.

A12
A13

A0

CS

A14
A15

MR
MW

4k x 8
RAM

PSEN:
Program store enable stepper motor interfacing.
Stepper motor converts electrical pulses to mechanical movements.
A

D
B

Rotor
A B
1 0
0 1
0 1
1 0

C
0
0
1
1

D
1
1
0
0

=
=
=
=

09
05
06
08

Question and Answers:


2 Mark question
1. 8051 Define timers in 8051?
Ans:
It has two timers / counter
2. Define DAC?
Ans:
Digital to Analog converter
V = RI
I0

Vref A1
A
A

2 ...... 8
4
256
Rref 2

Essay question:
1. Discuss 8051 Timer / Counter
2. Discuss interrupt Vs Polling
3. Discuss ISR, IVT
4. Explain enabling, disabling interrupt
5. 8051 interfacing with DAC and ADC?
6. 8051 interfacing with keyboard
7. 8051 external memory interface?
8. How stepper motor function clockwise?
Ans:
Day XXXIV
Objective question
1. 8051 has ________timer ________counter
i. 2 , 2 ii. 2 , 3
2. TMOD register ________
i. Timer mode ii. Non timer mode
3. TCON is _________
i. Timer
4. EI is ___________

ii. Timer / counter control register

i. Enabling interrupt ii. Disabling interrupt


5. DAC chip number is ________
i. 0803 ii. 8051
6. ADC chip number is _________
i. 0804

ii. 8051

7. keyboard has 8 interface with 8051 has _______


i. Return line scan line

ii. Scan line

Result Analysis
1.i 2. i
All the best.

3. ii

4. i

5.i

6.i

7.i

ANNEXURE FOR
UNIT V
8051 INTERFACING

1. How many address lines required for K RAM, 4 k PROM, 8 k EPROM.


Ans:
A0-A8 = 9 address lines
29 = 0.5 k RAM = RAM
If i add one address line
A0-A9=10 address lines
It can may = 1 k
A0-A10 = 2 k
A0-A11 = 4 k
A0-A12 = 8 k
2. If 512 x 8 bytes is possible 256 x 4 bytes?
Ans:
256 lines = A8 lines

A0-A7

RAM
256 x 4

D0D5

A0A3

RAM
256 x 4

D4D2

3. Draw the block diagram for 4 k x 8 interfacing 8051?


Ans:

8051

P00
P07

D0
D7
A0

MR
MW

A11

A12
A13

4k x 8 RAM

A14

CS

A15

4. Stepper Motor interfacing for clock wise and anti clockwise what is the interface?
Ans:
A

D
B

Clock wise
A
1
0
0
1

B
0
1
1
0

C
0
0
1
1

D
1
1
0
0

=
=
=
=

09H
05H
06H
0AH

For anti clock wise 0a, 06, 05 and 09


5. What are the main steps to generate a square wave by 8051 interface?

Ans:
Initialize port 0
LOOP MOV A,
OUT P0,

OOH
A

CALL DELAY
MOV A,

FF

OUT P0,

JMP
END

LOOP