2

(1026 - )EEES

hudabader82@yahoo.com

ramdan19@yahoo.com

.


.


.

. (
) Flow Chart
.

. Algorithm State Machine



.

.2 Selection Sort

.
insertion

field programmable gate arrays
) (FPGAs
] [1 Vector primitives [2] .
ASM ].[3
ASM



.

( )1 A
[4][5] . n

.1

select bubble.

.1
.2 j=0
.3 j
n-1 4 13

.4 min=J
.5 i=j+1
.6 i n
7 9
.7 ) a(i)<a(min min=i
.8 i 1 6
.9 j min ) a(j )a(min
.11 j 1 3
.11
( )1

.3

Algorithm State
Machines

.


.

hardware algorithm.


[6].

.

) (ASM ) (SM
.
ASM

ASM
sequential controller
.
( )2 ASM :
) (state box ) (decision box
) (conditional box - -

.

. - -

[7][8].

-
ASM

.
.

( )2 ASM
.4

.ASM

}]{xin [0], xin [1], ...... xin [n 2], xin [n 1

n
.

}]{xout [0] xout [1] ...................... xout [n 2] xout [n 1

}]{xout [0] xout [1] ...................... xout [n 2] xout [n 1

}] {Reg[0], Reg[1], ................. Reg[n 2], Reg[n 1
.
Temp1, Temp2
LDT1, LDT2

. SelTemp

(1026 - )EEES

( )1
j i
j
LDj UPj i
LDi .UPi LDData

.5 ASM
ASM
( )1

:

( )1

S 0

OR

()3

j LDj

A Word from a
register to load into
other one

LDData

.1
LDData

r
]Reg[i
]Xout[i

Din

Dout

Sel

Clk
LD

]Reg[i+1
]Xout[i+1

0 Mux

Clk
LD

0 Mux
1 Sel

( )3 j n-1
n-1 Cj

Reg[i] Load signal

Din

Dout

Xin[i] r

( )2 j

( )4 min j
min

Xin[i+1] r

LDmin
i J Selji

Reg[i+1] Load signal

( )5 i
LDi j incrementer

( )3

min
min
.LDMin

n Ci

Muxji

min Muxji

MuxMin SelMn

j n-1 Ci
i . n Cmin
j min C
] Reg[i ]Reg[min
s

8 i
UPi
( )9 j min
Cmin
j min

.
Cj

( )7 C
min i

Selji

( )6 i n

Temp1 Temp2

( )11 j Upj

( )11

( )4 ASM ( )5

.
8 8

T0

2
T5

Upi=1

CjMin

LDData=1
LDJ=1

T1

LDTemp2=1
Selji=0
SelMin=1

T6

Cj
1

SelTemp=0
LDTemp1=1
SelMin=0
En=1

LDMin=1 Selji=0
LDi=1

Upj=1

T2

T7
1

Ci
1
Selji =1 SelMin=1
LDTemp1=1

SelTemp=1
Selji=0
SelMin=1
En=1

T3

SelMin=0

T4

C
1

LDMin=1 Selji =1
2
ASM ) 4(

 (1026 - )EEES

( )5

 ( )2

cj ci c

x
x

x
x

0
1

cu
rre
nt
To
To

0
1

x
x

T1
T1

x
x

T2
T2
T3
T3
T4

Upj

Upi

En

SelT

Selmin

Selji

LDmin

LDT2

LDT1

LDi

LDj

LDD

ne
xt

cmin

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
1

0
1

To
T1

x
x

x
x

0
0

0
0

0
0

0
0

0
0

0
0

0
1

0
0

0
0

0
1

0
0

0
0

To
T2

x
x

x
x

x
x

1
0

0
0

0
0

0
0

0
1

0
1

0
0

0
0

0
1

0
0

0
0

0
0

T1
T3

x
x

x
x

0
1

x
x

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
1

0
0
1

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

T5
T4
T5

x
x
x

0
1
x

x
x
x

x
x
x

x
x
x

0
0

1
0

0
0

0
0

0
1

0
0

0
0

0
1

0
0

0
0

0
0

0
0

T2
T6

0
1

x
x

x
x

x
x

x
x

T5
T5

T7

T6

T1

T7

.6

LDData=T0s
LDj=T0S

( )5

LDi=T1Cj

LDT1=T2Ci+T6

LDT2=T5Cmin

()4

LDmin=T1Cj+T4

Selji=T2Ci+T4

3 D

Selmin=T2Ci+T5Cmin+T7

( )1

SelT=T7

En=T6+T7

To

Upi=T5cmin

111 T1 001

Upj=T2Ci

3 8 .
D0, D1, D2
( )1 :

D0=T0S+T2+CT3+T4+T6+T7
D1=T1Cj+T2Ci+T5+T6

D2=T3+T4+T5Cmin+T6

:

[1] Rene Mueller Jens Teubner Gustavo Alonso,

"Sorting Networks on FPGAs", The VLDB Journal
manuscript No. 1
[2] Zhou J, Ross KA (2002) Implementing database
operations using SIMD instructions. In: Proc. of the 2002
ACM SIGMOD Intl Conference on Management of
Data, Madison, WI, USA
[3] Hoda B. Abugharsa, "Design Data Sorter Circuit
Using Insertion Sorting Algorithm " ICCSET 2014 : 18th
Science,

Computer

Istanbul, Turkey, March

on

Conference

International

Engineering and Technology,

24-25, 2014.

1026 - )EEES(

[4] D. De Baer, J. Paredaens "Parallel Algorithms and

Architectures", Springer Berlin/Heidelberg, 1987.
[5] Ronald L. Rivest, "Introduction to Algorithms", Second
Edition, McGraw-Hill Book Company, 2001.
[6] Morris Mano, "Digital Design", Prentice Hall, Third
Edition 2002.
[7] Sajjan G. Shjiva, Huntsville, " Introduction to Logic
Design", MARCEL DEKKER Inc, second Edition, 1998.
[8] Thomas L. Floyd "Digital Fundamentals", Prentice
Hall, July 2005.