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Basic Elements
Processor
Main Memory
I/O modules
System bus
Top-Level Components
CPU
System
Bus
PC
MAR
IR
MBR
Execution
Unit
I/O AR
Main Memory
0
1
Instruction
Instruction
Instruction
I/O BR
I/O Module
Data
Data
Data
Data
n-2
n-1
Buffers
Processor Registers
User-visible registers
Enable programmer to minimize main-memory references by
optimizing register use
User-Visible Registers
May be referenced by machine language
Index
Segment pointer
Stack pointer
Address Registers
Index
Segment pointer
Stack pointer
5
positive result
negative result
zero
Overflow
Instruction Cycle
START
Fetch Next
Instruction
Execute
Instruction
Fetch Cycle
Execute Cycle
HALT
Instruction Register
Fetched instruction is placed in the instruction register
Types of instructions
Processor-memory
Processor-I/O
Data processing
Control
CPU Registers
300
1 9 4 0
3 0 1 PC
AC
301
5 9 4 1
0 0 0 3 AC
1 9 4 0 IR
302
2 9 4 1
1 9 4 0 IR
Memory
CPU Registers
300
1 9 4 0
3 0 0 PC
301
5 9 4 1
302
2 9 4 1
940 0 0 0 3
941 0 0 0 2
940 0 0 0 3
941 0 0 0 2
Step 1
Step 2
10
300
301
302
Memory
1 9 4 0
5 9 4 1
2 9 4 1
CPU
3
0
5
Registers
0 1 PC
0 0 3 AC
9 4 1 IR
300
301
302
Memory
1 9 4 0
5 9 4 1
2 9 4 1
CPU
3
0
1
Registers
0 2 PC
0 0 5 AC
9 4 0 IR
3 + 2 = 5
940 0 0 0 3
941 0 0 0 2
940 0 0 0 3
941 0 0 0 2
Step 3
Step 4
300
301
Memory
1 9 4 0
5 9 4 1
CPU Registers
3 0 2 PC
0 0 0 3 AC
302
2 9 4 1
2 9 4 1 IR
300
301
Memory
1 9 4 0
5 9 4 1
CPU Registers
3 0 3 PC
0 0 0 5 AC
302
2 9 4 1
2 9 4 0 IR
940 0 0 0 3
941 0 0 0 2
940 0 0 0 3
941 0 0 0 5
Step 5
Step 6
11
Interrupts
An interruption of the normal sequence of execution
Improves processing efficiency
Allows the processor to execute other instructions while an
I/O operation is in progress
12
Classes of Interrupts
Program
arithmetic overflow
division by zero
execute illegal instruction
reference outside users memory space
Timer
I/O
Hardware failure
13
Interrupt Handler
A program that determines nature of the interrupt and
performs whatever actions are needed
Control is transferred to this program
Generally part of the operating system
Interrupt Cycle
Fetch Cycle
Execute Cycle
Interrupt Cycle
Interrupts
Disabled
START
Fetch Next
Instruction
Check for
Execute
Interrupt;
Instruction Interrupts Process
Enabled
Interrupt
HALT
14
15
User
Program
I/O
Program
WRITE
I/O
Command
5
User
Program
1
WRITE
WRITE
4
I/O
Command
User
Program
I/O
Program
WRITE
4
I/O
Command
2a
2
END
I/O
Program
2b
Interrupt
Handler
WRITE
3a
WRITE
END
Interrupt
Handler
5
END
3
3b
WRITE
No interrupts
WRITE
Interrupts; short I/O wait
WRITE
Interrupts; long I/O wait
16
Multiple Interrupts
Disable interrupts while an interrupt is being processed
Processor ignores any new interrupt request signals
User Program
Interrupt
Handler X
User Program
Interrupt
Handler X
Interrupt
Handler Y
Interrupt
Handler Y
17
18
Multiprogramming
Processor has more than one program to execute
The sequence the programs are executed depend on their
relative priority and whether they are waiting for I/O
19
Memory Hierarchy
Registers
Cache
Main Memory
Disk Cache
Magnetic Disk
Magnetic Tape
Optical Disk
20
Disk Cache
A portion of main memory used as a buffer to temporarily to
hold data for the disk
Disk writes are clustered
21
Cache Memory
Invisible to operating system
Word
Transfer
CPU
Block
Transfer
Cache
Main Memory
22
23
Memory
Address
0
1
2
3
Data
Block
(K Words)
Slot
Number
0
1
2
Tag
Block
Block Length
(K words)
Cache
Block
2n-1
Word
Length
Main memory
24
Cache Design
Cache size
Block size
the unit of data exchanged between cache and main memory
hit means the information was found in the cache
larger block size more hits until probability of using newly
fetched data becomes less than the probability of reusing data
that has been moved out of cache
Mapping function
determines which cache location the block will occupy
Replacement algorithm
25
Write policy
When the memory write operation takes place
Can occur every time block is updated
Can occur only when block is replaced
Minimizes memory operations
Leaves memory in an obsolete state
26
Programmed I/O
I/O module performs the action,
not the processor
Sets appropriate bits in the I/O
status register
No interrupts occur
Processor checks status until
operation is complete
27
Interrupt-Driven I/O
Processor is interrupted when
I/O module ready to
exchange data
Processor is free to do other
work
No needless waiting
Consumes a lot of processor
time because every word
read or written passes
through the processor
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