a keyboard consist of matrix of key and an embedded microcontroller the

monitor the activities of the key and sends scan code accordingly. three types
of key activities are observed:
1. when a key is press, the make code of the key is transmitted
2. when a key is held down continuously, a condition known as typematic, the
make code is transmitted repeatedly at a specific rate. by default, a ps2
keyboard transmits the make code about every 100 ms after a key has been
held down for 0.5 second.
3. when a key is release, the break code of the key is transmitted.
the make code of the main part of a ps2 keyboard is show in figure 3. it is
normally 1 byte wide and represented by two hexadecimal number. for
example, the make code of the A key is IC. this code can be conveyed by one
packet when transmitted. the make codes of a handful of special purpose
key, which are known as the extended key, can have 2 to 4 byte. a few of
these key are sow in figure 8. for example, the make code of the upper arrow
on the right is E0 75. multiple packet are need for the transmission. the break
codes of the regular keys consist of F0 followed by the make code of the key.
for example, the break code of A key is F0 1C.

oversampling procedure
the most commonly used sampling rate is 16 time the baud rate, which
means that each serial bit is sampled 16 time. assume that the
communication uses N data bit and M stop bit. the oversampling scheme
work as follows:
1. wait until the incoming signal become '0' the begining of the start bit, and
the start the sampling tick counter.
2. when the counter reaches 7, the incoming signal reach the middle point of
the start bit . clear the counter to 0 and restart.
3. when the counter reach 15, the incoming signal progresses for one bit and
reaches the middle of the first data bit. retrieve its value, shift it into a
register, and restart the counter.
4. repeat step 3 N-1 more time to retrieve the remaining data bits.
5. if the optional parity bit is used, repeat step 3 one more time to optain the
parity bit.
6. repeat step 3 M more tie to obtain the stop bits.

the oversampling scheme basically performs the function of a clock signal.

instead of the using the rising edge to indicate when the input signal is valid,
it utilizes sampling tick to estimate the middle point of each bit. while the
receive has no information about the exact onset time of the start bit, the
estimation can be off by at most 1/16.the subsequent data bit retrieval are off
by at most 1/16 from the middle point as well. because of the oversampling,
the baud rate can only be a small fraction of the system clock rate, and thus
this scheme is not appropriate for a high data rate.

the conseptual block diagram of UART receiving subsystem is shown in fig6. it

consist of three major component:
1. UART receiver : the circuit to obtain the data word via oversampling.
2. baud rate generator : the circuit to generate the sampling tick.
3. interface circuit: the circuit that provider buffer and status between the
uart receiver and the system that uses the UART.

baud rate generator

the baud rate generator generate a sampling signal whose frequency is
exactly 16 time the uart designed baud rate. the void creating a new clock
domain and violating the synchronous design principle, the sampling signal
should function as enable tick rather than the clock signal to the uart
receiver, as discus section4.
for the 19,200 baud rate the sampling rate has to be 300 tick per secon.
since the system clock rate is 50 MHz, the baud rate generator need a mod
163 counter, in which the one clock cycle tick is asserted once every 163
clock cycle. the parameterized mod m counter discussed in section 4 can be
used for this purpose by setting the M generic to 163.

mod-m counter
a mod m counter count from 0 to m-1 and wrap around. a parameterized
mod-m counter is show in listing 4. it has two generics. one is M, which
specifies the limit, m and the other is N, which specifies the number of bits
needed and should be equal to (log2 M).

the next state logic us constructed by a conditional signal assignment

statement, if the counter reaches M-1, the new value is cleared to 0.
otherwise, it is incremented by 1.
inclusion of the N parameter in the code is somewhat redundant since its
value depends on M. a more elegant way is to define a function that calculate
N from M automatically. in VHDL, this can be done by creating a user defined
function in a package and invoking the package before the entity declaration.
this is beyond the scope of this book and the detail may be found in the
reference ciied in the bibliograpi section.

tick counter.