Professional Documents
Culture Documents
August 1997
Features
Description
Ordering Information
PART NUMBER
CA3162E
CA3162AE
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
0 to 70
16 Ld PDIP
E16.3
-40 to 85
16 Ld PDIP
E16.3
Pinout
CA3162
(PDIP)
TOP VIEW
21
16 23
20
15 22
NSD
14 V+
MSD
13 GAIN ADJ
LSD
12
HOLD/
BYPASS
11 HIGH INPUT
GND
10 LOW INPUT
ZERO ADJ
BCD
OUTPUTS
DIGIT
SELECT
OUTPUTS
INTEGRATING
CAP
ZERO ADJ
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
3-5
BCD
OUTPUTS
File Number
1080.2
CA3162, CA3162A
Functional Block Diagram
V+
V+
BCD OUTPUTS
ZERO
ADJ
INTEGRATING
CAP
8
21
20
22
23
V+
15
16
14
12
3
CONTROL LOGIC
COUNTERS AND MULTIPLEX
DIGIT
DRIVE
DIGIT SELECT
OUTPUTS
HIGH INPUT 11
LOW INPUT 10
THRESHOLD
DET.
V/I
CONVERTER
REFERENCE
CURRENT
GENERATOR
BAND GAP
REFERENCE
13
GAIN
ADJ
3-6
2048
96
OSC
HOLD/
BYPASS
GATES
GND
= MSD
= LSD
= NSD
CONVERSION
CONTROL
CA3162, CA3162A
Absolute Maximum Ratings
Thermal Information
Operating Conditions
Temperature Range
CA3162E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 75oC
CA3162AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4k, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
100k to V+ on Pins 3, 4, 5
Input Impedance, ZI
MIN
TYP
MAX
UNITS
4.5
5.5
17
mA
100
-80
nA
Pins 10 and 11
-12
+12
mV
Unadjusted Gain
846
954
mV
Linearity
Notes 1 and 2
-1
+1
Count
Slow Mode
Hz
Fast Mode
Pin 6 = 5V
96
Hz
0.8
1.2
1.6
Conversion Rate
Notes 3, 4
-0.2
+0.2
0.4
1.6
mA
1.6
2.5
mA
10
V/oV
0.005
%/oC
NOTES:
1. Apply 0V across V11 to V10 . Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to
give 900mV reading.
2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include 0.5 count bit
digitizing error.
3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100k resistance must be provided
for input bias currents.
4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is,
pin 11 may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input
signal is less than 999mV, the common mode input voltage may be raised accordingly.
3-7
CA3162, CA3162A
Timing Diagram
200mV
12
5 (LSD)
PIN NUMBER
500mV
4 (MSD)
500mV
3 (NSD)
500mV
2ms/DIV.
Detailed Description
The Functional Block Diagram of the CA3162E shows the V/I
converter and reference current generator, which is the heart
of the system. The V/I converter converts the input voltage
applied between pins 10 and 11 to a current that charges the
integrating capacitor on pin 12 for a predetermined time interval. At the end of the charging interval, the V/I converter is disconnected from the integrating capacitor, and a band gap
NOTE 2
NOTE 1
The EEE or --- displays indicate that the range of the system
has been exceeded in the positive or negative direction,
respectively. Negative voltages to -99mV are displayed with the
minus sign in the MSD. The BCD code is 1010 for a negative
overrange (---) and 1011 for a positive overrange (EEE).
+5V
0.1
F
0.27F
NORMAL
8
LOW SPEED MODE:
V6 = GROUND OR
OPEN
12
14
MSD
16
HOLD:
V6 = 1.2V
NSD
a
5
f
e
b
g
c
d
c
d
13
CA3161E
BCD
OUTPUTS
11
a
f
b
g
DIGIT
DRIVERS
CA3162E
a
f
b
g
POWER
2N2907, 2N3906
OR EQUIV.
COMMON
ANODE LED
DISPLAYS
LSD
12
11
16
10
15
15
14
HIGH
INPUTS
LOW
10
13
GAIN
ADJ
R1
150
3
CA3162E
PINS
3, 4, 5
10
k
NOTES:
1. The capacitor used here must be a low dielectric absorption type
such as a polyester or polystyrene type.
2. This capacitor should be placed as close as possible to the power
and ground Pins of the CA3161E.
R2
150
CA3162E
PINS
1, 2, 15, 16
1k
75
DIGIT
DRIVER
BCD SEGMENT
DRIVERS
FIGURE 2. BASIC DIGITAL READOUT SYSTEM USING THE CA3162E AND THE CA3161E
3-8
R3
150
CA3162, CA3162A
capacitors and pull-up resistors connected to the MSD, NSD
and LSD outputs are there to shorten the digit drive signal
thereby providing proper timing for the CD4056B latches.
+5V
0.047F
16
G3
0.047F
6
4
+5V
TO MSD
OF LCD
CD4056B
3
5 7
6x
10k
0.27F
ZERO
50k
8 14
12 4
3
9
CA3162E
HOLD
5
16
15
1
+5V
0.047
F
MSD
NSD
16
G4
LSD
0.047F
0.047
F
23
22
6
4
2
21
TO NSD
OF LCD
CD4056B
20
VIN+
11
VIN-
10 13
4x
7
100k
5 7
+5V
GAIN
10k
G5
16
1
6
+5V
4
G9
G7
TO LSD
OF LCD
CD4056B
G1 - G6: CD4049UB
HEX INVERTER
G7, G8, G9: CD4023B
TRIPLE 3 INPUT NAND GATE
5 7
8
TO LCD
BACKPLANE
G8
15k
100k
3-9
0.63F
CA3162, CA3162A
CA3162E Common-Cathode, LED Display Application
Figure 4 shows the CA3162E connected to a CD4511B
decode/driver to operate a common-cathode LED display.
Unlike the CA3161E, the CD4511B remains blank for all
BCD codes greater than nine. After 999mV the display
blanks rather than displaying EEE, as with the CA3161E.
When displaying negative voltage, the first digit remains
blank, instead of (-), and during a negative or positive overrange the display blanks.
V+
DP1
100k
22k
1/
3
DP2
1/ CD4049UB
6
CD4049UB
CD4012B
1/
CD4049UB
1/ CD4049UB
6
V+
V+ 16
1.8k
CD4511B
f 15
2 C
1 B
100k
100k
V+
3 LT
g 14
4 BL
a 13
HP5082-7433
OR EQUIVALENT
1.2k
1.8k
1.2k
5 LE/STROBE b 12
1.8k
100k
100k
6 D
c 11
7 A
d 10
12
11 10
1.8k
8 GND
e 9
c3
1.8k
V+
DP1
1 B
100
k
100
k
100
k
CA3162E
c1
D 16
C 15
2 A
3 NSD
V+ 14
4 MSD
GAIN 13
5 LSD
INT 12
HIGH 11
7 GND
LOW 10
8 ZERO
DP2
c2
4
c
5
dP
6
10k
GAIN
6 BUFFERS
(1 CD4050B)
ZERO 9
V+
V+
0.27F
6 HOLD
INPUT
50k
3-10
CA3162, CA3162A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: 3% PSG
Thickness: 13k 2.5k
METALLIZATION:
Type: Al
Thickness: 17.5k 2.5k
GND
ZERO ADJ
ZERO ADJ
LOW INPUT
CA3162, CA3162A
HIGH INPUT
HOLD/BYPASS
INTEGRATING CAP
LSD
MSD
NSD
20
21
23
22
V+
GAIN ADJ
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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