Algorithms for Fault Simulation

Serial Fault Simulation

This is the simplest algorithm for simulating faults. The circuit is first simulated in the true-value
mode for all vectors and primary output values are saved in a file. Next, faulty circuits are simulated one by
one. This is done by modifying the circuit description for a target fault and then using the true-value
simulator. As the simulation proceeds, the output values of the faulty circuit are dynamically compared with
the saved true responses. The simulation of a faulty circuit is stopped as soon as the comparison indicates
detection of the target fault. All faults are simulated serially in this way. A serial fault simulator repeatedly
uses a true-value simulator. Its implemen- tation is, therefore, simple. It can simulate any fault that can be
introduced in the circuit description.Thus, apart from the stuck-at and stuck-open types, bridg- ing, delay,
and analog faults can also be simulated. For this reason, analog circuit faults are usually simulated by this
method. Also, a serial fault simulator can easily simulate all types of fault conditions, such as fault-induced
races, hazards, loss of initialization, etc., in sequential circuits, which present difficulties to other types of
simulators. For n faults, the CPU time of a serial simulator can be almost n times that of a true-value
simulator. When fault-dropping is used, the CPU time can be signif- icantly lower, especially if many faults
are detected by a few earlier vectors in the set. Its memory requirement basically amounts to that of the
true-value simulator. It has been successfully used with hardware simulators and in multiprocessing environments. However, as we will discuss next, there are more intelligent algorithms to reduce the effort of
fault simulation.

Parallel Fault Simulation

Let us assume that the circuit consists of only logic gates and we wish to simulate stuck-at faults. Also,
signals are assumed to take only binary, i.e., 0 and 1, values. Also, all gates are assumed to have the same
delay. It is under these conditions that parallel fault simulation is most effective. So, each circuit in Figure
5.14 is almost identical to the fault-free circuit, except for one line that contains a stuck-at fault. In fact, the
connectivity and individual gate functions are identical in all circuits. The idea of parallel fault simulation is
to use the bit-parallelism of logical operations in a digital computer. For a 32-bit machine word, an integer
consists of a 32-bit binary vector. A logical AND or OR operation involving two words performs
simultaneous AND or OR operations on all respective pairs of bits. This allows a simultaneous simulation of
32 circuits with identical connectivity, but with possibly different signal values. For a large number of faults,
a parallel fault simulator will process w 1 faults in one pass, where w bits is the machine word size. This
is because one bit of the word is used for the signal value of the fault-free circuit. Thus, w 1 faults are
simulated in the same CPU time as that taken by the true-value simulation. If no fault-dropping is used, a
parallel fault simulator will run about w 1 times faster than a serial fault simulator. Both simulators will gain
speed by fault dropping. In serial fault simulator, the pass is terminated as soon as the single target fault is
detected. In parallel fault simulator, all w 1 faults must be detected before a pass can be terminated.
Therefore, the serial fault simulator gains more by fault dropping.