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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
------------------------------------- Entity Declaration --------------------------------------entity top_ifft is
port( clk
: in std_logic;
-- Processing clock
reset
: in std_logic;
-- Asychronous reset signal
real_in : in std_logic_vector(15 downto 0); -- Real part of the input
data
imag_in : in std_logic_vector(15 downto 0); -- Imaginary part of the
input data
valid_in : in std_logic;
-- Input data valid signa
l
start
: in std_logic;
-- Symbol start signal
real_out : out std_logic_vector(15 downto 0); -- Real part of the outpu
t data
imag_out : out std_logic_vector(15 downto 0); -- Imaginary part of the
output data
valid_out : out std_logic
-- Ouput data valid signa
l
);
end top_ifft;
----------------------------------- Architecture begin here ---------------------------------------architecture Behavioral of top_ifft is
---------------------------------- Components declaration -----------------------------------------COMPONENT radix4_butterfly_r
port( clk : in std_logic;
-- Processing clock
reset : in std_logic;
-- Asychronous reset signal
ri0
ri1
ri2
ri3
ii0
ii1
ii2
ii3
co1
co2
co3
si1
si2
si3
ro0
ro1
ro2
ro3
io0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
in
in
in
in
in
in
in
in
in
in
in
in
in
in
out
out
out
out
out
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
std_logic_vector(15
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
downto
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
0);
--------------------
io1
io2
io3
tput1
tput2
tput3
tput4
);
END COMPONENT;
COMPONENT ram_stage1_r
port(
clk
reset
wr
Mux_sel
ne for mux
wadd
s
radd
data_in1
data_in2
data_in3
data_in4
data_out1
1
data_out2
2
data_out3
3
data_out4
4
data_out_final_real
f the output data
data_out_final_Imag
art of the output data
valid_out
);
END COMPONENT;
in
in
in
in
in
out
-- read address
-- input data1
-- input data2
-- input data3
-- input data4
-- output data
COMPONENT ram_stage3_r
port (clk
: in std_logic;
-- Processing clock
wr
: in std_logic;
-- write enable
wadd
: in std_logic_vector(5 downto 0); -- write addres
radd
: in std_logic_vector(5 downto 0); -- read address
data_in : in std_logic_vector(31 downto 0); -- input data to write in
to memory
data_out : out std_logic_vector(31 downto 0) -- output data from memory
);
END COMPONENT;
--------------------------------------------- Signals Declaration -----------------------------------signal Real_1st_in_0
: std_logic_vector(15 downto 0);
signal Real_1st_in_1
: std_logic_vector(15 downto 0);
signal Real_1st_in_2
: std_logic_vector(15 downto 0);
signal Real_1st_in_3
: std_logic_vector(15 downto 0);
signal Imag_1st_in_0
: std_logic_vector(15 downto 0);
signal Imag_1st_in_1
: std_logic_vector(15 downto 0);
signal Imag_1st_in_2
: std_logic_vector(15 downto 0);
signal Imag_1st_in_3
: std_logic_vector(15 downto 0);
signal Real_2st_in_0
: std_logic_vector(15 downto 0);
signal Real_2st_in_1
: std_logic_vector(15 downto 0);
signal Real_2st_in_2
: std_logic_vector(15 downto 0);
signal Real_2st_in_3
: std_logic_vector(15 downto 0);
signal Imag_2st_in_0
: std_logic_vector(15 downto 0);
signal Imag_2st_in_1
signal Imag_2st_in_2
signal Imag_2st_in_3
signal wr_add_1st
signal wr_en1, wr_en2
signal wr_en3
signal enable_wr_count1
signal Data_in_s
signal wr_add_s
signal rd_add_s
signal Rd_add_s_d
signal rd_add_ss
signal rd_add_ss2
signal Data_out01_s
signal Data_out02_s
signal Data_out03_s
signal Data_out11_s
signal Data_out12_s
signal Data_out13_s
signal Data_out14_s
signal enable_rd_count1
signal Data1
signal Data2
signal Data3
signal Data4
signal enable_rd_count2
signal rd_add_s2
signal rd_add_s2_d
signal wr_add_ss
signal wr_add_ss_d
signal wr_add_sss
signal wr_en_ram2
signal wr_add_ss2
SIGNAL co1, co_1_1, co_1
SIGNAL co2, co_2
SIGNAL co3, co_3
SIGNAL so1, si_1
SIGNAL so2, si_2
SIGNAL so3, si_3
SIGNAL co_2_1
SIGNAL co_3_1
SIGNAL si_1_1
SIGNAL si_2_1
SIGNAL si_3_1
type state1 is (rst, s0,
signal ps1, ns1
mux_sel_s
mux_sel_s1
Real_out1
Real_out2
:
:
:
:
signal Real_out3
: std_logic_vector(15 downto 0);
signal Real_out4
: std_logic_vector(15 downto 0);
signal Imag_out1
: std_logic_vector(15 downto 0);
signal Imag_out2
: std_logic_vector(15 downto 0);
signal Imag_out3
: std_logic_vector(15 downto 0);
signal Imag_out4
: std_logic_vector(15 downto 0);
signal ri0_s
: std_logic_vector(15 downto 0);
signal ri1_s
: std_logic_vector(15 downto 0);
signal ri2_s
: std_logic_vector(15 downto 0);
signal ri3_s
: std_logic_vector(15 downto 0);
signal ii0_s
: std_logic_vector(15 downto 0);
signal ii1_s
: std_logic_vector(15 downto 0);
signal ii2_s
: std_logic_vector(15 downto 0);
signal ii3_s
: std_logic_vector(15 downto 0);
signal ri0_s1
: std_logic_vector(15 downto 0);
signal ri1_s1
: std_logic_vector(15 downto 0);
signal ri2_s1
: std_logic_vector(15 downto 0);
signal ri3_s1
: std_logic_vector(15 downto 0);
signal ii0_s1
: std_logic_vector(15 downto 0);
signal ii1_s1
: std_logic_vector(15 downto 0);
signal ii2_s1
: std_logic_vector(15 downto 0);
signal ii3_s1
: std_logic_vector(15 downto 0);
signal enable_wr_count1_d1 : std_logic;
signal enable_wr_count1_d2 : std_logic;
---------------------- ROM declaration and initialization ---------------------------------------type rom is array(0 to 63) of std_logic_vector(15 downto 0);
constant co_11 : rom := ( x"4000",
x"3ffb",
x"3fec",
x"3fd4",
x"3fb1",
x"3f85",
x"3f4f",
x"3f0f",
x"3ec5",
x"3e72",
x"3e15",
x"3daf",
x"3d3f",
x"3cc5",
x"3c42",
x"3bb6",
x"3b21",
x"3a82",
x"39db",
x"392b",
x"3871",
x"37b0",
x"36e5",
x"3612",
x"3537",
x"3453",
x"3368",
x"3274",
x"3179",
x"3076",
x"2f6c",
x"2e5a",
x"2d41",
x"2c21",
x"2afb",
x"29ce",
x"289a",
x"2760",
x"2620",
x"24da",
x"238e",
x"223d",
x"20e7",
x"1f8c",
x"1e2b",
x"1cc6",
x"1b5d",
x"19ef",
x"187e",
x"1709",
x"1590",
x"1413",
x"1294",
x"1112",
x"0f8d",
x"0e06",
x"0c7c",
x"0af1",
x"0964",
x"07d6",
x"0646",
x"04b5",
x"0324",
x"0192"
);
constant co_12 : rom := ( x"4000",
x"4000",
x"4000",
x"4000",
x"3fb1",
x"3fb1",
x"3fb1",
x"3fb1",
x"3ec5",
x"3ec5",
x"3ec5",
x"3ec5",
x"3d3f",
x"3d3f",
x"3d3f",
x"3d3f",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3871",
x"3871",
x"3871",
x"3871",
x"3537",
x"3537",
x"3537",
x"3537",
x"3179",
x"3179",
x"3179",
x"3179",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"289a",
x"289a",
x"289a",
x"289a",
x"238e",
x"238e",
x"238e",
x"238e",
x"1e2b",
x"1e2b",
x"1e2b",
x"1e2b",
x"187e",
x"187e",
x"187e",
x"187e",
x"1294",
x"1294",
x"1294",
x"1294",
x"0c7c",
x"0c7c",
x"0c7c",
x"0c7c",
x"0646",
x"0646",
x"0646",
x"0646"
);
constant co_13 : rom := ( x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e"
);
constant co_21 : rom := ( x"4000",
x"3fec",
x"3fb1",
x"3f4f",
x"3ec5",
x"3e15",
x"3d3f",
x"3c42",
x"3b21",
x"39db",
x"3871",
x"36e5",
x"3537",
x"3368",
x"3179",
x"2f6c",
x"2d41",
x"2afb",
x"289a",
x"2620",
x"238e",
x"20e7",
x"1e2b",
x"1b5d",
x"187e",
x"1590",
x"1294",
x"0f8d",
x"0c7c",
x"0964",
x"0646",
x"0324",
x"0000",
x"fcdc",
x"f9ba",
x"f69c",
x"f384",
x"f073",
x"ed6c",
x"ea70",
x"e782",
x"e4a3",
x"e1d5",
x"df19",
x"dc72",
x"d9e0",
x"d766",
x"d505",
x"d2bf",
x"d094",
x"ce87",
x"cc98",
x"cac9",
x"c91b",
x"c78f",
x"c625",
x"c4df",
x"c3be",
x"c2c1",
x"c1eb",
x"c13b",
x"c0b1",
x"c04f",
x"c014"
);
constant co_22 : rom := ( x"4000",
x"4000",
x"4000",
x"4000",
x"3ec5",
x"3ec5",
x"3ec5",
x"3ec5",
x"3b21",
x"3b21",
x"3b21",
x"3b21",
x"3537",
x"3537",
x"3537",
x"3537",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"238e",
x"238e",
x"238e",
x"238e",
x"187e",
x"187e",
x"187e",
x"187e",
x"0c7c",
x"0c7c",
x"0c7c",
x"0c7c",
x"0000",
x"0000",
x"0000",
x"0000",
x"f384",
x"f384",
x"f384",
x"f384",
x"e782",
x"e782",
x"e782",
x"e782",
x"dc72",
x"dc72",
x"dc72",
x"dc72",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"cac9",
x"cac9",
x"cac9",
x"cac9",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c13b",
x"c13b",
x"c13b",
x"c13b"
);
constant co_23 : rom := ( x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"2d41",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf"
);
x"e8f7",
x"ed6c",
x"f1fa",
x"f69c",
x"fb4b"
);
constant co_32 : rom := ( x"4000",
x"4000",
x"4000",
x"4000",
x"3d3f",
x"3d3f",
x"3d3f",
x"3d3f",
x"3537",
x"3537",
x"3537",
x"3537",
x"289a",
x"289a",
x"289a",
x"289a",
x"187e",
x"187e",
x"187e",
x"187e",
x"0646",
x"0646",
x"0646",
x"0646",
x"f384",
x"f384",
x"f384",
x"f384",
x"e1d5",
x"e1d5",
x"e1d5",
x"e1d5",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"c78f",
x"c78f",
x"c78f",
x"c78f",
x"c13b",
x"c13b",
x"c13b",
x"c13b",
x"c04f",
x"c04f",
x"c04f",
x"c04f",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"ce87",
x"ce87",
x"ce87",
x"ce87",
x"dc72",
x"dc72",
x"dc72",
x"dc72",
x"ed6c",
x"ed6c",
x"ed6c",
x"ed6c"
);
constant co_33 : rom := ( x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"4000",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df"
);
constant si_11 : rom := ( x"0000",
x"fe6e",
x"fcdc",
x"fb4b",
x"f9ba",
x"f82a",
x"f69c",
x"f50f",
x"f384",
x"f1fa",
x"f073",
x"eeee",
x"ed6c",
x"ebed",
x"ea70",
x"e8f7",
x"e782",
x"e611",
x"e4a3",
x"e33a",
x"e1d5",
x"e074",
x"df19",
x"ddc3",
x"dc72",
x"db26",
x"d9e0",
x"d8a0",
x"d766",
x"d632",
x"d505",
x"d3df",
x"d2bf",
x"d1a6",
x"d094",
x"cf8a",
x"ce87",
x"cd8c",
x"cc98",
x"cbad",
x"cac9",
x"c9ee",
x"c91b",
x"c850",
x"c78f",
x"c6d5",
x"c625",
x"c57e",
x"c4df",
x"c44a",
x"c3be",
x"c33b",
x"c2c1",
x"c251",
x"c1eb",
x"c18e",
x"c13b",
x"c0f1",
x"c0b1",
x"c07b",
x"c04f",
x"c02c",
x"c014",
x"c005"
);
constant si_12 : rom := ( x"0000",
x"0000",
x"0000",
x"0000",
x"f9ba",
x"f9ba",
x"f9ba",
x"f9ba",
x"f384",
x"f384",
x"f384",
x"f384",
x"ed6c",
x"ed6c",
x"ed6c",
x"ed6c",
x"e782",
x"e782",
x"e782",
x"e782",
x"e1d5",
x"e1d5",
x"e1d5",
x"e1d5",
x"dc72",
x"dc72",
x"dc72",
x"dc72",
x"d766",
x"d766",
x"d766",
x"d766",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"ce87",
x"ce87",
x"ce87",
x"ce87",
x"cac9",
x"cac9",
x"cac9",
x"cac9",
x"c78f",
x"c78f",
x"c78f",
x"c78f",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c2c1",
x"c2c1",
x"c2c1",
x"c2c1",
x"c13b",
x"c13b",
x"c13b",
x"c13b",
x"c04f",
x"c04f",
x"c04f",
x"c04f"
);
constant si_13 : rom := ( x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"e782",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df"
);
constant si_21 : rom := ( x"0000",
x"fcdc",
x"f9ba",
x"f69c",
x"f384",
x"f073",
x"ed6c",
x"ea70",
x"e782",
x"e4a3",
x"e1d5",
x"df19",
x"dc72",
x"d9e0",
x"d766",
x"d505",
x"d2bf",
x"d094",
x"ce87",
x"cc98",
x"cac9",
x"c91b",
x"c78f",
x"c625",
x"c4df",
x"c3be",
x"c2c1",
x"c1eb",
x"c13b",
x"c0b1",
x"c04f",
x"c014",
x"c000",
x"c014",
x"c04f",
x"c0b1",
x"c13b",
x"c1eb",
x"c2c1",
x"c3be",
x"c4df",
x"c625",
x"c78f",
x"c91b",
x"cac9",
x"cc98",
x"ce87",
x"d094",
x"d2bf",
x"d505",
x"d766",
x"d9e0",
x"dc72",
x"df19",
x"e1d5",
x"e4a3",
x"e782",
x"ea70",
x"ed6c",
x"f073",
x"f384",
x"f69c",
x"f9ba",
x"fcdc"
);
constant si_22 : rom := ( x"0000",
x"0000",
x"0000",
x"0000",
x"f384",
x"f384",
x"f384",
x"f384",
x"e782",
x"e782",
x"e782",
x"e782",
x"dc72",
x"dc72",
x"dc72",
x"dc72",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"cac9",
x"cac9",
x"cac9",
x"cac9",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c13b",
x"c13b",
x"c13b",
x"c13b",
x"c000",
x"c000",
x"c000",
x"c000",
x"c13b",
x"c13b",
x"c13b",
x"c13b",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"cac9",
x"cac9",
x"cac9",
x"cac9",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"dc72",
x"dc72",
x"dc72",
x"dc72",
x"e782",
x"e782",
x"e782",
x"e782",
x"f384",
x"f384",
x"f384",
x"f384"
);
constant si_23 : rom := ( x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"c000",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf"
);
constant si_31 : rom := (x"0000",
x"fb4b",
x"f69c",
x"f1fa",
x"ed6c",
x"e8f7",
x"e4a3",
x"e074",
x"dc72",
x"d8a0",
x"d505",
x"d1a6",
x"ce87",
x"cbad",
x"c91b",
x"c6d5",
x"c4df",
x"c33b",
x"c1eb",
x"c0f1",
x"c04f",
x"c005",
x"c014",
x"c07b",
x"c13b",
x"c251",
x"c3be",
x"c57e",
x"c78f",
x"c9ee",
x"cc98",
x"cf8a",
x"d2bf",
x"d632",
x"d9e0",
x"ddc3",
x"e1d5",
x"e611",
x"ea70",
x"eeee",
x"f384",
x"f82a",
x"fcdc",
x"0192",
x"0646",
x"0af1",
x"0f8d",
x"1413",
x"187e",
x"1cc6",
x"20e7",
x"24da",
x"289a",
x"2c21",
x"2f6c",
x"3274",
x"3537",
x"37b0",
x"39db",
x"3bb6",
x"3d3f",
x"3e72",
x"3f4f",
x"3fd4"
);
x"3537",
x"3d3f",
x"3d3f",
x"3d3f",
x"3d3f"
);
constant si_33 : rom := (x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"0000",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"c4df",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"d2bf",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e",
x"187e"
);
------------------------------- Signals declaration -----------------------------------------------signal Real_out_sig, imag_out_sig : std_logic_vector(15 downto 0);
signal wr_en_ram3
: std_logic;
signal wr_en_ram4
: std_logic;
signal wr_en_ram5
: std_logic;
begin
------------- radix4_butterfly_r module instantiation ----------------------------------------------Inst_radix4_butterfly : radix4_butterfly_r PORT MAP
( clk
=> clk,
reset => reset,
ri0 => ri0_s1,
ri1 => ri1_s1,
ri2 => ri2_s1,
ri3 => ri3_s1,
ii0 => ii0_s1,
ii1 => ii1_s1,
ii2 => ii2_s1,
ii3 => ii3_s1,
co1 => Co_1_1,
co2 => Co_2_1,
co3 => Co_3_1,
si1 => Si_1_1,
si2 => Si_2_1,
si3 => Si_3_1,
ro0 => Real_out1,
ro1 => Real_out2,
ro2 => Real_out3,
ro3 => Real_out4,
io0 => Imag_out1,
io1 => Imag_out2,
io2 => Imag_out3,
io3 => Imag_out4
);
Real_out <= Real_out_sig(15)& Real_out_sig(15)& Real_out_sig(15 downto 2);
imag_out <= imag_out_sig(15)& imag_out_sig(15)& imag_out_sig(15 downto 2);
Data1
<= Real_out1 & Imag_out1;
Data2
<= Real_out2 & Imag_out2;
Data3
<= Real_out3 & Imag_out3;
Data4
<= Real_out4 & Imag_out4;
process(clk, reset)
begin
if reset = '1' then
ri0_s1 <= (others => '0');
ri1_s1 <= (others => '0');
ri2_s1 <= (others => '0');
ri3_s1 <=
ii0_s1 <=
ii1_s1 <=
ii2_s1 <=
ii3_s1 <=
Co_1_1 <=
Co_2_1 <=
Co_3_1 <=
Si_1_1 <=
Si_2_1 <=
Si_3_1 <=
elsif clk =
ri0_s1 <=
ri1_s1 <=
ri2_s1 <=
ri3_s1 <=
ii0_s1 <=
ii1_s1 <=
ii2_s1 <=
ii3_s1 <=
Co_1_1 <=
Co_2_1 <=
Co_3_1 <=
Si_1_1 <=
Si_2_1 <=
Si_3_1 <=
end if;
end process;
(others
(others
(others
(others
(others
(others
(others
(others
(others
(others
(others
'1' and
ri0_s;
ri1_s;
ri2_s;
ri3_s;
ii0_s;
ii1_s;
ii2_s;
ii3_s;
Co_1;
Co_2;
Co_3;
Si_1;
Si_2;
Si_3;
=> '0');
=> '0');
=> '0');
=> '0');
=> '0');
=> '0');
=> '0');
=> '0');
=> '0');
=> '0');
=> '0');
clk'event then
case ps1 is
when Rst => if wr_add_1st = 189 then -- 253
ns1 <= s0;
else
ns1 <= Rst;
end if;
when s0 => if Rd_add_ss = 63 then
ns1 <= Rst;
else
ns1 <= s0;
end if;
when others => ns1 <= Rst;
end case;
end process;
process(ps1, wr_add_1st)
begin
case ps1 is
when Rst => enable_rd_count1 <= '0';
when s0 => enable_rd_count1 <= '1';
when others => enable_rd_count1 <= '0';
end case;
end process;
-- process to generate the read address for the input data memory
process(Clk, Reset, enable_rd_count1, wr_add_1st, start)
begin
if Reset = '1' then
----- add
Rd_add_ss <= ( others => '1');
elsif Clk'event and Clk = '1' then
if Rd_add_ss = 64 then
Rd_add_ss <= ( others => '1');
elsif enable_rd_count1 = '1' then
Rd_add_ss <= Rd_add_ss + '1';
end if;
end if;
end process;
Rd_add_s <= Rd_add_ss(5 downto 0);
process(Clk, reset, Rd_add_s, Rd_add_ss2, Rd_add_s2, wr_add_ss)
begin
if reset = '1' then
Rd_add_s_d <= ( others => '1');
Rd_add_s2_d <= ( others => '1');
wr_add_ss_d <= ( others => '1');
elsif Clk'event and Clk = '1' then
Rd_add_s_d <= Rd_add_ss;
Rd_add_s2_d <= Rd_add_s2;
wr_add_ss_d <= wr_add_ss;
end if;
end process;
-- *****************************************************************************
**********
-- process to assign next state to present state
Process(Clk, reset)
begin
if Reset = '1' then
ps2 <= Rst;
elsif Clk'event and Clk = '1' then
ps2 <= ns2;
end if;
end process;
--state machine for the genration of write enable signal to write the butterfly
output after first stage of processing
-process(ps2, wr_add_1st, wr_add_ss)
begin
case ps2 is
when Rst => if wr_add_1st = 189 then -- 253
ns2 <= s0;
else
ns2 <= Rst;
end if;
when s0 => if wr_add_ss = 254 and wr_add_1st = 189 then
ns2 <= s0;
elsif wr_add_ss = 254 then
ns2 <= rst;
else
ns2 <= s0;
end if;
when others => ns2 <= Rst;
end case;
end process;
process(ps2, wr_add_1st)
begin
case ps2 is
when Rst => enable_wr_count1 <= '0';
when s0 => enable_wr_count1 <= '1';
when others => enable_wr_count1 <= '0';
end case;
end process;
-- generating the write address for the second stage data
process(Clk, Reset, enable_wr_count1, start, wr_add_ss)
begin
if Reset = '1' then
wr_add_ss <= ( others => '1');
wr_en_ram2 <= '0';
wr_en_ram3 <= '0';
wr_en_ram4 <= '0';
wr_en_ram5 <= '0';
elsif Clk'event and Clk = '1' then
wr_en_ram2
<= enable_wr_count1_d2;
wr_en_ram3
<= wr_en_ram2;
wr_en_ram4
<= wr_en_ram3;
wr_en_ram5
<= wr_en_ram4;
if enable_wr_count1 = '1' then
<=
<=
<=
<=
<=
<=
<=
<=
Data_out11_s
Data_out11_s
Data_out12_s
Data_out12_s
Data_out13_s
Data_out13_s
Data_out14_s
Data_out14_s
(31
(15
(31
(15
(31
(15
(31
(15
downto
downto
downto
downto
downto
downto
downto
downto
16);
0);
16);
0);
16);
0);
16);
0);
-- process to generate the final read address for the output of the FFT
Process(Clk, reset)
begin
if Reset = '1' then
ps3 <= Rst;
elsif Clk'event and Clk = '1' then
ps3 <= ns3;
end if;
end process;
process(ps3, Rd_add_s2, Rd_add_ss)
begin
case ps3 is
when Rst => if Rd_add_ss = 62 or Rd_add_ss = 63 then -- 255 or Rd_add_ss
= 63
ns3 <= s0;
else
ns3 <= Rst;
end if;
when
when
when
when
s0
s1
s2
s3
=>
=>
=>
=>
ri1_s <=
ii1_s <=
ri2_s <=
ii2_s <=
ri3_s <=
ii3_s <=