Laboratory 4 Report

LAB4-1: DC VOLTAGE
DIFFERENT P-GAIN:

TRANSIENT RESPONSE AND DISTRUBANCE ANALYSIS WHEN THE

DC

VOLTAGE CONTROL USING

The block diagram of the system is shown below:

Fig 1a: The block diagram of the system

The transfer function of the system is derived as:
1.5M q
i
K
( K vp vi )
C
vp
s
s

s2( )
(1 i )(1
)(1 vi )
iload ( s )
i
s
s
s

1.5M q
1.5M q
v dc ( s)
i
i
1
1

(1 ) K load

(1 ) K load
C
C
sC
s
sC
s
s2 ( )
s2 ( )
i
i
1

C 2520uF ; M q 0.8981; K vp 0.05, 0.1,0.15; K vi 0.1; Ki 50; K load 1.4847; i 10000(rad / sec);

vp 24.55179, 52.4389, 79.5152(rad / sec); for different P-gains Kvp

vi 2.1774,1.01944, 0.6723 ( rad / sec); for different P-gains Kvp
The bode plots of the transfer function with different Kvp (P-gain) values are as follows:
Bode Diagram with diff erent Kvp values

60

M a g n itu d e (d B )

40
20
0

Kvp=0.05
Kvp=0.1
Kvp=0.15

-20

-40
270

P h a s e (d e g )

180
90
0

-90 -2
10

10

-1

10

10
10
Frequency (rad/s)

10

10

10

Figure 1b: Bode plot with different P-gain values of voltage control

iload ( s)
Vdc ( s )

The larger the magnitude of

, the better the disturbance rejection capability of DC voltage can be. Hence Kvp=0.05,
has better rejection capability.
The root locus of the system is found as follow:
We have closed loop transfer function as

s 2 i (1 1.5M q K load ) s
Vdc ( s )

iload ( s) Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii

Equating denominator part to zero, we get

Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii 0
1 K vp .H ( s ) 0
where H ( s)

1.5M qi s
Cs Ci s 1.5M q K vii
3

13471.5s
2520 10 s 25.20s 2 1347.15
6 3

Root Locus

3000

Im a g in a ry A x is (s e c o n d s-1 )

2000

1000

System: sys
Gain: 0.367
Pole: -9.8e+003
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 9.8e+003

System: sys
Gain: 4.68
Pole: -5e+003 + 158i
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 5e+003

System: sys
Gain: 4.67
Pole: -4.84e+003
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 4.84e+003

System: sys
Gain: 0.367
Pole: -200
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 200

System: sys
Gain: 4.68
Pole: -5e+003 - 158i
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 5e+003

-1000

-2000

-3000
-12000

-10000

-8000

-6000

-4000

Real Axis (seconds -1)

-2000

2000

Figure 1c: Root-locus of the system with the variation in the P-gain Kvp
From the root locus the system is stable for all Kvp values, except at zero.
The experimental results of the converter system for different values of Kvp are shown in figure below:
In the below figure: Green indicate DC voltage, Line current Ia indicate blue, Iqe indicate red and Iqe_command indicate
yellow.

Figure 1d: with P-gain Kvp=0.05

Figure 1e: with P-gain Kvp=0.1
Figure 1f: with P-gain Kvp=0.15
From the above three figures the settling time and overshoot of DC bus voltage is summarized in the following table I.
P-gain values
Settling time
Overshoot
Kvp=0.05
2.652s
17.8V
Kvp=0.1
4.52s
10.8V
Kvp=0.15
6.16s
7.7V
Table I Comparison table
It is observed that as P-gain increases, the settling time increases and overshoot decreases.
LAB4-2: DC VOLTAGE
DIFFERENT I-GAIN:

TRANSIENT RESPONSE AND DISTRUBANCE ANALYSIS WHEN THE

The parameters chosen are as follows:

DC

VOLTAGE CONTROL USING

C 2520uF ; M q 0.8981; K vp 0.1; Kvi 0.1, 0.2,0.3 (different I-gain values chosen);
K i 50; K load 1.4847; i 10000( rad / sec)

vp 52.4389, 51.3773, 50.268(rad / sec); vi 1.0194, 2.081, 3.19(rad / sec)

The bode plots of the transfer function with different Kvi (I-gain) values are as follows:
Using the transfer function Iload(s)/Vdc(s) with the above parameters we get bode plot as,

Bode Diagram

80

M a g n itu d e (d B )

60
40
20
0

Kvi=0.1
Kvi=0.2
Kvi=0.3

-20
-40
270

P h a s e (d e g )

180
90
0

-90 -2
10

10

-1

10

10

10
Frequency (rad/s)

10

10

10

10

Figure 2a: Bode plot with different I-gain values of voltage control

iload ( s)
Vdc ( s)

The larger the magnitude of

, the better the disturbance rejection capability of DC voltage can be. Hence Kvi=0.3,
has better rejection capability.
The root locus of the system is found as follow:
We have closed loop transfer function as

s 2 i (1 1.5M q K load ) s
Vdc ( s )

iload ( s) Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii

Equating denominator part to zero, we get

Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii 0
1 K vi .H ( s ) 0
where H ( s)

1.5M qi
Cs Ci s 1.5M q K vpi s
3

2.5

x 10

13471.5
2520 10 s 25.20 s 2 1347.15s
6 3

Root Locus

Im a g in a r y A x is ( s e c )o n d s

-1

1.5
1

0.5
0

-0.5
-1

-1.5
-2
-2.5
-3.5

-3

-2.5

-2

-1.5

-1

-1

-0.5

Real Axis (seconds )

0.5

1.5
x 10

Figure 2b (i)
Root Locus

600

System: sys
Gain: 679
Pole: -8.57 + 603i
Damping: 0.0142
Overshoot (%): 95.6
Frequency (rad/s): 603

Im a g in a ry A x is (s e c o -1n )d s

400
System: sys
Gain: 0.857
Pole: -43
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 43

200
0

System: sys
Gain: 0.857
Pole: -10.7
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 10.7
System: sys
Gain: 679
Pole: -8.57 - 603i
Damping: 0.0142
Overshoot (%): 95.6
Frequency (rad/s): 603

-200
-400
-600
-800

-600

-400

-200

-1

200

400

600

Real Axis (seconds )

Figure 2b (ii)
Figure 2b: Root-locus of the system with the variation in the I-gain Kvi i) actual ii) zoom-in view
From the root locus the system is stable for Kvi<=679. If Kvi>679, the system becomes unstable since the roots go to the right
half of the s-plane. The poles at Kvi=679 are -8.57+j603 and -8.57-j603.
The experimental results of the converter system for different values of Kvi are shown in figure below:
In the below figure: Green indicate DC voltage, Line current Ia indicate blue, Iqe indicate red and Iqe_command indicate
yellow.

Figure 2c: with I-gain Kvi=0.1;

Figure 2d: with I-gain Kvi=0.2
Figure 2e: with I-gain Kvi=0.3
From the above three figures the settling time and overshoot of DC bus voltage is summarized in the following table II.
I-gain values
Settling time
Overshoot
Kvi=0.1
4.53s
10.8V
Kvi=0.2
2.42s
9.9V
Kvi=0.3
1.974s
9.5V
Table II
From the above table, it is observed that as Kvi increases, the settling time and overshoot decreases.
LAB4-3: DC VOLTAGE TRANSIENT RESPONSE AND DISTRUBANCE ANALYSIS WHEN THE DC CURRENT CONTROL USES DIFFERENT
P-GAINS:
The parameters chosen are as follows:

C 2520uF ; M q 0.8981; K vp 0.1; K vi 0.1; Ki 40,50,60 (different P-gains for current control);
K load 1.4847; i 8000,10000,12000( rad / sec)

vp 52.4389(rad / sec); vi 1.0194(rad / sec)

The bode plots of the transfer function with different Ki (I-gain) values in current controller are as follows:
Using the transfer function Iload(s)/Vdc(s) with the above parameters we get bode plot as,

Bode Diagram

60

M a g n itu d e (d B )

40
20
Ki=40
Ki=50
Ki=60

-20
270

P h a s e (d e g )

180
90
0

-90 -2
10

10

-1

10

10
10
Frequency (rad/s)

10

10

10

Figure 3a: Bode plot for the closed loop system for different I-gain values of current controller
From the above bode plot it is observed that the magnitude of the gain of the closed loop transfer function is same for different
values of P-gain of current controller. Hence Vdc does not undergo transient changes with the change in the P-gain of current
controller. But there is small change in phase.
The root locus of the system is found as follow:
We have closed loop transfer function as

s 2 i (1 1.5M q K load ) s
Vdc ( s )

iload ( s) Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii

Equating denominator part to zero, we get

Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii 0
Ki
L
1 K i .H ( s) 0

1.5M q K vp
C 2 1.5M q K vp
s
s

L
L
0.504 s 2 26.943s 26.943
L

where H ( s)

Cs 3
2520 106 s 3
Root Locus

60

Im a g in a ry A x is (s e c o n d s-1 )

40

20

-20

-40

-60
-200

-150

-100

-50

Real Axis (seconds -1)

Figure 3b: (i) Actual root-locus

50

Root Locus
15

System: sys
Gain: 0.0129
Pole: -0.779 + 11.6i
Damping: 0.0669
Overshoot (%): 81
Frequency (rad/s): 11.7

Im a g in a ry A x is (s e c o n d s-1 )

10

System: sys
Gain: 1.38e-005
Pole: -0.437
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 0.437

-5

System: sys
Gain: 0.0129
Pole: -0.779 - 11.6i
Damping: 0.0669
Overshoot (%): 81
Frequency (rad/s): 11.7

-10
-30

-20

-10

Real Axis (seconds -1)

10

20

30

Figure 3b (ii) Zoomed in Root-locus

From the above rootlocus the system becomes unstable when the gain Ki<0.0129. The poles location at Ki=0.0129 are
-0.779+11.6j and -0.779-11.6j.
The experimental results of the converter system for different values of Ki are shown in figure below:
In the below figure: Green indicate DC voltage, Line current Ia indicate blue, Iqe indicate red and Iqe_command indicate
yellow.

Fig 3c: Ki=40

Fig 3d: Ki=50

Fig 3e: Ki=60

From the above three figures the settling time and overshoot of DC bus voltage is summarized in the following table III.
P-gain values
Settling time
Overshoot
Ki=0.4
4.52s
5.9V
Ki=0.5
3.988s
11.2V
Ki=0.6
3.48s
11.2
Table III
It is observed that as the Ki increases the settling time decreases and overshoot increases.
LAB4-4: DC
CHANGED.

VOLTAGE

TRANSIENT RESPONSE AND DISTRUBANCE ANALYSIS WHEN THE

The parameters chosen are as follows:

DC

C 2520uF , 3520uF ;(Different Values of the capacitance)

M q 0.8981; K vp 0.1; K vi 0.1; K i 50; K load 1.4847; i 10000( rad / sec)

vp 52.4389, 37.2437( rad / sec)

vi 1.0194, 1.0276( rad / sec)
The bode plots of the transfer function with different capacitance values are as follows:
Using the transfer function Iload(s)/Vdc(s) with the above parameters we get bode plot as,

SIDE CAPACITOR CAPACITANCE IS

Bode Diagram

60

M a g n itu d e (d B )

40
20
C=2520uF
C=3520uF

P h a s e (d e g )

-20
270
225
180
135
90
45
0
-45
-90 -2
10

10

-1

10

10
10
Frequency (rad/s)

10

10

10

Figure 4a: Bode plots with different values of capacitances

From the bode plot there is slight difference in the magnitude with the use of capacitance values. C=2520uF has low magnitude
response when compared to the C=3520uF. Therefore C=3520uF has better rejection capability.
The root locus of the system is found as follow:
We have closed loop transfer function as

s 2 i (1 1.5M q K load ) s
Vdc ( s )

iload ( s) Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii

Equating denominator part to zero, we get

Cs 3 Ci s 2 1.5M q K vpi s 1.5M q K vii 0
1 C.H ( s) 0
where H ( s )

s 3 i s 2
s 3 10000 s 2

1.5M q K vpi s 1.5M q K vii 1347.15s 1347.15

Root Locus

3000

Im a g in a ry A x is (s e c o n d s-1 )

2000

1000

System: sys
Gain: 5.38e-005
Pole: -5e+003 + 158i
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 5e+003

System: sys
Gain: 0.00145
Pole: -9.91e+003
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 9.91e+003

System: sys
Gain: 0.00145
Pole: -92.8
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 92.8

System: sys
Gain: 5.38e-005
Pole: -5e+003 - 158i
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 5e+003

-1000

-2000

-3000
-12000

-10000

-8000

-6000

-4000
-1

-2000

2000

Real Axis (seconds )

Figure 4b: Root-locus of the system with change in Capacitance

From the above root locus, it is observed that for all capacitance values the system is stable. Except zero capacitance.
The experimental results of the converter system for different values of Capacitance are shown in figure below:
In the below figure: Green indicate DC voltage, Line current Ia indicate blue, Iqe indicate red and Iqe_command indicate
yellow.

Fig 4c: C=2520uF

Fig 4d: C=3520uF
From the above three figures the settling time and overshoot of DC bus voltage is summarized in the following table IV
P-gain values
Settling time
Overshoot
C=2520uF
4.53s
10.8V
C=3520uF
3.795s
11.1V
From the above table it is observed that as the capacitance value increases the settling time decreases and overshoot increases.
Conclusion:
It is found that, as C (Capacitance) and Kvi (I-gain of DC voltage controller) increases settling time and overshoot decreases.
Hence it could be better to have high C and high Kvi.
It is also found that, as Ki (P-gain of current controller) increases, the settling time decreases and overshoot increases.
And as Kvp (P-gain of DC voltage controller) increases, the settling time increases and overshoot decreases. Therefore the
selection of Ki and Kvp is the compromise between the settling time and overshoot.