VHDL Synthesis for Implementing

Digital Designs into FPGAs

MSc Cristian Sisterna

UNSJ

Introduction

Very High Speed

ICs

Hardware

Description
Language
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V
H
D
L
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Hardware Description Language

HDL
(VHDL/Verilog)

FPGA

Xilinx

Altera

ASIC

Lattice

Actel

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Hardware Description Language

High level of abstraction
if(reset=1) then
count <= 0;
elsif(rising_edge(clk)) then
count <= count+1;
end if;

Easy to debug
Parameterized designs

Re-uso
IP Cores (free) available
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What is not VHDL

Verilog o VHDL IS NOT A programming language; IT IS A

HARDWARE DESCRIPTION LENGUAGE

Verilog o VHDL is not (yet) a highly abstract language:

y(n) = 0.75y(n-1) + 0.3x(n) ;
(Simulink/FPGA design flow)

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HDL Synthesis Sub-Set

Used to write code
to simulate the
behavior of a design

VHDL
VHDL
Synthesizable
Used to implement
the design into
hardware (for
instance in FPGA)

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VHDL Description Examples

x

y
sel

0
1

if(sel=1) then
z <= y;
else
z <= x;
end if;

z <= y when sel=1 else x;

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VHDL Description Ejemplos

d

clk

if(clk
)then
q <= d;
else
q <= q;
end if;

if(clk
)then
q <= d;
end if;
if(rising_edge(clk))then
q <= d;
end if;

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VHDL Module Structure

ff.vhd

entity

I/O
d

clk

q
architecture

Functionality
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VHDL Module Structure

ff.vhd
entity f
ff is
port(
d,clk : in std_logic;
q
: out std_logic);
end ff;

d
clk

architecture test of ff is
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= d;
end if;
end test;

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VHDL Code Is it really Works? ?

Test Bench

Stimulus
Signals

Tested
Signals

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VHDL Simulation / Verification

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VHDL - Synthesis
VHDL
Code

with tmp select

j <= w when 1000,
x when 0100,
y when 0010,
z when 0001,
'0when others;

Design
Constraints
NET CLOCK PERIOD = 50 ns;

NET LOAD LOC = P

Design
Attributes

Synthesis
Tool

FPGA list of
Components and
Connections

attribute syn_encoding of my_fsm:

type is one-hot;

FPGA Library
of Components
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VHDL-FPGA Design Flow

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Design Implemented in the FPGA

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FPGA Kit DE1-SoC

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=1
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FPGA Kit DE2-115

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=502
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FPGA Kit DE0-Nano-SoC Kit

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941

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FPGA Kit DE0-Nano Kit

http://www.terasic.com.tw/cgi-bin/page/archive.pl?CategoryNo=139&No=593
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FPGA Xilinx V5

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