Lab 5 Report

Design of a MOS Differential Amplifier

Kevin Bradshaw & Kai Qin
ECEN 326-502
Instructor: Sebastian Hoyos
Date Performed: March 3, 2016

Objectives
Understand the characteristics of a MOS differential amplifier.
Design and analyze two side by side common-sources and a current mirror meeting
certain constraints.
Evaluate the DC operating point of each transistor amplifiers and the transistor current
mirror.
Procedure
In this lab, the MOS differential circuit designed from the pre-lab was constructed. The
amplifier was designed to fit the constraints shown in Figure 1:
Figure 1: MOS Differential Amplifier Design Constraints

Using a chosen value for the tail current of the first MOS (M1), the small signal
parameters were found for all the transistors. Then by using the tail current and the
transistor parameters given, the gate source voltage for M4 was found. By calculating
the transconductance of M1, the drain resistances were found. By using the combined
load resistance of M1 and M2, the Common Mode Gain was found as well as the
Common Mode Rejection Ratio. Lastly, the base resistor for the current mirror was
found using the original gate source voltage for M4. Figure 2 shows the resulting circuit
designed and Table 1 shows the actual values used in the circuit. These values were
adjusted after construction in order to get an optimum gain with no clipping in the
voltage swing.

Figure 2: MOS Differential Amplifier

After the circuit was adjusted, the operating currents and voltages (including the
maximum unclipped output signal voltage amplitude) were measured and can be seen
in Table 2. Furthermore, the input resistance, current supply, and gain were measured
and can also be seen in Table 3. The differential input gain voltages can be seen in
Figure 3 and the overall output differential gain of this circuit can be seen in Figure 4.
The common mode gain can be seen in Figure 5. Lastly, the THD was measured by
using the FFT function on the oscilloscope and can be seen in Figure 6.

Figure 3: Vi, Vi2,

and Vi1-Vi2

Vi1
Vi2
Vi1 - Vi2

Figure 4: Vo1, Vo2,

and Vo1-Vo2

Vo1
Vo2
Vo1 - Vo2

Figure 5: Common
Mode Gain

Figure 6: FFT used for THD

Data Tables
Table 1: Final Design Circuit Parameters
Parameter

Value

Drain Resistors (RD)

45 k

Base Resistor (RB)

20 k
Table 2: Operating Bias Points

Parameter

Q1

Q2

Q3

Q4

Drain Current

69.5 uA

93.6 uA

0.163 mA

0.159 mA

Gate Voltage

0V

0V

3.15 V

3.15 V

Drain Voltage

-1.9 V

-0.849 V

1.54 V

3.14 V

Source Voltage

1.54 V

1.54 V

-5 V

-5 V

Table 3: Measured Circuit Values

Parameter

Value

VDD Supply Current

0.163 mA

VSS Supply Current

0.3205 mA

Offset (VO1 - VO2)

-1.051 V

Differential Gain (Adm)

12.5

Common Mode Gain (Acm)

0.176

Common Mode Rejection Ratio (CMRR)

35.18

THD

0.87 %

Maximum Unclipped Vout Signal

Amplitude

10.1 V

Discussion

The circuit we built in this lab met all the given specifications. We had a differential gain
of 12.5 which is higher than the required 10. The THD is 0.867% calculated using the
FFT measurement in Fig. 6, which is smaller than the required 5%. Also, both supply
currents are less than 0.5 mA.

Conclusion
From this lab, we have a better understanding of the characteristics of a MOS
differential amplifier, and we became more familiar with the procedures of how to design
and analyze output waveforms to meet given constraints of common mode gain and
differential mode gain. Also, we have learnt how to calculate THD from FFT
measurement of the output signal using oscilloscope.