Professional Documents
Culture Documents
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FEATURES
DESCRIPTION
AC Performance:
103dB of Dynamic Range at 4MSPS
111dB of Dynamic Range at 125kSPS
107dB THD
DC Accuracy:
3ppm INL
4mV/C Offset Drift
4ppm/C Gain Drift
Programmable Digital Filter with
User-Selectable Path:
Low-Latency: Completely settles in 2.65ms
Wide-Bandwidth: 1.7MHz BW with flat
passband
Flexible Read-Only Serial Interface:
Standard CMOS
Serialized LVDS
Easy Conversion Control with START Pin
Out-of-Range Detection
Supply: Analog +5V, Digital +3V
Power: 575mW
APPLICATIONS
PLL
DVDD
3x
Dual Filter
Path
AINP
DS
Modulator
AINN
CMOS and
LVDS
Compatible
Serial
Interface
Low-Latency
Filter
Wide-Bandwidth
Filter
Control
Data Ready
Data Output
AGND
ADS1675
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at ti.com.
UNIT
AVDD to AGND
PARAMETER
0.3 to +5.5
DVDD to DGND
0.3 to +3.6
AGND to DGND
0.3 to +0.3
100
mA
Input current
Momentary
10
mA
Continuous
+150
40 to +85
60 to +150
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
ADS1675
www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k,
unless otherwise noted.
ADS1675
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale input voltage
Common-mode input voltage
VREF
2.5
See Table 1
kSPS
AC PERFORMANCE
Data rate (fDATA)
Dynamic range
100
103
100.5
103.5
108
111
92
97
107
103
103
107
120
120
dB
dB
dB
dB
DC PRECISION
Resolution
24
23
Bits
Bits
24
(monotonic)
Bits
23
(monotonic)
Bits
Differential nonlinearity
Integral nonlinearity
Offset error
3
TA = +25C
5
4
TA = +25C
mV
mV/C
Noise
Common-mode rejection
ppm of FSR
15
%
ppm/C
71
dB
Passband ripple
Passband transition
Stop band
0.1dB attenuation
0.432fDATA
3dB attenuation
0.488fDATA
0.576fDATA
0.424fDATA
Hz
0.00002dB
dB
Hz
Hz
fCLK 0.576fDATA
Hz
86
dB
Group delay
28
tDRDY
Settling time
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3dB attenuation
Settling time
Complete settling
See Table 5
VREFP
2.75
3.0
3.5
2.75
3.0
3.5
VREFN
Short to AGND
CLOCK (CLK)
VIH
0.7AVDD
AVDD
VIL
AGND
0.3AVDD
DIGITAL INPUTS
VIH
0.7DVDD
DVDD
VIL
DGND
0.3DVDD
10
mA
Input leakage
CMOS OUTPUTS
VOH
IOH = 2mA
VOL
IOL = 2mA
0.8DVDD
V
0.2DVDD
LVDS OUTPUTS
|VOD(SS)|
340
mV
|VOD(SS)|
50
mV
VOC(SS)
|VOC(SS)|
1.2
50
mV
Peak-to-peak change in
common-mode output voltage
50
VOY or VOZ = 0V
mA
VOD = 0V
mA
VO = 0V or +DVDD
VOC(pp)
Short-circuit output current (IOS)
High-impedance output current (IOZ)
Load
150
mV
mA
5
pF
POWER-SUPPLY REQUIREMENTS
AVDD
4.75
5.0
5.25
DVDD
2.85
3.0
3.15
70
74
mA
53
59
mA
70
74
mA
510
545
mW
575
600
mW
Power-down
AVDD current
DVDD current
Power dissipation
mW
ADS1675
www.ti.com
DEVICE INFORMATION
53
52
DVDD
54
DGND
55
DGND
56
DVDD
57
AGND
58
AVDD
59
AGND
60
CLK
61
AVDD
CAP1
62
AGND
VREFN
63
CAP2
64
VREFN
VREFP
VREFP
TQFP PACKAGE
TQFP-64
(TOP VIEW)
51
50
49
AVDD
48 DVDD
AGND
47 DGND
AGND
46 DRDY
AINN
45 DRDY
AINP
44 DOUT
AGND
43 DOUT
AVDD
42 SCLK
RBIAS
41 SCLK
ADS1675
9
40 OTRA
AGND 10
39 OTRD
AGND
AVDD
11
38 CS
AVDD 12
37 START
22
23
24
25
26
27
28
29
30
31
32
DVDD
PDWN
SCLK _SEL
LVDS
DGND
LL_CONFIG
21
DGND
20
DGND
19
DVDD
18
RSV2
17
RSV1
33 FPATH
DVDD
34 DRATE[2]
DGND 16
DGND
35 DRATE[1]
DGND 15
DGND
DGND 14
DGND
36 DRATE[0]
DGND
VCM 13
TERMINAL FUNCTIONS
PIN
NAME
NO.
FUNCTION
AVDD
Analog
Analog supply
AGND
2, 3, 6, 9, 10,
54, 56, 57
Analog
Analog ground
AINN
Analog input
AINP
Analog input
RBIAS
Analog
VCM
DESCRIPTION
13
Analog
DGND
Digital
Digital ground
RSV2
21
Reserved
RSV1
22
Reserved
DVDD
Digital
PDWN
28
Digital input
SCLK_SEL
29
Digital input
LVDS
30
Digital input
(1)
Digital supply
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
NO.
FUNCTION
LL_CONFIG
32
Digital input
FPATH
33
Digital input
34-36
Digital input
START
37
Digital input
CS
38
Digital input
OTRD
39
Digital output
OTRA
40
Digital input
SCLK
41
Digital output
SCLK
42
Digital input/output
DOUT
43
Digital output
DOUT
44
Digital output
DRDY
45
Digital output
DRDY
46
Digital output
CLK
55
Digital input
CAP1
59
Analog
60, 61
Analog
62
Analog
63, 64
Analog
DRATE[2:0]
VREFN
CAP2
VREFP
DESCRIPTION
ADS1675
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TIMING CHARACTERISTICS
tLSCLKDC
tLSCLK
SCLK
tLDRPW
DRDY
tLSCLKDR
tLDOPD
DOUT
MSB
LSB
MSB
(1) High-speed LVDS valid only for DRATE = 100 and DRATE = 101.
(2) Timing shown is the single-end version of the LVDS signal pairs.
DESCRIPTION
MIN
tLDRPW
tLSCLKDR
tLDOPD
tLSCLK
tLSCLKDC
tCLK
tLCLKSCLK
tLPLLSTL
tSTCLK
tSETTLE
TYP
MAX
UNIT
tLSCLKs
ns
1.5
2.5
0.33
47
ns
tCLKs
53
31.25
ns
13
3
20
ns
80
ms
ns
tCLK
CLK
tLPLLSTL
tSTCLK
tLCLKSCLK
tLSCLK
SCLK
tSETTLE
START
tSETTLE
tLSCLKDR
DRDY
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
tCLK
tDC
CLK
tLCLKDR
tLDRPW
DRDY
CS
tLSCLK
tDRSCLK
tSPWH
SCLKinternal
tLDOPD
DOUT
MSB
LSB
Figure 3. Low-Speed Mode Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0)
DESCRIPTION
MIN
tDC
tSPWH
tCLK
31.25
tCLKDR
23
tLDRPW
tDRSCLK
tLSCLK
tLDOPD
47
TYP
MAX
50
53
15.6
ns
1
%
ns
30
2.2
ns
tCLK
4.4
1
1.9
UNIT
ns
tCLK
2.8
ns
ADS1675
www.ti.com
tLSCLKDR
DRDY
tLDRPW
CS
(1)
tCSSC
tSPW
tSPW
SCLKEXTERNAL
tLSCLK
tLDOPD
DOUT
Hi-Z
tCSRDO
MSB
LSB
tCSFDO
(3)
Figure 4. Low-Speed Mode Data Retrieval Timing with External SCLK (SCLK_SEL = 1)
DESCRIPTION
MIN
TYP
MAX
UNIT
tCLK
31.25
ns
tCLKDR
23
tLDRPW
tCSSC
ns
tLSCLK
25
ns
tSPW
12
tLDOPD
tLSCLKDR
tCSRDO
29
1
ns
tCLK
ns
10.5
15
ns
tCLK
ns
tSTART_CLKR
CLK
tSETTLE
tCLKDR
START
tSTART
DRDY
DESCRIPTION
tSTART_CLKR
tSTART
MIN
TYP
MAX
tCLK
tCLK
UNIT
0.5
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS
All specifications are at TA = 40C to +85C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5k, unless
otherwise noted.
SPECTRAL RESPONSE
(DRATE = 000, WB Filter)
0
-20
-20
-40
Amplitude (dBFS)
Amplitude (dBFS)
SPECTRAL RESPONSE
(DRATE = 000, WB Filter)
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
10
20
30
40
50
60
10
20
Frequency (kHz)
Figure 7.
SPECTRAL RESPONSE
(DRATE = 100, WB Filter)
SPECTRAL RESPONSE
(DRATE = 100, WB Filter)
60
-40
-60
-80
-100
-20
Amplitude (dBFS)
Amplitude (dBFS)
50
-20
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
100 200 300 400 500 600 700 800 900 1000
20
40
60
Frequency (kHz)
80
200
Frequency (kHz)
Figure 8.
Figure 9.
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
SPECTRAL RESPONSE
(DRATE = 101, WB Filter, Detailed View)
-20
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
-20
Amplitude (dBFS)
Amplitude (dBFS)
40
Figure 6.
-160
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (kHz)
20
40
60
80
200
Frequency (kHz)
Figure 10.
10
30
Frequency (kHz)
Figure 11.
ADS1675
www.ti.com
SPECTRAL RESPONSE
(DRATE = 101, WB Filter, Detailed View)
0
fIN = 10kHz, -6dBFS
THD = -109dBc
65,536 Points
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
20
40
60
80
200
40
60
80
Frequency (kHz)
Figure 12.
Figure 13.
SPECTRAL RESPONSE
(DRATE = 101, LL Filter)
SPECTRAL RESPONSE
(DRATE = 101, LL Filter, Detailed View)
200
-20
-40
Amplitude (dBFS)
-40
-60
-80
-100
-120
-140
-60
-80
-100
-120
-140
-160
-160
-180
-180
-200
-200
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (kHz)
20
40
60
80
200
Frequency (kHz)
Figure 14.
Figure 15.
SPECTRAL RESPONSE
(DRATE = 101, LL Filter, Detailed View)
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
0
fIN = 10kHz, -5.9dBFS
THD = -107.8dBc
65,536 Points
-20
-60
-80
-100
-120
-140
-20
Amplitude (dBFS)
-40
Amplitude (dBFS)
20
Frequency (kHz)
-20
Amplitude (dBFS)
-20
Amplitude (dBFS)
Amplitude (dBFS)
-20
-40
-60
-80
-100
-120
-160
-140
-180
-160
-200
0
20
40
60
80
200
Frequency (kHz)
Frequency (Hz)
Figure 16.
Figure 17.
2M
11
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
0
fIN = 100kHz, -6dBFS
THD = -103.2dBc
65,536 Points
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
2M
Frequency (Hz)
Frequency (Hz)
Figure 18.
Figure 19.
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
SIGNAL-TO-NOISE RATIO
vs INPUT SIGNAL AMPLITUDE
100
-20
fIN = 10kHz
80
-40
-60
-80
-100
70
60
fDATA = 2MSPS, WB
50
fDATA = 4MSPS, WB
40
-120
30
-140
20
-160
10
0
2M
-80
120
-60
-50
-40
-30
-20
-10
Figure 20.
Figure 21.
SIGNAL-TO-NOISE RATIO
vs INPUT COMMON-MODE VOLTAGE
95
fIN = 10kHz
fIN = 10kHz
fDATA = 4MSPS
WB Filter
94
110
93
100
90
fDATA = 2MSPS, WB
80
70
AIN = -0.5dBFS
92
SNR (dBc)
|THD| (dBc)
-70
Frequency (Hz)
fDATA = 4MSPS, WB
91
90
89
88
60
87
50
AIN = -6dBFS
86
40
85
-80
-70
-60
-50
-40
-30
-20
-10
1.5
2.0
2.5
3.0
3.5
Figure 22.
12
2M
90
SNR (dBc)
Amplitude (dBFS)
-20
Amplitude (dBFS)
Amplitude (dBFS)
-20
Figure 23.
ADS1675
www.ti.com
fIN = 10kHz
fDATA = 4MSPS
WB Filter
110
92.5
fCLK = 8MHz
92.0
SNR (dBc)
|THD| (dBc)
91.5
AIN = -6dBFS
105
91.0
fCLK = 16MHz
90.5
90.0
89.5
100
fCLK = 32MHz
89.0
AIN = -0.5dBFS
fIN = 10kHz
AIN = -0.5dBFS
88.5
95
88.0
1.5
2.0
2.5
3.0
3.5
10
20
Figure 24.
40
50
60
Figure 25.
POWER vs RBIAS
1100
fIN = 10kHz
AIN = -0.5dBFS
112
fIN = 10kHz
AIN = -0.5dBFS
1000
900
110
800
Power (mW)
108
|THD| (dBc)
30
RBIAS (kW)
fCLK = 8MHz
106
104
102
fCLK = 16MHz
700
600
500
100
400
98
300
96
fCLK = 32MHz
fCLK = 16MHz
200
fCLK = 32MHz
94
fCLK = 8MHz
100
0
10
20
30
40
50
60
10
20
RBIAS (kW)
30
40
50
60
RBIAS (kW)
Figure 26.
Figure 27.
105
110
|THD|
100
fIN = 10kHz
AIN = -0.5dBFS
fDATA = 4MSPS
WB Filter
95
SNR
108
LL Filter
106
WB Filter
104
Input Shorted
fCLK = 32MHz
125kSPS: DRATE = 000
250kSPS: DRATE = 001
500kSPS: DRATE = 010
1MSPS: DRATE = 011
2MSPS: DRATE = 100
4MSPS: DRATE = 101
102
100
98
96
94
92
90
-40
-15
10
35
60
85
8 16
32
64
128
256
Oversampling Ratio
Temperature (C)
Figure 28.
Figure 29.
13
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
Current (mA)
90
Input Shorted
fCLK = 32MHz
LVDS Interface
80
IAVDD, WB/LL Filter
Input Shorted
fCLK = 32MHz
LVDS Interface
580
570
70
60
550
540
530
LL Filter
520
IDVDD, LL Filter
50
510
WB Filter
500
IDVDD, WB Filter
40
490
8 16
32
128
64
256
8 16
32
400
Figure 30.
Figure 31.
NOISE HISTOGRAM
(DRATE = 101, WB Filter)
NOISE HISTOGRAM
(DRATE = 000, WB Filter)
1600
Input Shorted
s = 60LSB
65,536 Points
Wide Bandwidth
fDATA = 4MSPS
Input Shorted
s = 17LSB
65,536 Points
Wide Bandwidth
fDATA = 125kSPS
1400
300
200
100
0
-400
256
Oversampling Ratio
Number of Occurences
Number of Occurrences
500
128
64
Oversampling Ratio
600
560
Power (mW)
100
1200
1000
800
600
400
200
0
-300
-200
-100
100
200
300
400
-80
-60
-40
-20
20
40
60
80
Figure 32.
Figure 33.
INTEGRAL NONLINEARITY
vs ANALOG INPUT VOLTAGE
3
+25C
+85C
-40C
INL (ppm)
1
0
-1
fCLK = 32MHz
fDATA = 125kSPS
Wide Bandwidth
-2
-3
-3
-2
-1
Figure 34.
14
ADS1675
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OVERVIEW
The ADS1675 is a 24-bit, delta-sigma ()
analog-to-digital converter (ADC). It provides
high-resolution measurements of both ac and dc
signals and features an advanced, multi-stage analog
modulator with a programmable and flexible digital
decimation filter.
DVDD
CLK
VREFN
VREFP
CAP2
CAP1
RBIAS
PLL
VCM
Biasing
3x
AINN
VIN
PDWN
START
Dual Filter
Path
VREF
AINP
ADS1675
Low-Latency Filter
DS
Modulator
Wide-Bandwidth Filter
CLK
CMOS- and
LVDSCompatible
Serial
Interface
and
Control
DRDY, DRDY
DOUT, DOUT
SCLK, SCLK
CS
LVDS
SCLK_SEL
DRATE[2:0]
FPATH
LL_CONFIG
OTRD
DGND
AGND
OTRA
15
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
NOISE PERFORMANCE
The ADS1675 offers outstanding noise performance
that can be optimized by adjusting the data rate. As
the averaging is increased (thus reducing the data
rate), the noise drops correspondingly. Table 1 shows
the noise as a function of data rate for both the
Low-Latency and the Wide-Bandwidth filter paths
under the conditions shown.
Table 1 lists some of the more common methods of
specifying noise. The dynamic range is the ratio of
the root-mean-square (RMS) value of a full-scale sine
wave to the RMS noise with the inputs shorted
together. This value is expressed in decibels relative
to full-scale (dBFS). The input-referred noise is the
RMS value of the noise with the inputs shorted,
referred to the input of the ADS1675. The effective
number of bits (ENOB) is calculated from a dc
perspective using the formula in Equation 1, where
full-scale range equals 2VREF.
ln
Full-scale range
RMS noise
ENOB =
ln(2)
(1)
FILTER PATH
Low-Latency
(Fast Response
Mode
configuration)
DATA RATE[2:0]
DATA RATE
(kSPS)
DYNAMIC
RANGE (dB)
INPUTREFERRED
NOISE (mVRMS)
ENOB
NOISE-FREE
BITS
000
125
111
6.30
19.86
17.14
001
250
109
7.47
19.61
16.89
010
500
107
9.51
19.27
16.54
011
1000
105
11.72
18.97
16.24
100
2000
104
13.72
18.74
16.02
101
4000
103
14.23
18.69
15.96
000
125
111
6.17
19.89
17.17
001
250
109
7.44
19.62
16.90
010
500
107
9.66
19.25
16.52
011
1000
104
12.99
18.82
16.09
100
2000
101
18.64
18.30
15.57
101
4000
94
44.02
17.06
14.33
Low-speed
modes
High-speed
modes
Low-speed
modes
Wide-Bandwidth
High-speed
modes
(1)
16
ADS1675
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CONVERSION START
(2)
tSETTLE
tSETTLE
(1)
START
tSTART
DRDY
tSETTLE
START
tSTART
DRDY
(1) See the Low-Latency Filter and Wide-Bandwidth Filter sections for specific values of settling time tSETTLE.
17
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
DIGITAL FILTER
LOW-LATENCY
CONFIGURATION
Single-cycle settling
Fast response
FPATH PIN
Low-Latency path
Wide-Bandwidth path
blank
(1)
18
000
57.80
17.375ms
556tCLK
54
001
107.53
9.375ms
300tCLK
109
010
188.68
5.375ms
172tCLK
208
011
277.78
3.625ms
116tCLK
344
The input signal aliases when its frequency exceeds fDATA/2, in accordance with the Nyquist theorem.
ADS1675
www.ti.com
DATA
RATE
(kSPS)
000
125
17.375ms
556tCLK
54
001
250
9.375ms
300tCLK
109
010
500
5.375ms
172tCLK
208
011
1000
3.625ms
116tCLK
344
100
2000
2.76ms
265tLSCLK
350
101
4000
2.385ms
229tLSCLK
355
SETTLING TIME,
tSETTLE-LL
3dB
BANDWIDTH
(kHz)
Settling Time
The settling time in absolute time (ms) is the same for
both configurations of the Low-Latency filter, as
shown in Table 4 and Table 5. The difference
between the configurations is seen with the timing of
the conversions after the filter has settled from a
pulse on the START pin.
Figure 38 illustrates the response of both
configurations on approximately the same time scale
in order to highlight the differences. With the
single-cycle settling configuration, each conversion
fully settles; in other words, the conversion period
tDRDY-SCS = tSETTLE-LL. The benefit of this configuration
is its simplicitythe ADS1675 functions similar to a
successive-approximation register (SAR) converter
and there is no need to consider discarding
partially-settled data because each conversion is fully
settled.
With the fast response configuration, the data rate for
conversions after initial settling is faster; that is, the
conversion time is less than the settling:
tDRDY-FR < tSETTLE-LL. One benefit of this configuration
is a faster response to changes on the inputs,
because data are supplied at a faster rate. Another
advantage is better support for post-processing. For
example, if multiple readings are averaged to reduce
noise, the higher data rate of the fast response
configuration allows this averaging to happen in less
time than it requires with the single-cycle settling
filter. A third benefit is the ability to measure higher
input frequencies without aliasing as a result of the
higher data rate.
tSTART_CLKR
CLK
tSETTLE-LL
tCLKDR
START
tDRDY-SCS =
tCLKDR + 1tCLK + tSETTLE-LL
DRDYSCS
DRDYFR
tDRDY-FR
NOTE: DRDYSCS is the DRDY output with the Low-Latency single-cycle settling configuration. DRDYFR is the DRDY output with the
Low-Latency fast-response settling configuration.
Figure 38. Low-Latency Single-Cycle Settling and Fast-Response Configuration Conversion Timing
19
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
DRATE = 000
-10
Magnitude (dB)
-20
-30
DRATE = 011
-40
-50
DRATE = 101
-60
DRATE = 100
-70
-80
0
1.4
DRATE = 000,
001, 010
1.2
DRATE = 011
0.2
0.9
1.0
DRATE = 100
1.0
Settling (%)
0.1
0.8
DRATE = 101
0.6
-20
Magnitude (dB)
0.4
0.2
0
0
10
12
Conversions (1/fDRDY-FR)
-40
-60
-80
-100
-120
-140
0
Frequency Response
0.5
1.0
1.5
2.0
2.5
3.0
Change on
Analog Inputs
VIN
Data 1
Data 2
Data 3
Data 4
DRDYLL-FR
Figure 42. Settling Example with the Low-Latency Filter in Fast-Response Configuration
20
ADS1675
www.ti.com
Phase Response
20
0
-20
Magnitude (dB)
-40
-60
-80
-100
-120
-140
WIDE-BANDWIDTH FILTER
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.40
0.45
Magnitude (dB)
0.2
0.1
-0.000005
-0.000010
-0.000015
-0.000020
-0.000025
-0.000030
-0.000035
-0.000040
0
000
125
439.44ms
14062tCLK
59.375
001
250
219.81ms
7074tCLK
118.75
010
500
110.00ms
3520tCLK
237.5
011
1000
55.04ms
1763tCLK
475
100
2000
27.52ms
2642tLSCLK
950
101
4000
13.79ms
1324tLSCLK
1900
SETTLING TIME,
tSETTLE-LL
0.05 0.10
3dB
BANDWIDTH
(kHz)
0.15
0.20
0.25
0.30
0.35
Magnitude (dB)
DRATE
[2:0]
DATA
RATE
(kSPS)
-2
-4
-6
-8
-10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
21
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
Settling Time
20
0
Magnitude (dB)
-20
-40
-60
120
-80
100
-100
80
Settling (%)
-120
-140
0
0.5
1.0
1.5
2.5
2.0
3.0
60
Fully Settled at
55 Conversions
40
20
0
-20
0
Phase Response
10
20
30
40
50
60
Conversions (1/fDRDY-WB)
tSTART_CLKR
CLK
tSETTLE
START
tDRDY
(1)
tDRDY
tDRDY
tDRDY
DRDY
(1) tDRDY = 1/fDATA. See Table 6 for the relationship between tSETTLE and tDRDY when using the Wide-Bandwidth filter.
Figure 48. START Pin Used for Multiple Conversions with Wide-Bandwidth Filter Path
22
ADS1675
www.ti.com
SERIAL INTERFACE
The ADS1675 offers a flexible and easy-to-use,
read-only serial interface designed to connect to a
wide range of digital processors, including DSPs,
microcontrollers, and FPGAs. In the low-speed
modes (DRATE = 000 to 011) the ADS1675 serial
interface can be configured to support either standard
CMOS voltage swings or low-voltage differential
swings (LVDS). In addition, when using standard
CMOS voltage swings, SCLK can be internally or
externally generated.
3V
AIN
CLK
SCLK
(High-Speed Mode)
DRDY
OTRA
(Low-Speed Mode)
OTRA
(High-Speed Mode)
23
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
LVDS
Internal
CMOS
24
ADS1675
www.ti.com
DATA FORMAT
In the low-speed modes, the ADS1675 outputs 24
bits of data in twos complement format. A positive
full-scale input produces an output code of 7FFFFFh,
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals that exceed full-scale. Table 8 summarizes
the ideal output codes for different input signals.
When the input is positive out-of-range, exceeding
the positive full-scale value of VREF, the output clips to
all 7FFFFFh. Likewise, when the input is negative
out-of-range by going below the negative full-scale
value of VREF, the output clips to 800000h.
Table 8. Ideal Output Code vs Input Signal
INPUT SIGNAL
VIN = (AINP AINN)
VREF
7FFFFFh
+VREF
2
23
000001h
-1
000000h
-VREF
2
23
FFFFFFh
-1
23
< -VREF
( 2 2 - 1)
23
8000000h
START
CLK
START1
DRDY
DRDY1
CLK
ADS16752
START2
DRDY
DRDY2
CLK
CLK
tSETTLE
START
DRDY1
DRDY2
25
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
26
POWER SUPPLIES
Two supplies are used on the ADS1675: analog
(AVDD) and digital (DVDD). Each supply must be
suitably bypassed to achieve the best performance. It
is recommended that a 1mF and 0.1mF ceramic
capacitor be placed as close to each supply pin as
possible. AVDD must be very clean and stable in
order to achieve optimum performance from the
device.
Connect each supply-pin bypass capacitor to the
associated ground. Each main supply bus should also
be bypassed with a bank of capacitors from 47mF to
0.1mF. Figure 52 illustrates the recommended method
for ADS1675 power-supply decoupling.
Power-supply pins 53 and 54 are used to drive the
internal clock supply circuits and, as such, are very
noisy. It is highly recommended that the traces from
these pins not be shared or run close to any of the
adjacent AVDD or AGND pins of the ADS1675.
These pins should be well-decoupled, using a 0.1mF
ceramic capacitor close to the pins, and immediately
terminated into power and ground planes.
ADS1675
www.ti.com
+3V
0.1mF
0.1mF
57
58
10mF
0.1mF
56
54
53
52
51
50
49
1 AVDD
DVDD 48
2 AGND
DGND 47
0.1mF
10mF
3 AGND
+5V
0.1mF
10mF
6 AGND
ADS1675
7 AVDD
9 AGND
10 AGND
11 AVDD
12 AVDD
DGND DGND DGND DGND DVDD DVDD DGND DGND DVDD DGND
17
18
19
20
23
24
25
26
27
31
0.1mF
10mF
27
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
APPLICATION INFORMATION
To obtain the specified performance from the
ADS1675, the following layout and component
guidelines should be considered.
1. Power Supplies: The device requires two power
supplies for operation: DVDD and AVDD. A very
clean and stable AVDD supply is needed to
achieve optimal performance from the device. For
both supplies, use a 10mF tantalum capacitor,
bypassed with a 0.1mF ceramic capacitor, placed
close to the device pins. Alternatively, a single
10mF ceramic capacitor can be used. The
supplies should be relatively free of noise and
should not be shared with devices that produce
voltage spikes (such as relays, LED display
drivers, etc.). If a switching power-supply source
is used, the voltage ripple should be low (less
than 2mV). The power supplies may be
sequenced in any order.
2. Ground Plane: A single ground plane connecting
both AGND and DGND pins can be used. If
separate digital and analog grounds are used,
connect the grounds together at the converter.
3. Digital Inputs: Source terminate the digital inputs
to the device with 50 series resistors. The
resistors should be placed close to the driving
end of the digital source (oscillator, logic gates,
DSP, etc.). These resistors help reduce ringing
on the digital lines, which may lead to degraded
ADC performance.
4. Analog/Digital Circuits: Place analog circuitry
(input buffer, reference) and associated tracks
together, keeping them away from digital circuitry
(DSP, microcontroller, logic). Avoid crossing
digital tracks across analog tracks to reduce
noise coupling and crosstalk.
5. Reference Inputs: The ADS1675 reference input
has 400 across VREFP and VREFN. The
driving amplifier must source current for this static
current, as well as dynamic switching current as a
result of the 32MHz clock. The reference driving
amplifier should be ready to source at least
10.5mA.
28
ADS1675
www.ti.com
1kW
10nF
+5V
0.1mF
10W
OPA211
100W
1kW
100mF
10mF
0.1mF
1mF
63
62
OUT
VIN
+5V
TRIM
REF5030
0.1mF
64
3V
22mF
1mF
61
60
59
VINN
Differential
Inputs
10W
VINP
100pF
750pF
5 AINP
100pF
ADS1675
8 RBIAS
7.5kW
13 VCM
1 mF
CM
2.5V
VIN+
CM
2.5V
VIN-
+
-
VINN
VINP
THS4503
RG
249W
CM
2.5V
-4V
RF
249W
CF
100pF
29
ADS1675
SBAS416D DECEMBER 2008 REVISED AUGUST 2010
www.ti.com
CF
100pF
Signal Source
RG
243W
RS
50W
RT
59W
VIN
CM
2.5V
CM
2.5V
RS
50W
CM
2.5V
RG
243W
RF
249W
+9V
+
-
RT
59W
CM
2.5V
VINN
VINP
THS4503
CM
-4V 2.5V
RF
249W
CF
100pF
30
ADS1675
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ form page numbers in the current version.
Changes from Revision C (September 2009) to Revision D
Page
Changed AC Performance, Total harmonic distortion (fDATA = 4MSPS) typical specifiaction in Electrical
Characteristics table ............................................................................................................................................................. 3
Changed Digital Filter Characteristics (Wide-Bandwidth Path), Stop band attentuation typical specification in
Electrical Characteristics table .............................................................................................................................................. 3
Changed description of tDRSCLK parameter in internal SCLK timing requirements table ....................................................... 8
Changed description of tLSCLK parameter in internal SCLK timing requirements table ......................................................... 8
Changed description of the Reference Inputs guidline in Application Information section ................................................. 28
Page
31
www.ti.com
16-Jul-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
(3)
Samples
(Requires Login)
ADS1675IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
ADS1675IPAGR
ACTIVE
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
Purchase Samples
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
14-Jul-2012
Device
ADS1675IPAGR
PAG
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1500
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
14-Jul-2012
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1675IPAGR
TQFP
PAG
64
1500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A JANUARY 1995 REVISED DECEMBER 1996
PAG (S-PQFP-G64)
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0 7
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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