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Electronics & Communication Engineering Department, National Institute of Technology, Hamirpur (HP), India
Electronics & Communication Engineering Department, National Institute of Technology, Hamirpur (HP), India
3
Electronics & Communication Engineering Department, National Institute of Technology, Hamirpur (HP), India
2
Abstract
In this paper present the performance analysis of two possible realizations of a CNT-based nano-interconnect, namely one obtained
by using a bundle of SWCNT and another one employing an MWCNT and their applicability as interconnects in nanoscale integrated
circuits in subthreshold regime. The time delay, power dissipation and power delay product of SWCNT bundle and MWCNT
interconnect configurations are derived and compared to those of the copper (Cu) wire counterparts for the intermediate and global
interconnects for three different technologies (32-, 22- and 16nm). It is observed that, compared with the Cu, and SWCNT bundle the
MWCNT interconnect can lead to a reduction of all above three parameters and it becomes more significant with increasing
interconnect length. Because of considerable improvement in Power Delay Product MWCNT interconnect will be more suitable for
the next generation of interconnect technology as compared with the SWCNT bundle and Cu counterpart in subthreshold regime also.
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
488
1
N 2n
N
RS RS1,i i i
i 1 R
i 1
I sub I 0 e
RQ
N
2 n i i
ground
tox
w
VDS
1 e VT
s=w
(1)
n 1VT2
tox= ht
ground
w
(2)
i 1
i 1 i
(4)
I 0 0 COX W
i 1
nVT
D=w
N
D/2
===
===
===
Fig 1 Cross section of a===
typical interconnect configuration in
(3)
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
489
Description
Width of interconnect
Height of interconnect
Spacing between two parallel wires
Diameter of a SWCNT in the bundle
Outer diameter of MWCNT
Dielectric thickness
Height from the ground
Total number of SWCNTS in the bundle
and total number of shells in the MWCNT
C C E1 CQ1
Where,
Distributed part
Lsi,1/2
Rli/2
Rsi,1/2
Lsi,1/2
Rsi,n/2 CQi,n
Cmi-1
Rs2,1/2
Rs1/2
Lumped part
(9)
(10)
Distributed part
Ls-b/2
Rl-b/2 Rs-b/2
Ls2,n/2
Rs2,n/2 CQ2,n
Lumped part
Ls-b/2
Ls-b/2
Ls-b/2
Ls1,1/2
Ls1,n/2
Rs1/2
CQ1
CE
Rs-b/2
CE
Ls1,n/2
Rs1,n/2 CQ1,n
4CQ-b Rs-b/2
4CQ-b
Rs-b/2 Rl-b/2
Rl2/2
Rs2,n/2
Cm1.n
Cm1
Rl1/2
cosh 1 D 2ht / D
C E1
2
0 r
Rli/2
Rsi,n/2
Ls2,n/2
Rs2,1/2
CQ2
Ls1,1/2
(8)
Cmi-1,n
Ls2,1/2 Ls2,1/2
Rl2/2
Lsi,n/2 Lsi,n/2
Rsi,1/2
CQi
Lumped part
2e 2
CQ 2
193aF / m
hv F
ith shell. The number of conducting channels of the ith shell can
be expressed as [17]
Lumped part
CE
Rl1/2
Rs1,n/2
CE
aDi b, Di 3nm
n 2
3
nm
i
3
(5)
mfp ,i
2 10 3 Di
T 2
T
0
(6)
RQ
h
4e 2
(7)
C mi ,i 1
2 0 r
D
ln i 1
Di
(11)
interconnects for
2, where mutual
capacitances in
is connected to
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
490
Nw
Nt
w d
RS bundle
(13)
Nt
if N t is even
N w N t 2
N
N 1
N w Nt t
if N t is odd
2
(14)
ad b
n
2
d 3nm
d 3nm
(15)
1 RQ
Rc (16)
N 2n
mfp
(12)
2t d
2 10 d
T 2
T
0
RQ
(18)
2nNmfp
CQbundle CQ N
(19)
Interme
diate*and
Global
intercon
nect
Wire Width w
(nm)
Height Width
Ratio t/w
Dielectric
Thickness tox = ht
(nm)
Effective
Resistivity of Cu
(-cm)
Relative Permittivity of
Dielectric r
Technology Node
32
22
16
32*
48
2*
3
54.4*
22*
32
2*
3
39.6*
16*
24
2*
3
25.2*
110.4
4.83*
76.8
6.01*
60
7.34*
3.52
4.2
4.92
2.3
2.0
1.7
(17)
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
491
Length = 400m
2.5
2
Power dissipation (nW)
1.5
0.5
0
32nm
Cu
22nm
Technology Nodes
Bundled SWCNT
16nm
Single MWCNT
Length = 4mm
50
Length = 400um
40
Delay (ns)
7
6.5
6
30
20
Delay (ns)
5.5
10
5
0
4.5
32nm
4
Cu
3.5
3
32nm
Cu
22nm
Technology nodes
Bundled SWCNT
16nm
22nm
Technology Nodes
Bundled SWCNT
16nm
Single MWCNT
Single MWCNT
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
492
18
16
14
12
10
8
6
4
2
0
Length = 4mm
30
25
20
32nm
22nm
16nm
Technology node
Bundled SWCNT
Cu
PDP (aj)
15
Single MWCNT
10
10
0
100
Delay (ns)
200
300
400
500
6
4
Cu
Bundled SWCNT
Single MWCNT
2
0
0
100
200
300
400
500
600
Bundled SWCNT
Single MWCNT
60
40
PDP (aj)
Delay (ns)
50
30
20
10
0
0
1000
2000
3000
4000
5000
Bundled SWCNT
500
Cu
Single MWCNT
1000
2000
3000
4000
Bundled SWCNT
Single MWCNT
Interconnect length (m)
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
493
Cu
Bundle
d
SWCN
T
10.404
Single
MWCN
T
7.804
32nm
11.86
3
22nm
15.91
4
12.128
27.20
0
19.742
16nm
6.210
13.257
Reduction in
MWCNT
PDP than
cu/SWCNT
bundle
(no. of folds)
Cu Bundle
d
SWCN
T
1.9
1.675
1
2.0
3
1.554
2.0
5
1.489
Technolog
y
Cu
32nm
342.11
6
Bundle
d
SWCN
T
219.553
Single
MWCN
T
96.657
REFERENCES
[1]
[2]
[3]
[4]
22nm
406.00
1
235.128
106.152
3.82
4
2.215
16nm
504.29
0
245.949
130.575
3.86
2
1.88
5. CONCLUSIONS
This work analyzed the delay and power dissipation for Cu,
bundled SWCNT and single MWCNT interconnects for the
32-, 22- and 16nm technologies nodes using SPICE
simulation. The MWCNT, SWCNT bundle and Cu
interconnects have been represented as an equivalent circuit
model and the CMOS driver is used to drive the interconnect
[5]
[6]
[7]
[8]
[9]
[10]
[11]
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
494
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
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Volume: 03 Issue: 04 | Apr-2014, Available @ http://www.ijret.org
495