SPI INTERFACE BLOCK HIGH LEVEL DESCRIPTION

Overview
The SPI/serial interface module implements a generic 4-bit wide SPI interface to connect to
several peripherals on the Orange Platform, namely:
i)

Texas Instruments DAC 128s085 chipset

ii)

ICS Clock Generator 307 chipset

iii)

Texas Instruments DAC 8555 chipset

iv)

Texas Instruments SR_hc594 Serial latches.

This module presents a common programming interface to software abstracting out the individual
differences within these devices w.r.t to the SPI protocol implementation.

FPGA Implementation

Figure 1 below illustrates the high level implementation of the SPI serial interface block. As shown in the
figure, the logic for asserting the clock and data lines is common for all peripherals, and the chip select is
asserted based on the device being asserted.

Figure 1: SPI Interface Block Diagram

2.1

SPI State Machine

The SPI state machine shown in Figure 1 handles the bulk of the functionality implemented in this
module. Figure 2 illustrates the state transition diagram.

Figure 2: SPI State Machine Diagram

2.2

Clocking

This module expects a 50MHz input clock (though the top level could feed another input clock frequency
if needed) and drives out a divided-by-two version to peripherals as the serial clock during an active
access. MO
2.3

Processor Interface

This block implements the control/ status registers and FIFOs required to interface with the P1010 host.
The FIFO interface implemented here is borrowed from the Obsidian design, which essentially presents
the head entry of a FIFO as a 32-bit register to the processor.

2.3.1

Control Register (Write/Read)

Bit(s
)

Parameter

Description

31:28

Unused

NA

31:24

Unused

N/A

23:20

Read FIFO Empty

Threshold

Programmable Read FIFO Empty Threshold

19:16

Write FIFO Empty

Threshold

Programmable Write FIFO Empty Threshold

15:8

Number of Bits

Number of Bits to read/write.

7:4

Device Select

0000 = DEV_1_ICS_307
0001 = DEV_2_DAC_128S085
0010 = DEV_3_DAC_8555
0011 = DEV_4_HC594

2.3.2

R_W

0 = Read, 1 = Write

Clear Read FIFO

Set high to clear read FIFO

Clear Write FIFO

Set high to clear write FIFO

Start bit

Rising edge on start bit triggers an access.

Interrupt Status Register (Read Only)

Bit(s)

Parameter

Description

31:10

Unused

NA

Rd FIFO Empty

Rd FIFO empty flag

Wr FIFO Full

Wr FIFO Full flag

Rd access complete

Indicator that read access is finished

Rd FIFO Status
Empty

Rd FIFO Empty

Rd FIFO Overflow

Rd FIFO overflow

Rd FIFO Above
Threshold

Rd FIFO above threshold.

Wr access complete

Indicator that write access is finished

WrFIFO Status
Empty

Wr FIFO Empty

Wr FIFO Overflow

Wr FIFO overflow

Wr FIFO Above
Threshold

Wr FIFO below threshold.

2.4

Software Programming Guidelines

2.4.1

Write Access

Program Write FIFO with number of words to write

Configure control register with start bit = 0 and other fields as required for transaction specifics
(e.g write/read, transaction length, etc.)

Configure control register with start bit = 1

Wait for access_done interrupt .

2.4.2

Read Access

Configure control register with start bit = 0 and other fields as required for transaction specifics.

Configure address register and instruction register

Wait for access_done or threshold level interrupt.

Read read FIFO for programmed burst length.