PRBS Test Design Document

Overview
A special FPGA build will be created to verify PCB connectivity and signal integrity.
A key functional area that needs to be verified using this special FPGA build is the
high-speed SERDES links used to the implement the V-by-one interface. Figure 1.
Below shows the architectural overview of the loop-back based verification plan.
Implementation
Figure below depicts the PRBS error testing function in the FPGA for a single lane. It
essentially consists of a 16-bit PRBS pattern generator which feeds the Transmit
transceiver. This generated data can be looped back to the PRBS Receiver either by
using external connections or by selecting the internal loopback feature. In both
cases, the PRBS receiver does the error detection and recording. Note that internal
loopback is implemented in user logic (and not in the Transceiver) since support for
transceiver loopback in Cyclone V transceivers is not clearly documented.

Figure 1. PRBS setup

Register File

Control Register (R/W) *

Bit 0 -> Enable PRBS counter. Set this bit high to enable PRBS generation
Bit 1-> Loopback enabled. Set this bit high to enable external loopback
Bit 2 -> Internal loopback enabled. Set this bit high to enable internal
loopback
Bit 3 -> Inject error. Toggle this bit to inject error.
Bit 4 -> Clear Error Count. Toggle this bit to clear error count register.

Error Count Register (Read only)*

Bit 0 -> High indicates PRBS sync achieved on receiver
Bit 1-3 > Reserved for Future use
Bit 15-4 12 bit counter to count PRBS errors.

* One register per link. Number of links is TBD.