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Analog Features
Analog-to-Digital Converter (ADC) Module:
- 10-bit resolution, up to 12 channels
- Auto acquisition capability
- Conversion available during Sleep
Analog Comparator Module:
- Two rail-to-rail analog comparators
- Power mode control
- Software controllable hysteresis
Voltage Reference Module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
Peripheral Highlights
Up to 17 I/O Pins and 1 Input Only Pin:
- High current sink/source 25 mA/25 mA
- Programmable weak pull-ups
- Programmable interrupt-on-change pins
Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Dedicated, low-power 32 kHz oscillator driver
Three Timer2-types: 8-Bit Timer/Counter with 8-Bit
Period Register, Prescaler and Postscaler
Two Capture, Compare, PWM (CCP) Modules
Two Enhanced CCP (ECCP) Modules:
- Software selectable time bases
- Auto-shutdown and auto-restart
- PWM steering
Up to Two Master Synchronous Serial Port
(MSSP) with SPI and I2CTM with:
- 7-bit address masking
- SMBus/PMBusTM compatibility
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) Module
mTouch Sensing Oscillator Module:
- Up to 12 input channels
DS40001440E-page 1
PIC16(L)F1825/9
Peripheral Highlights (Continued)
Data Signal Modulator Module:
- Selectable modulator and carrier sources
SR Latch:
- Multiple Set/Reset input options
- Emulates 555 Timer applications
Note:
DS40001440E-page 2
information,
Debug(1)
XLP
PIC12(L)F1822
(1)
2K
256
128
6
4
4
1
2/1
1
1
0/1/0
PIC12(L)F1840
(2)
4K
256
256
6
4
4
1
2/1
1
1
0/1/0
PIC16(L)F1823
(1)
2K
256
128 12
8
8
2
2/1
1
1
1/0/0
PIC16(L)F1824
(3)
4K
256
256 12
8
8
2
4/1
1
1
1/1/2
PIC16(L)F1825
(4)
8K
256 1024 12
8
8
2
4/1
1
1
1/1/2
PIC16(L)F1826
(5)
2K
256
256 16 12 12
2
2/1
1
1
1/0/0
PIC16(L)F1827
(5)
4K
256
384 16 12 12
2
4/1
1
2
1/1/2
PIC16(L)F1828
(3)
4K
256
256 18 12 12
2
4/1
1
1
1/1/2
PIC16(L)F1829
(4)
8K
256 1024 18 12 12
2
4/1
1
2
1/1/2
PIC16(L)F1847
(6)
8K
256 1024 16 12 12
2
4/1
1
2
1/1/2
Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS41413
PIC12(L)F1822/PIC16(L)F1823 Data Sheet, 8/14-Pin Flash Microcontrollers.
2: DS41441
PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers.
3: DS41419
PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers.
4: DS41440
PIC16(L)F1825/1829 Data Sheet, 14/20-Pin Flash Microcontrollers.
5: DS41391
PIC16(L)F1826/1827 Data Sheet, 18/20/28-Pin Flash Microcontrollers.
6: DS41453
PIC16(L)F1847 Data Sheet, 18/20/28-Pin Flash Microcontrollers.
SR Latch
ECCP (Full-Bridge)
ECCP (Half-Bridge)
CCP
MSSP (I2C/SPI)
EUSART
Timers
(8/16-bit)
Comparators
CapSense (ch)
I/Os(2)
Data SRAM
(bytes)
Data EEPROM
(bytes)
Program Memory
Flash (words)
Device
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
I/H
I/H
I/H
I/H
I/H
I/H
I/H
I/H
I/H
I/H
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
please
visit
PIC16(L)F1825/9
FIGURE 1:
FIGURE 2:
14
VSS
RA5
13
RA0/ICSPDAT
12
RA1/ICSPCLK
11
RA2
10
RC0
RC1
RC2
RA4
MCLR/VPP/RA3
RC5
RC4
RC3
PIC16(L)F1825
VDD
RA4
13 VSS
NC
14
15 NC
RA5 1
16 VDD
QFN, UQFN
12 RA0/ICSPDAT
11 RA1/ICSPCLK
PIC16(L)F1825
RC1 8
9 RC0
RC2 7
RC5 4
RC3 6
10 RA2
RC4 5
MCLR/VPP/RA3 3
DS40001440E-page 3
PIC16(L)F1825/9
14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1825)
Comparator
SR Latch
Timers
ECCP
MSSP
Interrupt
Modulator
Pull-up
Basic
AN0
VREFDACOUT
CPS0
C1IN+
TX(1)
CK(1)
IOC
ICSPDAT
ICDDAT
RA1
12 11
AN1
VREF+
CPS1
C12IN0-
SRI
RX(1)
DT(1)
IOC
ICSPCLK
ICDCLK
RA2
11 10
AN2
CPS2
C1OUT
SRQ
T0CKI
CCP3
FLT0
INT/
IOC
RA3
T1G(1)
SS1(1)
IOC
MCLR
VPP
RA4
AN3
CPS3
T1G(1)
T1OSO
P2B(1)
SDO1(1)
IOC
OSC2
CLKOUT
CLKR
RA5
T1CKI
T1OSI
CCP2
P2A(1)
IOC
OSC1
CLKIN
RC0
10
AN4
CPS4
C2IN+
P1D(1)
SCL
SCK
RC1
AN5
CPS5
C12IN1-
CCP4
P1C(1)
SDA
SDI
RC2
AN6
CPS6
C12IN2-
P1D(1)
P2B(1)
SDO1(1)
MDCIN1
RC3
AN7
CPS7
C12IN3-
CCP2(1)
P1C(1)
P2A(1)
SS1(1)
MDMIN
RC4
C2OUT
SRNQ
P1B
TX(1)
CK(1)
MDOUT
RC5
CCP1
P1A
RX(1)
DT(1)
MDCIN2
VDD
16
VDD
VSS
14 13
VSS
Note 1:
EUSART
Cap Sense
13 12
A/D
RA0
I/O
Reference
16-Pin QFN/UQFN
14-Pin PDIP/SOIC/TSSOP
TABLE 1:
DS40001440E-page 4
PIC16(L)F1825/9
FIGURE 3:
VSS
19
RA0/ICSPDAT
RA4
18
RA1/ICSPCLK
MCLR/VPP/RA3
17
RA2
RC5
VDD
FIGURE 4:
RC4
RC3
RC6
RC7
RB7
PIC16(L)F1829
RA5
16
RC0
15
RC1
14
RC2
13
RB4
12
RB5
10
11
RB6
16 ICSPDAT/RA0
VDD
Vss
20
19
18
17
RA4
RA5
QFN, UQFN
RC6 5
RC7 6
RB7 7
RB6 8
RB5 9
RB4 10
15 RA1/ICSPCLK
MCLR/VPP/RA3 1
14 RA2
RC5 2
RC4 3 PIC16(L)F1829 13 RC0
12 RC1
RC3 4
11 RC2
DS40001440E-page 5
PIC16(L)F1825/9
20-PIN ALLOCATION TABLE (PIC16(L)F1829)
Cap Sense
Comparator
SR Latch
Timers
CCP
EUSART
SSP
Interrupt
Modulator
Pull-up
Basic
19 16
AN0
VREFDACOUT
CPS0
C1IN+
IOC
ICSPDAT/
ICDDAT
RA1
18 15
AN1
VREF+
CPS1
C12IN0-
SRI
IOC
ICSPCLK/
ICDCLK
RA2
17 14
AN2
CPS2
C1OUT
SRQ
T0CKI
CCP3
FLT0
INT/
IOC
RA3
T1G(1)
IOC
Y(4)
MCLR
VPP
RA4
20
AN3
CPS3
T1G(1)
T1OSO
P2B(1)
SS2(1)
IOC
OSC2
CLKOUT
CLKR
RA5
19
T1CKI
T1OSI
CCP2(1)
P2A(1)
SDO2(1)
IOC
OSC1
CLKIN
RB4
13 10
AN10
CPS10
SDA1
SDI1
IOC
RB5
12
AN11
CPS11
RX(1)
DT(1)
SDA2
SDI2
IOC
RB6
11
SCL1
SCK1
IOC
RB7
10
TX(1)
CK(1)
SCL2
SCK2
IOC
RC0
16 13
AN4
CPS4
C2IN+
P1D(1)
SS2(1)
RC1
15 12
AN5
CPS5
C12IN1-
P1C(1)
SDO2(1)
RC2
14 11
AN6
CPS6
C12IN2-
P1D(1)
P2B(1)
MDCIN1
RC3
AN7
CPS7
C12IN3-
P1C(1)
CCP2(1)
P2A(1)
MDMIN
RC4
C2OUT
SRNQ
P1B
TX(1)
CK(1)
MDOUT
RC5
CCP1
P1A
RX(1)
DT(1)
MDCIN2
RC6
AN8
CPS8
CCP4
SS1
RC7
AN9
CPS9
SDO1
VDD
18
VDD
Vss
20 17
VSS
Note
1:
A/D
RA0
I/O
Reference
20-Pin QFN/UQFN
20-Pin PDIP/SOIC/SSOP
TABLE 2:
DS40001440E-page 6
PIC16(L)F1825/9
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 17
3.0 Memory Organization ................................................................................................................................................................. 19
4.0 Device Configuration .................................................................................................................................................................. 47
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 53
6.0 Reference Clock Module ............................................................................................................................................................ 71
7.0 Resets ........................................................................................................................................................................................ 74
8.0 Interrupts .................................................................................................................................................................................... 82
9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 96
10.0 Watchdog Timer ......................................................................................................................................................................... 98
11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 102
12.0 I/O Ports ................................................................................................................................................................................... 116
13.0 Interrupt-on-Change ................................................................................................................................................................. 136
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 141
15.0 Temperature Indicator Module ................................................................................................................................................. 143
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 144
17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 157
18.0 SR Latch................................................................................................................................................................................... 162
19.0 Comparator Module.................................................................................................................................................................. 167
20.0 Timer0 Module ......................................................................................................................................................................... 174
21.0 Timer1 Module with Gate Control............................................................................................................................................. 177
22.0 Timer2/4/6 Modules.................................................................................................................................................................. 188
23.0 Data Signal Modulator.............................................................................................................................................................. 192
24.0 Capture/Compare/PWM Modules ............................................................................................................................................ 201
25.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module .............................................................................................. 229
26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 281
27.0 Capacitive Sensing (CPS) Module ........................................................................................................................................... 309
28.0 In-Circuit Serial Programming (ICSP) ............................................................................................................................... 317
29.0 Instruction Set Summary .......................................................................................................................................................... 320
30.0 Electrical Specifications............................................................................................................................................................ 334
31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 370
32.0 Development Support............................................................................................................................................................... 401
33.0 Packaging Information.............................................................................................................................................................. 405
Appendix A: Data Sheet Revision History.......................................................................................................................................... 432
Appendix B: Migrating From Other PIC Devices ............................................................................................................................. 432
The Microchip Web Site ..................................................................................................................................................................... 433
Customer Change Notification Service .............................................................................................................................................. 433
Customer Support .............................................................................................................................................................................. 433
Product Identification System ............................................................................................................................................................ 434
DS40001440E-page 7
PIC16(L)F1825/9
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS40001440E-page 8
PIC16(L)F1825/9
1.0
DEVICE OVERVIEW
Peripheral
PIC16(L)F1829
DEVICE PERIPHERAL
SUMMARY
PIC16(L)F1825
TABLE 1-1:
ADC
Data EEPROM
EUSART
SR Latch
ECCP1
ECCP2
CCP3
CCP4
C1
C2
Capture/Compare/PWM Modules
Comparators
Timers
Timer0
Timer1
Timer2
Timer4
Timer6
DS40001440E-page 9
PIC16(L)F1825/9
FIGURE 1-1:
Program
Flash Memory
CLKR
OSC2/CLKOUT
OSC1/CLKIN
RAM
EEPROM
Clock
Reference
Timing
Generation
PORTA
CPU
INTRC
Oscillator
PORTB(3)
(Figure 2-1)
MCLR
Note
PORTC
ADC
10-Bit
Timer0
Timer1
Timer2
Timer4
Timer6
Comparators
SR
Latch
ECCP1
ECCP2
CCP3
CCP4
MSSP
EUSART
1:
2:
3:
DS40001440E-page 10
PIC16(L)F1825/9
TABLE 1-2:
Name
RA0/AN0/CPS0/C1IN+/VREF-/
DACOUT/TX(1)/CK(1)/
ICSPDAT/ICDDAT
RA1/AN1/CPS1/C12IN0-/VREF+/
SRI/RX(1)/DT(1)/ICSPCLK/
ICDCLK
RA2/AN2/CPS2/T0CKI/INT/
C1OUT/SRQ/CCP3/FLT0
RA3/SS1(1)/T1G(1)/VPP/MCLR
Function
Input
Type
RA0
TTL
AN0
AN
Output
Type
Description
CPS0
AN
C1IN+
AN
VREF-
AN
DACOUT
AN
TX
CK
ST
ICSPDAT
ST
ICDDAT
ST
RA1
TTL
AN1
AN
CPS1
AN
C12IN0-
AN
VREF+
AN
SRI
ST
SR Latch input.
RX
ST
DT
ST
ICSPCLK
ST
ICDCLK
ST
RA2
ST
AN2
AN
CPS2
AN
T0CKI
ST
INT
ST
External interrupt.
C1OUT
SRQ
CCP3
ST
CMOS Capture/Compare/PWM3.
FLT0
ST
RA3
TTL
SS1
ST
T1G
ST
VPP
HV
Programming voltage.
MCLR
ST
DS40001440E-page 11
PIC16(L)F1825/9
TABLE 1-2:
Name
RA4/AN3/CPS3/OSC2/
CLKOUT/T1OSO/CLKR/
SDO1(1)/P2B(1)/T1G(1,2)
RA5/CLKIN/OSC1/T1OSI/
T1CKI/P2A(1)/CCP2(1)
RC0/AN4/CPS4/C2IN+/SCL/
SCK/P1D(1)
RC1/AN5/CPS5/C12IN1-/SDA/
SDI/P1C(1)/CCP4
RC2/AN6/CPS6/C12IN2-/
P1D(1,2)/P2B(1,2)/SDO1(1,2)/
MDCIN1
Function
Input
Type
RA4
TTL
Output
Type
Description
AN3
AN
CPS3
AN
OSC2
CLKOUT
T1OSO
XTAL
CLKR
XTAL
SDO1
P2B
T1G
ST
RA5
TTL
CLKIN
CMOS
OSC1
XTAL
T1OSI
XTAL
XTAL
T1CKI
ST
P2A
CCP2
ST
CMOS Capture/Compare/PWM2.
RC0
TTL
AN4
AN
CPS4
AN
C2IN+
AN
SCL
I2C
OD
I2C clock.
SCK
ST
P1D
RC1
TTL
AN5
AN
CPS5
AN
C12IN1-
AN
SDA
I2C
OD
SDI
CMOS
P1C
CCP4
AN
RC2
TTL
Capture/Compare/PWM4.
AN6
AN
CPS6
AN
C12IN2-
AN
P1D
P2B
SDO1
MDCIN1
ST
DS40001440E-page 12
PIC16(L)F1825/9
TABLE 1-2:
Name
RC3/AN7/CPS7/C12IN3-/
P2A(1,2)/CCP2(1,2)/P1C(1,2)/
SS1(1,2)/MDMIN
RC4/C2OUT/SRNQ/P1B/TX(1,2)/
CK(1,2)/MDOUT
RC5/P1A/CCP1/DT(1,2)/RX(1,2)/
MDCIN2
Function
Input
Type
RC3
TTL
Output
Type
Description
AN7
AN
CPS7
AN
C12IN3-
AN
P2A
CCP2
AN
P1C
Capture/Compare/PWM2.
SS1
ST
MDMIN
ST
RC4
TTL
C2OUT
SRNQ
P1B
TX
CK
ST
MDOUT
RC5
TTL
P1A
CCP1
ST
CMOS Capture/Compare/PWM1.
RX
ST
DT
ST
MDCIN2
ST
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
DS40001440E-page 13
PIC16(L)F1825/9
TABLE 1-3:
Name
RA0/AN0/CPS0/C1IN+/VREF-/
DACOUT/ICSPDAT/ICDDAT
RA1/AN1/CPS1/C12IN0-/VREF+/
SRI/ICSPCLK/ICDCLK
RA2/AN2/CPS2/T0CKI/INT/
C1OUT/SRQ/CCP3/FLT0
RA3/T1G(1)/VPP/MCLR
RA4/AN3/CPS3/OSC2/
CLKOUT/T1OSO/CLKR/SS2(1)/
P2B(1)/T1G(1,2)
Function
Input
Type
RA0
TTL
AN0
AN
Output
Type
Description
CPS0
AN
C1IN+
AN
VREF-
AN
DACOUT
AN
ICSPDAT
ST
ICDDAT
ST
RA1
TTL
AN1
AN
CPS1
AN
C12IN0-
AN
VREF+
AN
SRI
ST
SR Latch input.
ICSPCLK
ST
ICDCLK
ST
RA2
ST
AN2
AN
CPS2
AN
T0CKI
ST
INT
ST
External interrupt.
C1OUT
SRQ
CCP3
ST
CMOS Capture/Compare/PWM3.
FLT0
ST
RA3
TTL
T1G
ST
VPP
HV
Programming voltage.
MCLR
ST
RA4
TTL
AN3
AN
CPS3
AN
OSC2
CLKOUT
T1OSO
XTAL
CLKR
SS2
ST
P2B
T1G
ST
XTAL
DS40001440E-page 14
PIC16(L)F1825/9
TABLE 1-3:
Name
RA5/CLKIN/OSC1/T1OSI/
SD02(1)/T1CKI/P2A(1)/CCP2(1)
RB4/AN10/CPS10/SDA1/SDI1
RB5/AN11/CPS11/RX
DT(1,2)/SDA2/SDI2
(1,2)
RB6/SCL1/SCK1
RB7/TX(1,2)/CK(1,2)/SCL2/SCK2
RC0/AN4/CPS4/C2IN+/P1D(1)/
SS2(1,2)
RC1/AN5/CPS5/C12IN1-/P1C(1)/
SD02(1,2)
Function
Input
Type
Output
Type
RA5
TTL
CLKIN
CMOS
OSC1
XTAL
T1OSI
XTAL
XTAL
SD02
T1CKI
ST
P2A
CCP2
ST
CMOS Capture/Compare/PWM2.
RB4
TTL
Description
AN10
AN
CPS10
AN
SDA1
I2C
OD
SDI1
CMOS
RB5
TTL
AN11
AN
CPS11
AN
RX
ST
DT
ST
SDA2
I2C
SDI2
CMOS
RB6
TTL
SCL1
I2C
I2C clock 1.
SCK1
ST
RB7
TTL
TX
CK
ST
SCL2
I2C
OD
I2C clock 2.
SCK2
ST
RC0
TTL
AN4
AN
CPS4
AN
C2IN+
AN
P1D
SS2
ST
RC1
TTL
AN5
AN
CPS5
AN
C12IN1-
AN
P1C
SDO2
DS40001440E-page 15
PIC16(L)F1825/9
TABLE 1-3:
Name
RC2/AN6/CPS6/C12IN2-/
P1D(1,2)/P2B(1,2)/MDCIN1
RC3/AN7/CPS7/C12IN3-/
P2A(1,2)/CCP2(1,2)/P1C(1,2)/
MDMIN
RC4/C2OUT/SRNQ/P1B/TX(1)/
CK(1)/MDOUT
RC5/P1A/CCP1/DT(1)/RX(1)/
MDCIN2
RC6/AN8/CPS8/CCP4/SS1
Function
Input
Type
RC2
TTL
Output
Type
Description
AN6
AN
CPS6
AN
C12IN2-
AN
P1D
P2B
MDCIN1
ST
RC3
TTL
AN7
AN
CPS7
AN
C12IN3-
AN
P2A
CCP2
AN
Capture/Compare/PWM2.
P1C
MDMIN
ST
RC4
TTL
C2OUT
SRNQ
P1B
TX
CK
ST
MDOUT
RC5
TTL
P1A
CCP1
ST
CMOS Capture/Compare/PWM1.
RX
ST
DT
ST
MDCIN2
ST
RC6
TTL
AN8
AN
CPS8
AN
CCP4
AN
Capture/Compare/PWM4.
SS1
ST
RC7
TTL
AN9
AN
CPS9
AN
SDO1
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
RC7/AN9/CPS9/SDO1
DS40001440E-page 16
PIC16(L)F1825/9
2.0
2.1
2.2
2.3
2.4
Instruction Set
DS40001440E-page 17
PIC16(L)F1825/9
FIGURE 2-1:
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(15-bit)
(13-bit)
14
Instruction
Instruction Reg
reg
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Indirect
Addr
12
12
Direct Addr 7
5
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
Power-up
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W Reg
Internal
Oscillator
Block
VDD
DS40001440E-page 18
VSS
PIC16(L)F1825/9
3.0
MEMORY ORGANIZATION
3.1
TABLE 3-1:
PIC16(L)F1825
PIC16(L)F1829
8,192
7FFFh
DS40001440E-page 19
PIC16(L)F1825/9
FIGURE 3-1:
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
RETLW Instruction
Stack Level 0
Stack Level 1
Stack Level 15
EXAMPLE 3-1:
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Page 1
0FFFh
1000h
Page 2
Page 3
Rollover to Page 0
Rollover to Page 3
DS40001440E-page 20
3.1.1.1
Reset Vector
On-chip
Program
Memory
3.1.1
17FFh
1800h
1FFFh
2000h
constants
BRW
RETLW
RETLW
RETLW
RETLW
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
; LOTS OF CODE
MOVLW
DATA_INDEX
call constants
; THE CONSTANT IS IN W
7FFFh
PIC16(L)F1825/9
3.1.1.2
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
; LOTS OF CODE
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW
0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.2
3.2.1
CORE REGISTERS
INDF0
INDF1
PCL
STATUS
FSR0 Low
FSR0 High
FSR1 Low
FSR1 High
BSR
WREG
PCLATH
INTCON
Note:
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
DS40001440E-page 21
PIC16(L)F1825/9
3.2.1.1
STATUS Register
REGISTER 3-1:
U-0
U-0
R-1/q
R-1/q
R/W-0/u
R/W-0/u
R/W-0/u
TO
PD
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS40001440E-page 22
PIC16(L)F1825/9
3.2.2
3.2.3
FIGURE 3-2:
0Bh
0Ch
Core Registers
(12 bytes)
3.2.4
Memory Region
00h
3.2.3.1
BANKED MEMORY
PARTITIONING
COMMON RAM
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.2.5
TABLE 3-2:
Device
PIC16(L)F1825
PIC16(L)F1829
Banks
Table No.
0-7
Table 3-3
8-15
Table 3-4
16-23
Table 3-5
24-31
Table 3-6
31
Table 3-7
DS40001440E-page 23
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
CCPR2L
BANK 6
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
CCPR3L
CCPR3H
CCP3CON
CCPR4L
BANK 7
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB(1)
PORTC
PIR1
PIR2
PIR3
PIR4(1)
TMR0
TMR1L
TMR1H
T1CON
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB(1)
TRISC
PIE1
PIE2
PIE3
PIE4(1)
OPTION_REG
PCON
WDTCON
OSCTUNE
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB(1)
LATC
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELB(1)
ANSELC
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUA
WPUB(1)
WPUC
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INLVLA
INLVLB(1)
INLVLC
IOCAP
IOCAN
IOCAF
019h
T1GCON
099h
OSCCON
119h
DACCON1
199h
RCREG
219h
SSP2BUF(1)
299h
CCPR2H
319h
CCPR4H
399h
01Ah
TMR2
09Ah
OSCSTAT
11Ah
SRCON0
19Ah
TXREG
21Ah
SSP2ADD(1)
29Ah
CCP2CON
31Ah
CCP4CON
39Ah
CLKRCON
IOCBP(1)
IOCBN(1)
IOCBF(1)
01Bh
PR2
09Bh
ADRESL
11Bh
SRCON1
19Bh
SPBRGL
21Bh
SSP2MSK(1)
29Bh
PWM2CON
31Bh
39Bh
01Ch
T2CON
09Ch
ADRESH
11Ch
19Ch
SPBRGH
21Ch
SSP2STAT(1)
29Ch
CCP2AS
31Ch
39Ch
MDCON
01Dh
09Dh
ADCON0
11Dh
APFCON0
19Dh
RCSTA
21Dh
SSP2CON1(1)
29Dh
PSTR2CON
31Dh
39Dh
MDSRC
01Eh
CPSCON0
09Eh
ADCON1
11Eh
APFCON1
19Eh
TXSTA
21Eh
SSP2CON2(1)
29Eh
CCPTMRS
31Eh
39Eh
MDCARL
01Fh
020h
CPSCON1
09Fh
0A0h
11Fh
120h
19Fh
1A0h
BAUDCON
21Fh
220h
SSP2CON3(1)
29Fh
2A0h
31Fh
320h
39Fh
3A0h
MDCARH
General
Purpose
Register
96 Bytes
06Fh
070h
General
Purpose
Register
80 Bytes
0EFh
0F0h
07Fh
Note 1:
16Fh
170h
Accesses
70h 7Fh
Common RAM
Legend:
General
Purpose
Register
80 Bytes
0FFh
1EFh
1F0h
Accesses
70h 7Fh
17Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h 7Fh
1FFh
General
Purpose
Register
80 Bytes
27Fh
Accesses
70h 7Fh
2FFh
General
Purpose
Register
80 Bytes
3EFh
3F0h
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
General
Purpose
Register
80 Bytes
Accesses
70h 7Fh
37Fh
Accesses
70h 7Fh
3FFh
PIC16(L)F1825/9
DS40001440E-page 24
TABLE 3-3:
TABLE 3-4:
BANK 8
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TMR4
PR4
T4CON
TMR6
PR6
T6CON
BANK 9
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
General
Purpose
Register
80 Bytes
46Fh
470h
DS40001440E-page 25
Legend:
BANK 10
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
General
Purpose
Register
80 Bytes
4EFh
4F0h
Accesses
70h 7Fh
47Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 11
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
General
Purpose
Register
80 Bytes
56Fh
570h
Accesses
70h 7Fh
4FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
General
Purpose
Register
80 Bytes
5EFh
5F0h
Accesses
70h 7Fh
57Fh
BANK 12
600h
INDF0
601h
INDF1
602h
PCL
603h
STATUS
604h
FSR0L
605h
FSR0H
606h
FSR1L
607h
FSR1H
608h
BSR
609h
WREG
60Ah
PCLATH
60Bh
INTCON
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
Accesses
70h 7Fh
5FFh
BANK 13
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
BANK 14
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Unimplemented
Read as 0
6EFh
6F0h
Accesses
70h 7Fh
67Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 15
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
Unimplemented
Read as 0
76Fh
770h
Accesses
70h 7Fh
6FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
7EFh
7F0h
Accesses
70h 7Fh
77Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
7FFh
PIC16(L)F1825/9
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
BANK 16
800h
801h
802h
803h
804h
805h
806h
807h
808h
809h
80Ah
80Bh
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
81Fh
820h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 17
880h
881h
882h
883h
884h
885h
886h
887h
888h
889h
88Ah
88Bh
88Ch
88Dh
88Eh
88Fh
890h
891h
892h
893h
894h
895h
896h
897h
898h
899h
89Ah
89Bh
89Ch
89Dh
89Eh
89Fh
8A0h
Unimplemented
Read as 0
86Fh
870h
Legend:
BANK 18
900h
901h
902h
903h
904h
905h
906h
907h
908h
909h
90Ah
90Bh
90Ch
90Dh
90Eh
90Fh
910h
911h
912h
913h
914h
915h
916h
917h
918h
919h
91Ah
91Bh
91Ch
91Dh
91Eh
91Fh
920h
Unimplemented
Read as 0
8EFh
8F0h
8FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 19
980h
981h
982h
983h
984h
985h
986h
987h
988h
989h
98Ah
98Bh
98Ch
98Dh
98Eh
98Fh
990h
991h
992h
993h
994h
995h
996h
997h
998h
999h
99Ah
99Bh
99Ch
99Dh
99Eh
99Fh
9A0h
Unimplemented
Read as 0
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
97Fh
BANK 20
A00h
A01h
A02h
A03h
A04h
A05h
A06h
A07h
A08h
A09h
A0Ah
A0Bh
A0Ch
A0Dh
A0Eh
A0Fh
A10h
A11h
A12h
A13h
A14h
A15h
A16h
A17h
A18h
A19h
A1Ah
A1Bh
A1Ch
A1Dh
A1Eh
A1Fh
A20h
Unimplemented
Read as 0
9EFh
9F0h
96Fh
970h
Accesses
70h 7Fh
Accesses
70h 7Fh
87Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 21
A80h
A81h
A82h
A83h
A84h
A85h
A86h
A87h
A88h
A89h
A8Ah
A8Bh
A8Ch
A8Dh
A8Eh
A8Fh
A90h
A91h
A92h
A93h
A94h
A95h
A96h
A97h
A98h
A99h
A9Ah
A9Bh
A9Ch
A9Dh
A9Eh
A9Fh
AA0h
Unimplemented
Read as 0
BANK 22
B00h
B01h
B02h
B03h
B04h
B05h
B06h
B07h
B08h
B09h
B0Ah
B0Bh
B0Ch
B0Dh
B0Eh
B0Fh
B10h
B11h
B12h
B13h
B14h
B15h
B16h
B17h
B18h
B19h
B1Ah
B1Bh
B1Ch
B1Dh
B1Eh
B1Fh
B20h
Unimplemented
Read as 0
Accesses
70h 7Fh
A7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
AEFh
AF0h
A6Fh
A70h
Accesses
70h 7Fh
9FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 23
B80h
B81h
B82h
B83h
B84h
B85h
B86h
B87h
B88h
B89h
B8Ah
B8Bh
B8Ch
B8Dh
B8Eh
B8Fh
B90h
B91h
B92h
B93h
B94h
B95h
B96h
B97h
B98h
B99h
B9Ah
B9Bh
B9Ch
B9Dh
B9Eh
B9Fh
BA0h
Unimplemented
Read as 0
Unimplemented
Read as 0
Accesses
70h 7Fh
B7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BEFh
BF0h
B6Fh
B70h
Accesses
70h 7Fh
AFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
BFFh
PIC16(L)F1825/9
DS40001440E-page 26
TABLE 3-5:
TABLE 3-6:
BANK 24
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 25
C80h
C81h
C82h
C83h
C84h
C85h
C86h
C87h
C88h
C89h
C8Ah
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
Unimplemented
Read as 0
DS40001440E-page 27
C6Fh
C70h
CFFh
BANK 26
D00h
D01h
D02h
D03h
D04h
D05h
D06h
D07h
D08h
D09h
D0Ah
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
Unimplemented
Read as 0
CEFh
CF0h
Accesses
70h 7Fh
Legend:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 27
D80h
D81h
D82h
D83h
D84h
D85h
D86h
D87h
D88h
D89h
D8Ah
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
Unimplemented
Read as 0
D6Fh
D70h
Accesses
70h 7Fh
CFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
DEFh
DF0h
Accesses
70h 7Fh
D7Fh
BANK 28
E00h
E01h
E02h
E03h
E04h
E05h
E06h
E07h
E08h
E09h
E0Ah
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
BANK 29
E80h
E81h
E82h
E83h
E84h
E85h
E86h
E87h
E88h
E89h
E8Ah
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
Unimplemented
Read as 0
E6Fh
E70h
Accesses
70h 7Fh
DFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 30
F00h
F01h
F02h
F03h
F04h
F05h
F06h
F07h
F08h
F09h
F0Ah
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
Unimplemented
Read as 0
EEFh
EF0h
Accesses
70h 7Fh
E7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 31
F80h
INDF0
F81h
INDF1
F82h
PCL
F83h
STATUS
F84h
FSR0L
F85h
FSR0H
F86h
FSR1L
F87h
FSR1H
F88h
BSR
F89h
WREG
F8Ah
PCLATH
F8Bh
INTCON
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
See Table 3-7 for
F98h register mapping
F99h
details
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
Unimplemented
Read as 0
F6Fh
F70h
Accesses
70h 7Fh
EFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
FEFh
FF0h
Accesses
70h 7Fh
F7Fh
Accesses
70h 7Fh
FFFh
PIC16(L)F1825/9
C00h
C01h
C02h
C03h
C04h
C05h
C06h
C07h
C08h
C09h
C0Ah
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
PIC16(L)F1825/9
TABLE 3-7:
PIC16(L)F1825/9 MEMORY
MAP, BANK 31
Bank 31(1)
F8Ch
Unimplemented
Read as 0
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
Legend:
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
STKPTR
TOSL
TOSH
3.2.6
PIC16(L)F1825
PIC16(L)F1829
Bank(s)
Page No.
29
30
31
32
33
34
35
36
37
9-30
38
31
39
DS40001440E-page 28
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
000h(1)
INDF0
001h(1)
INDF1
002h(1)
PCL
003h(1)
STATUS
004h(1)
FSR0L
005h(1)
FSR0H
006h(1)
FSR1L
007h(1)
FSR1H
008h(1)
BSR
009h(1)
WREG
00Ah(1)
PCLATH
00Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
00Ch
PORTA
RA5
RA4
RA3
RA2
RA1
RA0
00Dh
PORTB(2)
00Eh
PORTC
00Fh
Unimplemented
010h
Unimplemented
011h
PIR1
TMR1GIF
ADIF
012h
PIR2
OSFIF
C2IF
C1IF
013h
PIR3
CCP4IF
014h
PIR4(2)
015h
TMR0
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
018h
T1CON
TMR1CS1
TMR1CS0
019h
T1GCON
TMR1GE
T1GPOL
01Ah
TMR2
01Bh
PR2
01Ch
T2CON
Working Register
RB7
RB6
RB5
RB4
RC7(2)
RC6(2)
RC5
RC4
RC3
RC2
RC1
RC0
RCIF
TXIF
SSP1IF
CCP1IF
EEIF
BCL1IF
CCP3IF
TMR6IF
T1CKPS<1:0>
T1GTM
T1GSPM
TMR2IF
TMR1IF
CCP2IF
TMR4IF
BCL2IF
SSP2IF
T1OSCEN
T1SYNC
T1GGO/
DONE
T1GVAL
TMR1ON
T1GSS<1:0>
T2OUTPS<3:0>
CPSCON0
CPSON
CPSRM
01Fh
CPSCON1
1:
2:
3:
4:
DC
BSR<4:0>
01Eh
Note
01Dh
Legend:
PD
TMR2ON
T2CKPS<1:0>
Unimplemented
CPSRNG<1:0>
CPSOUT
CPSCH<3:0>
T0XCS
DS40001440E-page 29
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 1
080h(1)
INDF0
081h(1)
INDF1
082h(1)
PCL
083h(1)
STATUS
084h(1)
FSR0L
085h(1)
FSR0H
086h(1)
FSR1L
087h(1)
FSR1H
088h(1)
BSR
089h(1)
WREG
08Ah(1)
PCLATH
08Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
08Ch
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
08Dh
TRISB(2)
08Eh
TRISC
08Fh
Unimplemented
090h
Unimplemented
091h
PIE1
TMR1GIE
ADIE
092h
PIE2
OSFIE
C2IE
C1IE
093h
PIE3
CCP4IE
094h
PIE4(2)
095h
OPTION_REG
WPUEN
INTEDG
STKOVF
STKUNF
DC
BSR<4:0>
TRISB7
TRISB6
TRISB5
TRISB4
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
PCON
WDTCON
098h
OSCTUNE
099h
OSCCON
SPLLEN
09Ah
OSCSTAT
T1OSCR
09Bh
ADRESL
09Ch
ADRESH
09Dh
ADCON0
09Eh
ADCON1
ADFM
09Fh
1:
2:
3:
4:
PD
096h
Note
TO
Working Register
097h
Legend:
RCIE
TXIE
SSP1IE
CCP1IE
EEIE
BCL1IE
CCP3IE
TMR6IE
TMR0CS
TMR0SE
PSA
TMR1IE
CCP2IE
TMR4IE
BCL2IE
SSP2IE
PS<2:0>
RMCLR
RI
POR
WDTPS<4:0>
OSTS
HFIOFR
BOR
HFIOFL
TUN<5:0>
IRCF<3:0>
PLLR
TMR2IE
SCS<1:0>
MFIOFR
LFIOFR
HFIOFS
CHS<4:0>
ADCS<2:0>
GO/DONE
ADNREF
Unimplemented
ADON
ADPREF<1:0>
DS40001440E-page 30
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
100h(1)
INDF0
101h(1)
INDF1
102h(1)
PCL
103h(1)
STATUS
104h(1)
FSR0L
105h(1)
FSR0H
106h(1)
FSR1L
107h(1)
FSR1H
108h(1)
BSR
109h(1)
WREG
10Ah(1)
PCLATH
10Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
10Ch
LATA
LATA5
LATA4
LATA2
LATA1
LATA0
10Dh
LATB(2)
10Eh
LATC
10Fh
Unimplemented
110h
Unimplemented
111h
CM1CON0
C1ON
C1OUT
112h
CM1CON1
C1INTP
C1INTN
113h
CM2CON0
C2ON
C2OUT
114h
CM2CON1
C2INTP
C2INTN
115h
CMOUT
116h
BORCON
SBOREN
TO
PD
BSR<4:0>
LATB7
LATB6
LATB5
LATB4
LATC7(2)
LATC6(2)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
C1OE
C1POL
C1PCH<1:0>
C2OE
C2POL
C2PCH<1:0>
C1SP
C1HYS
C1NCH1
C1NCH0
C2SP
C2HYS
C2SYNC
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DACCON0
DACEN
DACLPS
DACOE
DACPSS<1:0>
119h
DACCON1
11Ah
SRCON0
SRLEN
11Bh
SRCON1
SRSPE
11Ch
11Dh
APFCON0
RXDTSEL
11Eh
APFCON1
11Fh
1:
2:
3:
4:
Working Register
118h
Note
117h
Legend:
DC
C1SYNC
C2NCH<1:0>
MC2OUT
MC1OUT
DACNSS
DACR<4:0>
SRCLK<2:0>
ADFVR<1:0>
SRQEN
SRNQEN
SRPS
SRPR
SRSC2E(2)
SRSC1E
SRRPE
SRRCKE
SRRC2E(2)
SRRC1E
SDO1SEL(3)
SS1SEL(3)
T1GSEL
TXCKSEL
SDO2SEL(2)
SS2SEL(2)
P1DSEL
P1CSEL
P2BSEL
SRSCKE
Unimplemented
Unimplemented
DS40001440E-page 31
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 3
180h(1)
INDF0
181h(1)
INDF1
182h(1)
PCL
183h(1)
STATUS
184h(1)
FSR0L
185h(1)
FSR0H
186h(1)
FSR1L
187h(1)
FSR1H
188h(1)
BSR
189h(1)
WREG
18Ah(1)
PCLATH
18Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
18Ch
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
18Dh
ANSELB(2)
ANSB5
ANSB4
18Eh
ANSELC
ANSC7(2)
ANSC3
ANSC2
ANSC1
ANSC0
18Fh
Unimplemented
190h
Unimplemented
191h
EEADRL
192h
EEADRH
193h
EEDATL
194h
EEDATH
195h
EECON1
196h
EECON2
197h
Unimplemented
198h
Unimplemented
199h
RCREG
19Ah
TXREG
19Bh
SPBRGL
19Ch
SPBRGH
19Dh
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
19Fh
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
Legend:
Note
1:
2:
3:
4:
TO
PD
DC
BSR<4:0>
Working Register
(4)
ANSC6(2)
EEPGD
CFGS
FREE
WRERR
WREN
WR
DS40001440E-page 32
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 4
200h(1)
INDF0
201h(1)
INDF1
202h(1)
PCL
203h(1)
STATUS
204h(1)
FSR0L
205h(1)
FSR0H
206h(1)
FSR1L
207h(1)
FSR1H
208h(1)
BSR
209h(1)
WREG
20Ah(1)
PCLATH
20Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
20Ch
WPUA
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
TO
PD
DC
BSR<4:0>
Working Register
20Dh
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
20Eh
WPUC
WPUC7(2)
WPUC6(2)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
20Fh
Unimplemented
210h
Unimplemented
211h
SSP1BUF
212h
SSP1ADD
ADD<7:0>
213h
SSP1MSK
MSK<7:0>
214h
SSP1STAT
SMP
CKE
D/A
215h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
216h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
217h
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
218h
Unimplemented
219h
SSP2BUF(2)
21Ah
SSP2ADD(2)
ADD<7:0>
21Bh
SSP2MSK(2)
MSK<7:0>
21Ch
SSP2STAT(2)
SMP
CKE
D/A
21Dh
SSP2CON1(2)
WCOL
SSPOV
SSPEN
CKP
21Eh
SSP2CON2(2)
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
21Fh
SSP2CON3(2)
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
Legend:
Note
1:
2:
3:
4:
R/W
UA
BF
SSPM<3:0>
R/W
UA
BF
SSPM<3:0>
DS40001440E-page 33
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 5
280h(1)
INDF0
281h(1)
INDF1
282h(1)
PCL
283h(1)
STATUS
284h(1)
FSR0L
285h(1)
FSR0H
286h(1)
FSR1L
287h(1)
FSR1H
288h(1)
BSR
289h(1)
WREG
28Ah(1)
PCLATH
28Bh(1)
INTCON
GIE
28Ch
Unimplemented
28Dh
Unimplemented
28Eh
Unimplemented
28Fh
Unimplemented
290h
Unimplemented
291h
CCPR1L
292h
CCPR1H
293h
CCP1CON
294h
PWM1CON
295h
CCP1AS
296h
PSTR1CON
297h
Unimplemented
298h
CCPR2L
299h
CCPR2H
29Ah
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
29Bh
PWM2CON
P2RSEN
P2DC6
P2DC5
P2DC4
P2DC3
P2DC2
P2DC1
P2DC0
29Ch
CCP2AS
CCP2ASE
CCP2AS2
CCP2AS1
CCP2AS0
PSS2AC1
PSS2AC0
PSS2BD1
PD
DC
BSR<4:0>
Working Register
P1M<1:0>
TMR0IE
INTE
IOCIE
INTF
CCP1M<3:0>
CCP1AS<2:0>
PSS1AC<1:0>
STR1SYNC
STR1D
PSS1BD<1:0>
STR1C
STR1B
STR1A
PSTR2CON
STR2SYNC
STR2D
STR2C
STR2B
C4TSEL1
C4TSEL0
C3TSEL1
C3TSEL0
C2TSEL1
C2TSEL0
C1TSEL1
29Fh
Unimplemented
DS40001440E-page 34
CCPTMRS
1:
2:
3:
4:
P1DC<6:0>
CCP1ASE
DC1B<1:0>
29Dh
Note
IOCIF
P1RSEN
29Eh
Legend:
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 6
300h(1)
INDF0
301h(1)
INDF1
302h(1)
PCL
303h(1)
STATUS
304h(1)
FSR0L
305h(1)
FSR0H
306h(1)
FSR1L
307h(1)
FSR1H
308h(1)
BSR
309h(1)
WREG
30Ah(1)
PCLATH
30Bh(1)
INTCON
GIE
30Ch
Unimplemented
30Dh
Unimplemented
30Eh
Unimplemented
30Fh
Unimplemented
310h
Unimplemented
311h
CCPR3L
312h
CCPR3H
313h
CCP3CON
314h
Unimplemented
315h
Unimplemented
316h
Unimplemented
317h
Unimplemented
318h
CCPR4L
319h
CCPR4H
31Ah
CCP4CON
31Bh
Unimplemented
31Ch
Unimplemented
31Dh
Unimplemented
31Eh
Unimplemented
31Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
PD
DC
BSR<4:0>
Working Register
TMR0IE
DC3B1
DC4B1
INTE
IOCIE
INTF
IOCIF
CCP3M3
CCP3M2
CCP3M1
CCP3M0
CCP4M3
CCP4M2
CCP4M1
CCP4M0
DS40001440E-page 35
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 7
380h(1)
INDF0
381h(1)
INDF1
382h(1)
PCL
383h(1)
STATUS
384h(1)
FSR0L
385h(1)
FSR0H
386h(1)
FSR1L
387h(1)
FSR1H
388h(1)
BSR
389h(1)
WREG
38Ah(1)
PCLATH
38Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
38Ch
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
38Dh
INLVLB(2)
INLVLB7
INLVLB6
INLVLB5
INLVLB4
38Eh
INLVLC(3)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
INLVLC7
INLVLC6
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
PD
DC
BSR<4:0>
Working Register
INLVLC(2)
38Fh
Unimplemented
390h
Unimplemented
391h
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
392h
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
393h
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
394h
IOCBP(2)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
395h
IOCBN(2)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
396h
IOCBF(2)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
397h
Unimplemented
398h
Unimplemented
399h
Unimplemented
39Ah
CLKRCON
CLKREN
39Bh
39Ch
MDCON
MDEN
39Dh
MDSRC
MDMSODIS
39Eh
MDCARL
MDCLODIS
39Fh
MDCARH
MDCHODIS
Legend:
Note
1:
2:
3:
4:
CLKROE
CLKRSLR
CLKRDC<1:0>
CLKRDIV<2:0>
Unimplemented
MDOE
MDOUT
MDOPOL
MDMS<3:0>
MDCLPOL
MDCLSYNC
MDCL<3:0>
MDCHPOL MDCHSYNC
MDCH<3:0>
MDBIT
DS40001440E-page 36
MDSLR
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 8
400h(1)
INDF0
401h(1)
INDF1
402h(1)
PCL
403h(1)
STATUS
404h(1)
FSR0L
405h(1)
FSR0H
406h(1)
FSR1L
407h(1)
FSR1H
408h(1)
BSR
409h(1)
WREG
40Ah(1)
PCLATH
40Bh(1)
INTCON
GIE
40Ch
Unimplemented
40Dh
Unimplemented
40Eh
Unimplemented
40Fh
Unimplemented
410h
Unimplemented
411h
Unimplemented
412h
Unimplemented
413h
Unimplemented
414h
Unimplemented
415h
TMR4
416h
PR4
417h
T4CON
418h
Unimplemented
419h
Unimplemented
41Ah
Unimplemented
41Bh
Unimplemented
41Ch
TMR6
41Dh
PR6
41Eh
T6CON
41Fh
Legend:
Note
1:
2:
3:
4:
PD
DC
BSR<4:0>
Working Register
TMR0IE
INTE
IOCIE
INTF
IOCIF
TMR4ON
T4CKPS<1:0>
TMR6ON
Unimplemented
T6CKPS<1:0>
DS40001440E-page 37
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Banks 9-30
x00h/
x80h(1)
INDF0
x00h/
x81h(1)
INDF1
x02h/
x82h(1)
PCL
x03h/
x83h(1)
STATUS
x04h/
x84h(1)
FSR0L
x05h/
x85h(1)
FSR0H
x06h/
x86h(1)
FSR1L
x07h/
x87h(1)
FSR1H
x08h/
x88h(1)
BSR
x09h/
x89h(1)
WREG
x0Ah/
x8Ah(1)
PCLATH
x0Bh/
x8Bh(1)
INTCON
GIE
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note
1:
2:
3:
4:
TO
PD
DC
BSR<4:0>
Working Register
TMR0IE
INTE
IOCIE
Unimplemented
INTF
IOCIF
DS40001440E-page 38
PIC16(L)F1825/9
TABLE 3-8:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 31
F80h(1)
INDF0
F81h(1)
INDF1
F82h(1)
PCL
F83h(1)
STATUS
F84h(1)
FSR0L
F85h(1)
FSR0H
F86h(1)
FSR1L
F87h(1)
FSR1H
F88h(1)
BSR
F89h(1)
WREG
F8Ah(1)
PCLATH
F8Bh(1)
INTCON
GIE
F8Ch
FE3h
FE4h
STATUS_
PD
DC
BSR<4:0>
Working Register
TMR0IE
INTE
IOCIE
INTF
IOCIF
Unimplemented
Z_SHAD
DC_SHAD
C_SHAD
SHAD
FE5h
WREG_
SHAD
FE6h
BSR_
SHAD
FE7h
PCLATH_
SHAD
FE8h
FSR0L_
SHAD
FE9h
FSR0H_
SHAD
FEAh
FSR1L_
SHAD
FEBh
FSR1H_
SHAD
FECh
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Legend:
Note
1:
2:
3:
4:
Unimplemented
DS40001440E-page 39
PIC16(L)F1825/9
3.3
3.3.2
FIGURE 3-3:
14
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
PC
6
PCLATH
Instruction with
PCL as
Destination
ALU Result
14
PCH
PCL
GOTO, CALL
PC
6 4
PCLATH
11
OPCODE <10:0>
14
PCH
PCL
PC
6
PCLATH
CALLW
14
PCH
PCL
PC
BRW
15
PC + W
14
PCH
PCL
PC
BRA
15
PC + OPCODE <8:0>
3.3.1
3.3.3
3.3.4
COMPUTED GOTO
BRANCHING
MODIFYING PCL
DS40001440E-page 40
PIC16(L)F1825/9
3.4
3.4.1
Stack
Note:
FIGURE 3-4:
TOSH:TOSL
0x0F
STKPTR = 0x1F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
0x1F
0x0000
STKPTR = 0x1F
DS40001440E-page 41
PIC16(L)F1825/9
FIGURE 3-5:
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-6:
0x00
Return Address
STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS40001440E-page 42
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x06
PIC16(L)F1825/9
FIGURE 3-7:
TOSH:TOSL
3.4.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
3.5
Indirect Addressing
DS40001440E-page 43
PIC16(L)F1825/9
FIGURE 3-8:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x1000
0x1FFF
0x0FFF
Reserved
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
0x7FFF
0x8000
Reserved
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS40001440E-page 44
PIC16(L)F1825/9
3.5.1
FIGURE 3-9:
BSR
Indirect Addressing
From Opcode
7
0
Bank Select
Location Select
FSRxH
0
FSRxL
0
Bank Select
11111
Bank 31
Location Select
0x00
0x7F
DS40001440E-page 45
PIC16(L)F1825/9
3.5.2
3.5.3
FIGURE 3-10:
7
FSRnH
0 0 1
FSRnL
FIGURE 3-11:
7
1
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
FSRnL
0x8000
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
DS40001440E-page 46
0xF6F
0xFFFF
0x7FFF
PIC16(L)F1825/9
4.0
DEVICE CONFIGURATION
4.1
Configuration Words
DS40001440E-page 47
PIC16(L)F1825/9
REGISTER 4-1:
CONFIGURATION WORD 1
R/P-1/1
R/P-1/1
R/P-1/1
FCMEN
IESO
CLKOUTEN
R/P-1/1
R/P-1/1
BOREN<1:0>
bit 13
R/P-1/1
R/P-1/1
R/P-1/1
CP
MCLRE
PWRTE
R/P-1/1
CPD
bit 8
R/P-1/1
R/P-1/1
R/P-1/1
WDTE<1:0>
R/P-1/1
R/P-1/1
FOSC<2:0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
Note 1:
2:
3:
DS40001440E-page 48
PIC16(L)F1825/9
REGISTER 4-1:
bit 2-0
Note 1:
2:
3:
DS40001440E-page 49
PIC16(L)F1825/9
REGISTER 4-2:
CONFIGURATION WORD 2
R/P-1/1
R/P-1/1
U-1
R/P-1/1
R/P-1/1
R/P-1/1
LVP(1)
DEBUG(2)
BORV
STVREN
PLLEN
bit 13
bit 8
U-1
U-1
U-1
R-1
U-1
U-1
Reserved
R/P-1/1
R/P-1/1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
Legend:
bit 13
bit 12
bit 11
Unimplemented: Read as 1
bit 10
bit 9
bit 8
bit 7-5
Unimplemented: Read as 1
bit 4
bit 3-2
Unimplemented: Read as 1
bit 1-0
Note 1:
2:
3:
The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and
programmers. For normal device operation, this bit should be maintained as a 1.
See Vbor parameter for specific trip point voltages.
DS40001440E-page 50
PIC16(L)F1825/9
4.2
Code Protection
4.2.1
4.2.2
4.3
Write Protection
4.4
User ID
DS40001440E-page 51
PIC16(L)F1825/9
4.5
REGISTER 4-3:
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 13
bit 8
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
0 = Bit is cleared
bit 13-5
bit 4-0
1 = Bit is set
DS40001440E-page 52
PIC16(L)F1825/9
5.0
5.1
Overview
DS40001440E-page 53
PIC16(L)F1825/9
SIMPLIFIED PIC MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 5-1:
External
Oscillator
OSC2
Sleep
4 x PLL
Oscillator Timer1
FOSC<2:0> = 100
T1OSO
T1OSCEN
Enable
Oscillator
IRCF<3:0>
HFPLL
500 kHz
Source
16 MHz
(HFINTOSC)
Postscaler
Internal
Oscillator
Block
500 kHz
(MFINTOSC)
31 kHz
Source
31 kHz
31 kHz (LFINTOSC)
DS40001440E-page 54
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
MUX
T1OSI
Sleep
T1OSC
MUX
OSC1
CPU and
Peripherals
Internal Oscillator
Clock
Control
FOSC<2:0> SCS<1:0>
Clock Source Option
for other modules
PIC16(L)F1825/9
5.2
5.2.1
FIGURE 5-2:
OSC1/CLKIN
Clock from
Ext. System
PIC MCU
FOSC/4 or I/O(1)
Note 1:
OSC2/CLKOUT
5.2.1.1
Clock
Switchingfor
more
EC Mode
5.2.1.2
DS40001440E-page 55
PIC16(L)F1825/9
FIGURE 5-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC MCU
PIC MCU
OSC1/CLKIN
C1
To Internal
Logic
Quartz
Crystal
C2
Note 1:
2:
OSC1/CLKIN
RS(1)
RF(2)
C1
Sleep
OSC2/CLKOUT
RP(3)
C2 Ceramic
RS(1)
Resonator
Note 1:
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
DS40001440E-page 56
To Internal
Logic
RF(2)
Sleep
OSC2/CLKOUT
5.2.1.3
PIC16(L)F1825/9
5.2.1.4
4xPLL
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
5.2.1.5
TIMER1 Oscillator
FIGURE 5-5:
QUARTZ CRYSTAL
OPERATION (TIMER1
OSCILLATOR)
PIC MCU
T1OSI
C1
To Internal
Logic
32.768 kHz
Quartz
Crystal
C2
5.2.1.6
External RC Mode
T1OSO
DS40001440E-page 57
PIC16(L)F1825/9
FIGURE 5-6:
EXTERNAL RC MODES
VDD
REXT
Internal
Clock
CEXT
VSS
FOSC/4 or I/O(1)
OSC2/CLKOUT
2.
3.
DS40001440E-page 58
PIC MCU
OSC1/CLKIN
5.2.2
PIC16(L)F1825/9
5.2.2.1
HFINTOSC
5.2.2.2
MFINTOSC
The
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 5-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 Internal
Oscillator Clock Switch Timing for more information.
The MFINTOSC is enabled by:
Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
FOSC<2:0> = 100, or
Set the System Clock Source (SCS) bits of the
OSCCON register to 1x
The Medium-Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running and can be utilized.
5.2.2.3
5.2.2.4
LFINTOSC
DS40001440E-page 59
PIC16(L)F1825/9
5.2.2.5
DS40001440E-page 60
5.2.2.6
PIC16(L)F1825/9
5.2.2.7
5.
6.
7.
DS40001440E-page 61
PIC16(L)F1825/9
FIGURE 5-7:
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
Running
LFINTOSC
0
IRCF <3:0>
System Clock
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC
Oscillator Delay(1) 2-cycle Sync
Running
HFINTOSC/
MFINTOSC
IRCF <3:0>
=0
System Clock
Note 1:
DS40001440E-page 62
PIC16(L)F1825/9
5.3
Clock Switching
5.3.3
TIMER1 OSCILLATOR
5.3.1
5.3.4
5.3.2
DS40001440E-page 63
PIC16(L)F1825/9
5.4
5.4.1
Note:
TABLE 5-1:
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
Sleep/POR
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
EC, RC(1)
DC 32 MHz
2 cycles
LFINTOSC
EC,
RC(1)
DC 32 MHz
1 cycle of each
Sleep/POR
Timer1 Oscillator
LP, XT, HS(1)
32 kHz-20 MHz
MFINTOSC(1)
HFINTOSC(1)
2 s (approx.)
LFINTOSC(1)
31 kHz
1 cycle of each
Timer1 Oscillator
32 kHz
PLL inactive
PLL active
16-32 MHz
2 ms (approx.)
Note 1:
PLL inactive.
DS40001440E-page 64
PIC16(L)F1825/9
5.4.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
5.4.3
FIGURE 5-8:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC
PC + 1
System Clock
DS40001440E-page 65
PIC16(L)F1825/9
5.5
5.5.3
FIGURE 5-9:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
5.5.1
FAIL-SAFE DETECTION
5.5.2
5.5.4
Clock
Failure
Detected
FAIL-SAFE OPERATION
DS40001440E-page 66
PIC16(L)F1825/9
FIGURE 5-10:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS40001440E-page 67
PIC16(L)F1825/9
5.6
REGISTER 5-1:
R/W-0/0
SPLLEN
R/W-1/1
R/W-1/1
IRCF<3:0>
R/W-1/1
U-0
R/W-0/0
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
bit 2
Unimplemented: Read as 0
bit 1-0
Note 1:
DS40001440E-page 68
PIC16(L)F1825/9
REGISTER 5-2:
R-1/q
R-0/q
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
T1OSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
q = Conditional
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001440E-page 69
PIC16(L)F1825/9
REGISTER 5-3:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
000001 =
000000 = Oscillator module is running at the factory-calibrated frequency.
111111 =
TABLE 5-2:
Name
Bit 7
OSCCON
SPLLEN
OSCSTAT
T1OSCR
OSCTUNE
Bit 6
Bit 5
PLLR
OSTS
Bit 4
Bit 3
Bit 2
HFIOFR
HFIOFL
MFIOFR
BCL1IE
IRCF<3:0>
PIE2
OSFIE
C2IE
C1IE
EEIE
PIR2
OSFIF
C2IF
C1IF
EEIF
T1CON
Legend:
CONFIG1
Legend:
Bit 0
SCS<1:0>
T1CKPS<1:0>
Register
on Page
68
LFIOFR
HFIOFS
69
CCP2IE
89
BCL1IF
CCP2IF
93
T1OSCEN
T1SYNC
TMR1ON
185
TUN<5:0>
TMR1CS<1:0>
70
Unimplemented location, read as 0. Shaded cells are not used by clock sources.
TABLE 5-3:
Name
Bit 1
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
Bit 9/1
BOREN<1:0>
WDTE<1:0>
FOSC<2:0>
Bit 8/0
CPD
Register
on Page
48
Unimplemented location, read as 0. Shaded cells are not used by clock sources.
DS40001440E-page 70
PIC16(L)F1825/9
6.0
6.3
6.3.1
OSCILLATOR MODES
6.3.2
CLKOUT FUNCTION
6.4
6.1
Slew Rate
6.2
Effects of a Reset
DS40001440E-page 71
PIC16(L)F1825/9
6.5
REGISTER 6-1:
R/W-0/0
R/W-0/0
R/W-1/1
CLKREN
CLKROE
CLKRSLR
R/W-1/1
R/W-0/0
R/W-0/0
CLKRDC<1:0>
R/W-0/0
R/W-0/0
CLKRDIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4-3
bit 2-0
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
Word 1 = 0 will result in FOSC/4. See Section 6.3 Conflicts with the CLKR Pin for details.
DS40001440E-page 72
PIC16(L)F1825/9
TABLE 6-1:
Name
CLKRCON
Legend:
Bit 7
Bit 6
Bit 5
CLKREN
CLKROE
CLKRSLR
CONFIG1
Legend:
Bit 3
CLKRDC<1:0>
Bit 2
Bit 1
Bit 0
CLKRDIV<2:0>
Register
on Page
72
Unimplemented locations read as 0. Shaded cells are not used by reference clock sources.
TABLE 6-2:
Name
Bit 4
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
CPD
Register
on Page
48
Unimplemented locations read as 0. Shaded cells are not used by reference clock sources.
DS40001440E-page 73
PIC16(L)F1825/9
7.0
RESETS
FIGURE 7-1:
MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
BOR
Enable
PWRT
Zero
LFINTOSC
64 ms
PWRTEN
DS40001440E-page 74
PIC16(L)F1825/9
7.1
7.2
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
7.1.1
TABLE 7-1:
Device Operation
upon Wake-up from
Sleep
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
Active
Awake
Active
10
Sleep
Disabled
Active
Begins immediately
Disabled
Begins immediately
Disabled
Begins immediately
01
00
Note 1:
In these specific cases, Release of POR and the Wake-up from Sleep, there is no delay in start-up. The
BOR Ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the
BOR circuit is forced on by the BOREN<1:0> bits.
7.2.1
BOR IS ALWAYS ON
7.2.3
7.2.2
DS40001440E-page 75
PIC16(L)F1825/9
FIGURE 7-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
TPWRT(1)
REGISTER 7-1:
R/W-1/u
U-0
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-1
Unimplemented: Read as 0
bit 0
DS40001440E-page 76
PIC16(L)F1825/9
7.3
MCLR
7.7
TABLE 7-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
Disabled
Enabled
Enabled
7.3.1
MCLR ENABLED
7.3.2
MCLR DISABLED
7.4
7.5
7.8
Power-Up Timer
7.9
Start-up Sequence
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 5.0 Oscillator Module (With Fail-Safe
Clock Monitor) for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 7-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
RESET Instruction
7.6
DS40001440E-page 77
PIC16(L)F1825/9
FIGURE 7-3:
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Internal Oscillator
Oscillator
FOSC
FOSC
DS40001440E-page 78
PIC16(L)F1825/9
7.10
TABLE 7-3:
STKOVF STKUNF
RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
TABLE 7-4:
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
0000h
---u uuuu
uu-- 0uuu
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
---u uuuu
uu-- u0uu
Condition
PC + 1
(1)
0000h
0000h
---u uuuu
1u-- uuuu
0000h
---u uuuu
u1-- uuuu
DS40001440E-page 79
PIC16(L)F1825/9
7.11
REGISTER 7-2:
R/W/HS-0/q
R/W/HS-0/q
U-0
U-0
R/W/HC-1/q
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
STKOVF
STKUNF
RMCLR
RI
POR
BOR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40001440E-page 80
PIC16(L)F1825/9
TABLE 7-5:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORRDY
76
PCON
STKOVF
STKUNF
RMCLR
RI
POR
BOR
80
STATUS
TO
PD
DC
22
WDTCON
SWDTEN
100
WDTPS<4:0>
Legend: Unimplemented bit, reads as 0. Shaded cells are not used by Resets.
DS40001440E-page 81
PIC16(L)F1825/9
8.0
INTERRUPTS
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
FIGURE 8-1:
INTERRUPT LOGIC
Interrupt to CPU
INTE
IOCIF
IOCIE
From Peripheral Interrupt
Logic (Figure 8-2)
PEIE
GIE
DS40001440E-page 82
PIC16(L)F1825/9
8.1
Operation
8.2
Interrupt Latency
DS40001440E-page 83
PIC16(L)F1825/9
FIGURE 8-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Inst(PC)
Interrupt
GIE
PC
Execute
PC-1
PC
2 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
DS40001440E-page 84
PC+2
NOP
NOP
PIC16(L)F1825/9
FIGURE 8-3:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF
(5)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 30.0 Electrical Specifications.
5:
DS40001440E-page 85
PIC16(L)F1825/9
8.3
8.4
INT Pin
8.5
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
DS40001440E-page 86
PIC16(L)F1825/9
8.6
8.6.1
INTCON REGISTER
REGISTER 8-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCxF register
have been cleared by software.
DS40001440E-page 87
PIC16(L)F1825/9
8.6.2
PIE1 REGISTER
REGISTER 8-2:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001440E-page 88
PIC16(L)F1825/9
8.6.3
PIE2 REGISTER
REGISTER 8-3:
R/W-0/0
OSFIE
Note:
C2IE
R/W-0/0
R/W-0/0
C1IE
EEIE
R/W-0/0
U-0
U-0
R/W-0/0
BCL1IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
DS40001440E-page 89
PIC16(L)F1825/9
8.6.4
PIE3 REGISTER
REGISTER 8-4:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
CCP4IE
CCP3IE
TMR6IE
TMR4IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
Unimplemented: Read as 0
DS40001440E-page 90
PIC16(L)F1825/9
PIE4 REGISTER(1)
8.6.5
REGISTER 8-5:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
BCL2IE
SSP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
DS40001440E-page 91
PIC16(L)F1825/9
8.6.6
PIR1 REGISTER
REGISTER 8-6:
Note:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001440E-page 92
PIC16(L)F1825/9
8.6.7
PIR2 REGISTER
REGISTER 8-7:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
Unimplemented: Read as 0
DS40001440E-page 93
PIC16(L)F1825/9
8.6.8
PIR3 REGISTER
REGISTER 8-8:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
CCP4IF
CCP3IF
TMR6IF
TMR4IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
Unimplemented: Read as 0
DS40001440E-page 94
PIC16(L)F1825/9
PIR4 REGISTER(1)
8.6.9
REGISTER 8-9:
U-0
U-0
U-0
U-0
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
BCL2IF
SSP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
TABLE 8-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
PIE3
CCP4IE
CCP3IE
TMR6IE
OPTION_REG
(1)
PS<2:0>
176
TMR2IE
TMR1IE
88
CCP2IE
89
TMR4IE
90
PIE4
BCL2IE
SSP2IE
91
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
PIR3
CCP4IF
CCP3IF
TMR6IF
TMR4IF
94
BCL2IF
SSP2IF
95
(1)
PIR4
Legend:
Note 1:
DS40001440E-page 95
PIC16(L)F1825/9
9.0
DS40001440E-page 96
9.1
9.1.1
PIC16(L)F1825/9
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 9-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
TOST(3)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
PC + 1
Inst(PC) = Sleep
Inst(PC - 1)
PC + 2
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
TABLE 9-1:
Name
Bit 7
Bit 6
Bit 5
INTCON
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
138
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
138
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
137
IOCBF(1)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
139
IOCBN(1)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
139
IOCBP(1)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
138
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
89
PIE1
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
BCL2IE
SSP2IE
91
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
SSP2IF
95
22
SWDTEN
100
PIE2
PIE4(1)
PIR4
BCL2IF
STATUS
TO
PD
DC
WDTCON
(1)
Legend:
Note 1:
WDTPS<4:0>
DS40001440E-page 97
PIC16(L)F1825/9
10.0
WATCHDOG TIMER
FIGURE 10-1:
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
DS40001440E-page 98
WDTPS<4:0>
PIC16(L)F1825/9
10.1
10.3
10.2
WDT IS ALWAYS ON
10.2.2
TABLE 10-1:
by
10.4
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail event
WDT is disabled
Oscillator Start-up TImer (OST) is running
10.2.3
10.2.1
Time-Out Period
Sleep.
See
WDTE<1:0>
SWDTEN
Device
Mode
11
10
WDT
Mode
10.5
Active
Awake Active
Sleep
01
0
00
TABLE 10-2:
Disabled
Active
Disabled
Disabled
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Cleared
DS40001440E-page 99
PIC16(L)F1825/9
10.6
REGISTER 10-1:
U-0
U-0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>
R/W-0/0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-1
bit 0
Note 1:
DS40001440E-page 100
PIC16(L)F1825/9
TABLE 10-3:
Name
Bit 6
OSCCON
SPLLEN
STATUS
WDTCON
Legend:
CONFIG1
Legend:
Bit 4
Bit 3
IRCF<3:0>
Bit 2
TO
PD
Bit 1
Bit 0
SCS<1:0>
DC
WDTPS<4:0>
Register
on Page
68
22
SWDTEN
100
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by Watchdog Timer.
TABLE 10-4:
Name
Bit 5
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
WDTE<1:0>
CPD
FOSC<2:0>
Register
on Page
48
Unimplemented location, read as 0. Shaded cells are not used by Watchdog Timer.
DS40001440E-page 101
PIC16(L)F1825/9
11.0
EECON1
EECON2
EEDATL
EEDATH
EEADRL
EEADRH
11.1
11.1.1
DS40001440E-page 102
PIC16(L)F1825/9
11.2
11.2.1
EXAMPLE 11-1:
BANKSEL EEADRL
;
MOVLW
DATA_EE_ADDR ;
MOVWF
EEADRL
;Data Memory
;Address to read
BCF
EECON1, CFGS ;Deselect Config space
BCF
EECON1, EEPGD;Point to DATA memory
BSF
EECON1, RD
;EE Read
MOVF
EEDATL, W
;W = EEDATL
Note:
11.2.2
11.2.3
11.2.4
DS40001440E-page 103
PIC16(L)F1825/9
Required
Sequence
EXAMPLE 11-2:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
EEADRL
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
EECON1, CFGS
EECON1, EEPGD
EECON1, WREN
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
;Point to DATA memory
;Enable writes
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BTFSC
GOTO
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
EECON1,
$-2
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable Interrupts
;Disable writes
;Wait for write to complete
;Done
FIGURE 11-1:
GIE
WR
GIE
WREN
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
EEADRH,EEADRL
INSTR (PC + 1)
BSF EECON1,RD
executed here
PC
+3
PC+3
EEDATH,EEDATL
INSTR(PC + 1)
executed here
PC + 5
PC + 4
INSTR (PC + 3)
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDATL
Register
EERHLT
DS40001440E-page 104
PIC16(L)F1825/9
11.3
11.3.1
TABLE 11-1:
Device
PIC16(L)F1825
PIC16(L)F1829
FLASH MEMORY
ORGANIZATION BY DEVICE
Erase Block
(Row) Size/
Boundary
Number of
Write Latches/
Boundary
32 words,
EEADRL<4:0>
= 00000
32 words,
EEADRL<4:0>
= 00000
DS40001440E-page 105
PIC16(L)F1825/9
EXAMPLE 11-3:
EEADRL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
INTCON,GIE
;
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
;
;
;
;
DS40001440E-page 106
PIC16(L)F1825/9
11.3.2
11.3.3
DS40001440E-page 107
PIC16(L)F1825/9
After the BSF EECON1,WR instruction, the processor
requires two cycles to set up the write operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
FIGURE 11-2:
0 7
EEDATH
EEDATA
14
EEADRL<4:0> = 00000
14
EEADRL<4:0> = 00001
Buffer Register
14
EEADRL<4:0> = 00010
Buffer Register
14
EEADRL<4:0> = 11111
Buffer Register
Buffer Register
Program Memory
DS40001440E-page 108
PIC16(L)F1825/9
EXAMPLE 11-4:
Required
Sequence
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
BSF
BSF
INTCON,GIE
EEADRL
ADDRL,W
EEADRL
ADDRH,W
EEADRH
EECON1,EEPGD
EECON1,CFGS
EECON1,FREE
EECON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
EECON2
0AAh
EECON2
EECON1,WR
NOP
;
;
;
;
;
;
;
;
EECON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
DS40001440E-page 109
PIC16(L)F1825/9
EXAMPLE 11-5:
;
;
;
;
;
;
;
INTCON,GIE
EEADRH
ADDRH,W
EEADRH
ADDRL,W
EEADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
;
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
EEDATL
FSR0++
EEDATH
MOVF
XORLW
ANDLW
BTFSC
GOTO
EEADRL,W
0x07
0x07
STATUS,Z
START_WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
EECON2
0AAh
EECON2
EECON1,WR
;
;
;
;
;
;
;
;
Required
Sequence
LOOP
NOP
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
EEADRL,F
LOOP
EECON1,LWLO
55h
EECON2
0AAh
EECON2
EECON1,WR
;
;
;
;
;
;
;
;
NOP
BCF
BSF
DS40001440E-page 110
EECON1,WREN
INTCON,GIE
PIC16(L)F1825/9
11.4
TABLE 11-2:
11.5
Address
Function
Read Access
Write Access
8000h-8003h
8006h
8007h-8008h
User IDs
Device ID/Revision ID
Configuration Words 1 and 2
Yes
Yes
Yes
Yes
No
No
EXAMPLE 11-3:
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
EEADRL
PROG_ADDR_LO
EEADRL
EEADRH
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
INTCON,GIE
EECON1,RD
INTCON,GIE
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
;
;
;
;
DS40001440E-page 111
PIC16(L)F1825/9
11.6
Write Verify
EXAMPLE 11-6:
BANKSEL EEDATL
MOVF
EEDATL, W
BSF
XORWF
BTFSS
GOTO
:
;
;EEDATL not changed
;from previous write
EECON1, RD ;YES, Read the
;value written
EEDATL, W ;
STATUS, Z ;Is data the same
WRITE_ERR ;No, handle error
;Yes, continue
DS40001440E-page 112
PIC16(L)F1825/9
11.7
REGISTER 11-1:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory
REGISTER 11-2:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 11-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
REGISTER 11-4:
U-1
R/W-0/0
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 1
bit 6-0
Note
EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address
1:
Unimplemented, read as 1.
DS40001440E-page 113
PIC16(L)F1825/9
REGISTER 11-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W/HC-0/0
R/W-x/q
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001440E-page 114
PIC16(L)F1825/9
REGISTER 11-6:
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 11-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
EECON1
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
114
EEADRL<7:0>
(1)
INTCON
113
EEADRH<6:0
EEDATL
EEDATH
115*
113
EEDATL<7:0>
113
EEDATH<5:0>
113
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
89
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
Legend: Unimplemented location, read as 0. Shaded cells are not used by data EEPROM module.
* Page provides register information.
Note 1: Unimplemented, read as 1.
DS40001440E-page 115
PIC16(L)F1825/9
12.0
I/O PORTS
FIGURE 12-1:
Read LATx
D
Write LATx
Write PORTx
CK
VDD
Data Bus
I/O pin
Read PORTx
To peripherals
ANSELx
EXAMPLE 12-1:
PIC16(L)F1825
PIC16(L)F1829
PORTC
Device
PORTB
TABLE 12-1:
Data Register
TRISx
;
;
;
;
VSS
INITIALIZING PORTA
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
DS40001440E-page 116
PIC16(L)F1825/9
12.1
RX/DT/TX/CK
SDO1
SS (Slave Select)
T1G
P1B/P1C/P1D/P2B
CCP1/P1A/CCP2
DS40001440E-page 117
PIC16(L)F1825/9
REGISTER 12-1:
R/W-0/0
R/W-0/0
R/W-0/0
RXDTSEL
SDO1SEL
SS1SEL
U-0
R/W-0/0
R/W-0/0
U-0
U-0
T1GSEL
TXCKSEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1-0
Unimplemented: Read as 0
DS40001440E-page 118
PIC16(L)F1825/9
REGISTER 12-2:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SDO2SEL(1)
SS2SEL(1)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PIC16(L)F1829 only.
DS40001440E-page 119
PIC16(L)F1825/9
12.2
PORTA Registers
12.2.1
ANSELA REGISTER
EXAMPLE 12-2:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTA
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
DS40001440E-page 120
PIC16(L)F1825/9
12.2.2
TABLE 12-2:
Pin Name
Note 1:
2:
RA0
ICSPDAT
ICDDAT
DACOUT
RA1
ICSPCLK
ICDCLK
RX/DT(2)
RA2
SRQ
C1OUT
CCP3
RA3
RA4
CLKOUT
T1OSO
CLKR
SDO1
P2B(2)
RA5
DS40001440E-page 121
PIC16(L)F1825/9
REGISTER 12-3:
U-0
U-0
R/W-x/x
R/W-x/x
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-4:
U-0
U-0
R/W-1/1
R/W-1/1
R-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
bit 2-0
DS40001440E-page 122
PIC16(L)F1825/9
REGISTER 12-5:
U-0
U-0
R/W-x/u
R/W-x/u
U-0
R/W-x/u
R/W-x/u
R/W-x/u
LATA5
LATA4
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-6:
U-0
U-0
U-0
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
ANSA4
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3
Unimplemented: Read as 0
bit 2-0
ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001440E-page 123
PIC16(L)F1825/9
REGISTER 12-7:
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
REGISTER 12-8:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-0/0
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001440E-page 124
PIC16(L)F1825/9
TABLE 12-3:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
123
APFCON0
RXDTSEL
SDO1SEL(2)
SS1SEL(2)
T1GSEL
TXCKSEL
118
APFCON1
SDO2SEL(1)
SS2SEL(1)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
119
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
LATA
LATA5
LATA4
LATA2
LATA1
LATA0
123
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PORTA
RA5
RA4
RA3
RA0
122
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
WPUA
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
124
Bit 8/0
Register
on Page
Name
ANSELA
OPTION_REG
Legend:
Note 1:
2:
CONFIG1
Legend:
RA2
176
RA1
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.
PIC16(L)F1829 only.
PIC16(L)F1825 only.
TABLE 12-4:
Name
PS<2:0>
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
WDTE<1:0>
Bit 9/1
BOREN<1:0>
CPD
FOSC<2:0>
48
DS40001440E-page 125
PIC16(L)F1825/9
12.3
PORTB Registers
(PIC16(L)F1829 only)
12.3.1
ANSELB REGISTER
DS40001440E-page 126
PIC16(L)F1825/9
12.3.2
TABLE 12-5:
Pin Name
Note 1:
2:
RB4
SDA
RB5
SDA2
RX(2)/DT(2)
RB6
SCL/SCK
RB7
TX(2)/CK(2)
DS40001440E-page 127
PIC16(L)F1825/9
REGISTER 12-9:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
RB7
RB6
RB5
RB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
TRISB7
TRISB6
TRISB5
TRISB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
LATB7
LATB6
LATB5
LATB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
DS40001440E-page 128
PIC16(L)F1825/9
REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
ANSB5
ANSB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3-0
Unimplemented: Read as 0
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
WPUB7
WPUB6
WPUB5
WPUB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
INLVLB7
INLVLB6
INLVLB5
INLVLB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 7-6
Unimplemented: Read as 0
DS40001440E-page 129
PIC16(L)F1825/9
TABLE 12-6:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELB
ANSB5
ANSB4
129
INLVLB
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
LATB7
LATB6
LATB5
LATB4
128
Name
LATB
PORTB
RB7
RB6
RB5
RB4
128
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
128
WPUB7
WPUB6
WPUB5
WPUB4
129
WPUB
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by PORTB.
PIC16(L)F1829 only.
DS40001440E-page 130
PIC16(L)F1825/9
12.4
PORTC Registers
12.4.1
ANSELC REGISTER
DS40001440E-page 131
PIC16(L)F1825/9
12.4.2
TABLE 12-7:
Pin Name
Function Priority(1)
RC0
RC1
RC2
SDO1(2) (PIC16(L)F1825
only)
P1D(2)
P2B(2)
RC3
RC4
MDOUT
SRNQ
C2OUT
TX(2)/CK(2)
P1B
RC5
RX(2)/DT(2)
CCP1/P1A
RC6(3)
SS1
CCP4
RC7(3)
SDO1
Note 1:
2:
3:
DS40001440E-page 132
PIC16(L)F1825/9
REGISTER 12-15: PORTC: PORTC REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC7(1)
RC6(1)
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
RC<7:0>: PORTC General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
RC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
Note 1:
TRISC7
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
TRISC<7:0>: PORTC Tri-State Control bits(1)
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
bit 7-0
Note 1:
TRISC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
R/W-x/u
LATC7(2)
(2)
LATC6
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
LATC<7:0>: PORTC Output Latch Value bits(1, 2)
bit 7-0
Note 1:
2:
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
LATC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
DS40001440E-page 133
PIC16(L)F1825/9
REGISTER 12-18: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSC7(2)
ANSC6(2)
ANSC3
ANSC2
ANSC1
ANSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively(2)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 5-4
Unimplemented: Read as 0
bit 3-0
ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSELC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUC7(3)
WPUC6(3)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
2:
3:
DS40001440E-page 134
PIC16(L)F1825/9
REGISTER 12-20: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER
U-0(3)
U-0(3)
(2)
(2)
R/W-1/1
R/W-1/1
INLVLC7(1)
INLVLC6(1)
R/W-0/0(3)
R/W-0/0(3)
R/W-0/0(3)
R/W-0/0(3)
R/W-0/0(3)
R/W-0/0(3)
(2)
(2)
(2)
(2)
(2)
R/W-1/1(2)
R/W-1/1
R/W-1/1
INLVLC5
INLVLC4
R/W-1/1
INLVLC3
R/W-1/1
INLVLC2
R/W-1/1
INLVLC1
INLVLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
INLVLC<7:0>: PORTC Input Level Select bits(1)
For RC<7:0> pins, respectively
1 = ST input used for port reads and interrupt-on-change
0 = TTL input used for port reads and interrupt-on-change
bit 7-0
Note 1:
2:
3:
INLVLC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0.
PIC16(L)F1829 only, Reset default value.
PIC16(L)F1825 only, Reset default value.
TABLE 12-8:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
129
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
LATC7(1)
LATC6(1)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
128
PORTC
RC7(1)
RC6(1)
RC5
RC4
RC3
RC2
RC1
RC0
128
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
128
WPUC
WPUC7(1)
WPUC6(1)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
129
Name
ANSELC
INLVLC
LATC
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by PORTC.
PIC16(L)F1829 only.
DS40001440E-page 135
PIC16(L)F1825/9
13.0
INTERRUPT-ON-CHANGE
13.1
13.3
Interrupt Flags
13.4
EXAMPLE 13-1:
13.2
MOVLW
XORWF
ANDWF
13.5
CLEARING
INTERRUPT FLAGS
(PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
DS40001440E-page 136
PIC16(L)F1825/9
FIGURE 13-1:
IOCANx
Q4Q1
CK
Edge
Detect
RAx
IOCAPx
Data Bus =
0 or 1
Write IOCAFx
CK
To Data Bus
IOCAFx
CK
IOCIE
R
Q2
From all other
IOCAFx individual
pin detectors
Q1
Q2
Q2
Q3
Q4
Q4Q1
13.6
Q1
Q1
Q2
Q3
Q4
IOC interrupt
to CPU core
Q3
Q4
Q4Q1
Q4
Q4Q1
Q4Q1
Interrupt-on-Change Registers
REGISTER 13-1:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001440E-page 137
PIC16(L)F1825/9
REGISTER 13-2:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-3:
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-4:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBP7
IOCBP6
IOCBP5
IOCBP4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
DS40001440E-page 138
PIC16(L)F1825/9
REGISTER 13-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 5-0
Unimplemented: Read as 0
REGISTER 13-6:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBF7
IOCBF6
IOCBF5
IOCBF4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 5-0
Unimplemented: Read as 0
DS40001440E-page 139
PIC16(L)F1825/9
TABLE 13-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
123
ANSELB
ANSB5
ANSB4
129
INLVLA
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
Name
ANSELA
(1)
INLVLA5
INLVLA4
INLVLB(1)
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
138
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
138
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
137
IOCAF
IOCAN
IOCAP
IOCAP5
IOCBF(1)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
139
(1)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
139
(1)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
138
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISB7
TRISB6
TRISB5
TRISB4
128
IOCBN
IOCBP
TRISA
(1)
TRISB
Legend: Unimplemented location, read as 0. Shaded cells are not used by interrupt-on-change.
Note 1: PIC16(L)F1829 only.
DS40001440E-page 140
PIC16(L)F1825/9
14.0
14.1
14.2
FIGURE 14-1:
CDAFVR<1:0>
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
X1
X2
X4
FVR BUFFER2
(To Comparators, DAC, CPS)
FVREN
+
_
FVRRDY
DS40001440E-page 141
PIC16(L)F1825/9
14.3
REGISTER 14-1:
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
FVREN
FVRRDY(1)
TSEN
TSRNG
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
TABLE 14-1:
Name
FVRCON
Legend:
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
142
DS40001440E-page 142
PIC16(L)F1825/9
15.0
TEMPERATURE INDICATOR
MODULE
FIGURE 15-1:
VDD
TSEN
TSRNG
15.1
TEMPERATURE CIRCUIT
DIAGRAM
VOUT
ADC
MUX
ADC
n
CHS bits
(ADCON0 register)
Circuit Operation
EQUATION 15-1:
VOUT RANGES
15.2
TABLE 15-1:
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 14.0 Fixed Voltage Reference (FVR) for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
3.6V
1.8V
15.3
Temperature Output
15.4
DS40001440E-page 143
PIC16(L)F1825/9
16.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 16-1:
VREF-
ADNREF = 0
VDD
VSS
ADPREF = 00
ADPREF = 11
VREF+
AN0
00000
AN1
00001
AN2
00010
AN3
00011
AN4
00100
AN5
00101
AN6
00110
AN7
00111
AN8(2)
01000
(2)
01001
AN10(2)
01010
AN11(2)
01011
AN9
ADPREF = 10
ADC
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
16
ADON
Temp Indicator
11101
DAC_output
11110
FVR Buffer1
11111
VSS
ADRESH
ADRESL
CHS<4:0>
Note 1:
2:
DS40001440E-page 144
PIC16(L)F1825/9
16.1
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
16.1.1
PORT CONFIGURATION
16.1.2
CHANNEL SELECTION
16.1.3
VREF+ pin
VDD
FVR 2.048V
FVR 4.096V (Not available on LF devices)
16.1.4
CONVERSION CLOCK
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
DS40001440E-page 145
PIC16(L)F1825/9
TABLE 16-1:
ADC
Clock Source
ADCS<2:0>
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
62.5ns(2)
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
Fosc/4
100
125 ns
(2)
(2)
(2)
(2)
Fosc/8
001
0.5 s(2)
400 ns(2)
0.5 s(2)
Fosc/16
101
800 ns
800 ns
010
1.0 s
Fosc/64
110
FRC
x11
Fosc/32
Legend:
Note 1:
2:
3:
4:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
1.0 s
2.0 s
4.0 s
16.0 s(3)
1.6 s
2.0 s
4.0 s
2.0 s
3.2 s
4.0 s
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
200 ns
250 ns
500 ns
8.0 s
(3)
8.0 s
16.0 s
(3)
1.0-6.0 s(1,4)
(3)
1.0-6.0 s(1,4)
32.0 s(3)
64.0 s(3)
1.0-6.0 s(1,4)
FIGURE 16-2:
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b8
b3
b9
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS40001440E-page 146
PIC16(L)F1825/9
16.1.5
INTERRUPTS
16.1.6
RESULT FORMATTING
FIGURE 16-3:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
bit 0
Unimplemented: Read as 0
MSB
(ADFM = 1)
bit 7
Unimplemented: Read as 0
LSB
bit 0
bit 7
bit 0
10-bit A/D Result
DS40001440E-page 147
PIC16(L)F1825/9
16.2
16.2.1
ADC Operation
STARTING A CONVERSION
16.2.2
COMPLETION OF A CONVERSION
16.2.3
TERMINATING A CONVERSION
DS40001440E-page 148
16.2.4
16.2.5
TABLE 16-2:
Device
PIC16(L)F1825/9
CCP4
PIC16(L)F1825/9
16.2.6
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 16-1:
A/D CONVERSION
DS40001440E-page 149
PIC16(L)F1825/9
16.2.7
REGISTER 16-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-2
bit 1
bit 0
Note 1:
2:
3:
4:
PIC16(L)F1829 only.
See Section 17.0 Digital-to-Analog Converter (DAC) Modulefor more information.
See Section 14.0 Fixed Voltage Reference (FVR) for more information.
See Section 15.0 Temperature Indicator Module for more information.
DS40001440E-page 150
PIC16(L)F1825/9
REGISTER 16-2:
R/W-0/0
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
R/W-0/0
ADNREF
R/W-0/0
R/W-0/0
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3
Unimplemented: Read as 0
bit 2
bit 1-0
Note 1:
When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 30.0 Electrical Specifications for details.
DS40001440E-page 151
PIC16(L)F1825/9
REGISTER 16-3:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 16-4:
R/W-x/u
R/W-x/u
ADRES<1:0>
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
DS40001440E-page 152
PIC16(L)F1825/9
REGISTER 16-5:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 16-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001440E-page 153
PIC16(L)F1825/9
16.3
EQUATION 16-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
2
1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1
2
1
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 12.5pF 1k + 7k + 10k ln(0.0004885)
= 1.72 s
Therefore:
T A CQ = 2 s + 1.72 s + 50C- 25C 0.05 s/C
= 4.97s
Note 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001440E-page 154
PIC16(L)F1825/9
FIGURE 16-4:
Analog
Input
pin
Rs
VT 0.6V
CPIN
5 pF
VA
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT 0.6V
CHOLD = 12.5 pF
VSS/VREF-
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
Legend: CHOLD
CPIN
RSS
= Sampling Switch
VT
= Threshold Voltage
Note 1:
FIGURE 16-5:
5 6 7 8 9 10 11
Sampling Switch
(k)
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
VREF-
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
VREF+
DS40001440E-page 155
PIC16(L)F1825/9
TABLE 16-3:
Name
ADCON0
ADCON1
ADFM
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ADNREF
CHS<4:0>
ADCS<2:0>
Bit 1
Bit 0
GO/DONE
ADON
ADPREF<1:0
Register on
Page
150
151
ADRESH
152, 153
ADRESL
152, 153
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
123
ANSELB(1)
ANSB5
ANSB4
129
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
134
ANSELC
CCP4CON
INLVLA
P4M<1:0>
INLVLB(1)
INLVLC
INTCON
DC4B<1:0>
INLVLA5
CCP4M<3:0>
INLVLA4
INLVLA3
INLVLA2
224
INLVLA1
INLVLA0
124
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISA
TRISB(1)
TRISB7
TRISB6
TRISB5
TRISB4
128
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DACCON0
DACEN
DACLPS
DACOE
DACPSS<1:0>
DACCON1
TRISC
Legend:
Note
1:
DACR<4:0>
ADFVR<1:0>
DACNSS
142
160
160
x = unknown, u = unchanged, = unimplemented read as 0, q = value depends on condition. Shaded cells are not used for ADC
module.
PIC16(L)F1829 only.
DS40001440E-page 156
PIC16(L)F1825/9
17.0
DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
17.1
EQUATION 17-1:
IF DACEN = 1
DACR 4:0
VOUT = VSOURCE+ VSOURCE- ----------------------------+ VSOURCE5
2
IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111
V OUT = V SOURCE +
IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000
V OUT = V SOURCE
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
17.2
17.3
DS40001440E-page 157
PIC16(L)F1825/9
FIGURE 17-1:
VSOURCE+
VDD
VREF+
R
R
2
R
DACEN
DACLPS
R
R
32
Steps
R
32-to-1 MUX
DACPSS<1:0>
DACR<4:0>
DAC_Output
DACOUT
DACOE
DACNSS
VREF-
VSOURCE-
VSS
FIGURE 17-2:
DAC
Module
R
Voltage
Reference
Output
Impedance
DS40001440E-page 158
DACOUT
PIC16(L)F1825/9
17.4
17.4.1
FIGURE 17-3:
17.4.2
DACR<4:0> = 11111
R
DACEN = 0
DACLPS = 1
R
DAC Voltage Ladder
(see Figure 17-1)
DACEN = 0
DACLPS = 0
R
VSRC-
17.5
DACR<4:0> = 00000
VSRC-
17.6
Effects of a Reset
DS40001440E-page 159
PIC16(L)F1825/9
17.7
REGISTER 17-1:
R/W-0/0
R/W-0/0
R/W-0/0
U-0
DACEN
DACLPS
DACOE
R/W-0/0
R/W-0/0
U-0
R/W-0/0
DACNSS
DACPSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-2
bit 1
Unimplemented: Read as 0
bit 0
REGISTER 17-2:
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DACR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
Note 1:
The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
DS40001440E-page 160
PIC16(L)F1825/9
TABLE 17-1:
Name
Bit 6
Bit 5
Bit 4
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DACCON0
DACEN
DACLPS
DACOE
DACPSS<1:0>
DACCON1
Legend:
Bit 3
Bit 2
DACR<4:0>
Bit 1
Bit 0
ADFVR<1:0>
DACNSS
Register
on page
142
160
160
DS40001440E-page 161
PIC16(L)F1825/9
18.0
SR LATCH
18.1
18.2
Latch Output
18.3
Effects of a Reset
Latch Operation
DS40001440E-page 162
PIC16(L)F1825/9
FIGURE 18-1:
SRPS
Pulse
Gen(2)
SRLEN
SRQEN
SRI
S
SRSPE
SRCLK
Q
SRQ
SRSCKE
sync_C2OUT(3, 4)
SRSC2E(4)
sync_C1OUT(3)
SRSC1E
SRPR
SR
Latch(1)
Pulse
Gen(2)
SRI
R
SRRPE
SRCLK
Q
SRNQ
SRRCKE
sync_C2OUT(3, 4)
SRRC2E(4)
SRLEN
SRNQEN
sync_C1OUT(3)
SRRC1E
Note 1:
2:
3:
4:
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
Pulse generator causes a 1 Q-state pulse width.
Name denotes the connection point at the comparator output.
PIC16(L)F1829 only.
DS40001440E-page 163
PIC16(L)F1825/9
TABLE 18-1:
SRCLK
Divider
FOSC = 32 MHz
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 4 MHz
FOSC = 1 MHz
111
512
110
256
62.5 kHz
39.0 kHz
31.3 kHz
7.81 kHz
1.95 kHz
125 kHz
78.1 kHz
62.5 kHz
15.6 kHz
3.90 kHz
101
100
128
250 kHz
156 kHz
125 kHz
31.25 kHz
7.81 kHz
64
500 kHz
313 kHz
250 kHz
62.5 kHz
15.6 kHz
011
32
1 MHz
625 kHz
500 kHz
125 kHz
31.3 kHz
010
16
2 MHz
1.25 MHz
1 MHz
250 kHz
62.5 kHz
001
4 MHz
2.5 MHz
2 MHz
500 kHz
125 kHz
000
8 MHz
5 MHz
4 MHz
1 MHz
250 kHz
REGISTER 18-1:
R/W-0/0
R/W-0/0
SRLEN
R/W-0/0
R/W-0/0
SRCLK<2:0>
R/W-0/0
R/W-0/0
R/S-0/0
R/S-0/0
SRQEN
SRNQEN
SRPS
SRPR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS40001440E-page 164
PIC16(L)F1825/9
REGISTER 18-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SRSPE
SRSCKE
SRSC2E(1)
SRSC1E
SRRPE
SRRCKE
SRRC2E(1)
SRRC1E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PIC16(L)F1829 only.
DS40001440E-page 165
PIC16(L)F1825/9
TABLE 18-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
123
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INLVLC
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
SRQEN
SRNQEN
SRPS
SRPR
164
165
SRCON0
SRLEN
SRCON1
SRSPE
SRSCKE
SRSC2E(1)
SRSC1E
SRRPE
SRRCKE
SRRC2E(1)
SRRC1E
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
TRISA
TRISC
Legend:
Note 1:
TRISC7
(1)
SRCLK<2:0>
TRISC6
(1)
DS40001440E-page 166
PIC16(L)F1825/9
19.0
COMPARATOR MODULE
FIGURE 19-1:
19.1
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Comparator Overview
FIGURE 19-2:
Note:
CxNCH<1:0>
CxON(1)
CxINTP
Interrupt
det
C12IN0-
C12IN1-
1
MUX(2)
2
C12IN2C12IN3-
Set CxIF
det
CXPOL
CxVN
Cx(3)
CxVP
CXIN+
DAC_Output
FVR Buffer2
To Data Bus
EN
Q1
CxHYS
CxSP
async_CxOUT
CXSYNC
CxON(1)
VSS
CXOUT
MCXOUT
0
1
MUX(2)
2
CxINTN
Interrupt
CXPCH<1:0>
CXOE
To PWM
TRIS bit
CXOUT
2
D
(from Timer1)
T1CLK
Note
1:
2:
3:
sync_CxOUT
To Timer1 or
SR Latch
When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a 0 at the output.
When CxON = 0, all multiplexer inputs are disconnected.
Output of comparator can be frozen during debugging.
DS40001440E-page 167
PIC16(L)F1825/9
19.2
Comparator Control
Enable
Output selection
Output polarity
Speed/Power selection
Hysteresis enable
Output synchronization
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
19.2.1
COMPARATOR OUTPUT
SELECTION
TABLE 19-1:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
19.2.4
COMPARATOR ENABLE
19.2.2
19.2.3
COMPARATOR SPEED/POWER
SELECTION
19.3
Comparator Hysteresis
DS40001440E-page 168
PIC16(L)F1825/9
19.4
19.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
19.6
19.5
Comparator Interrupt
19.7
19.8
DS40001440E-page 169
PIC16(L)F1825/9
19.9
FIGURE 19-3:
Rs < 10K
Analog
Input
pin
VT 0.6V
RIC
To Comparator
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
= Interconnect Resistance
RIC
= Source Impedance
RS
= Analog Voltage
VA
= Threshold Voltage
VT
Note 1:
DS40001440E-page 170
PIC16(L)F1825/9
REGISTER 19-1:
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
U-0
R/W-1/1
R/W-0/0
R/W-0/0
CxON
CxOUT
CxOE
CxPOL
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS40001440E-page 171
PIC16(L)F1825/9
REGISTER 19-2:
R/W-0/0
R/W-0/0
CxINTP
CxINTN
R/W-0/0
R/W-0/0
CxPCH<1:0>
U-0
U-0
R/W-0/0
R/W-0/0
CxNCH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
REGISTER 19-3:
U-0
U-0
U-0
U-0
U-0
U-0
R-0/0
R-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
DS40001440E-page 172
PIC16(L)F1825/9
TABLE 19-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1HYS
C1SYNC
171
Name
CM1CON1
C1NTP
C1INTN
C1PCH1
C1PCH0
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
CM2CON1
C2NTP
C2INTN
DACCON0
DACEN
DACLPS
DACOE
DACPSS<1:0>
DACCON1
FVREN
FVRRDY
TSEN
CMOUT
FVRCON
C2PCH<1:0>
C1NCH<1:0>
C2HYS
C2SYNC
C2NCH<1:0>
MC2OUT
MC1OUT
DACNSS
DACR<4:0>
TSRNG
CDAFVR<1:0>
172
171
172
172
160
160
ADFVR<1:0>
142
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INLVLC
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
89
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
133
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
133
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
PORTC
Legend:
Note 1:
Unimplemented location, read as 0. Shaded cells are unused by the comparator module.
PIC16(L)F1829 only.
DS40001440E-page 173
PIC16(L)F1825/9
20.0
20.1.2
TIMER0 MODULE
20.1
Timer0 Operation
20.1.1
FIGURE 20-1:
FOSC/4
Data Bus
0
T0CKI
1
0
From CPSCLK
Sync
2 TCY
TMR0
0
1 TMR0SE
TMR0CS
8-bit
Prescaler
PSA
T0XCS
PS<2:0>
DS40001440E-page 174
PIC16(L)F1825/9
20.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
20.1.4
TIMER0 INTERRUPT
20.1.5
20.1.6
DS40001440E-page 175
PIC16(L)F1825/9
20.2
REGISTER 20-1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 20-1:
Name
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CPSOUT
T0xCS
315
CPSCON0
CPSON
CPSRM
CPSRNG<1:0>
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
TRISA5
TRISA4
TRISA3
OPTION_REG
TMR0
TRISA
Legend:
ADFVR<1:0>
PS<2:0>
176
142
174*
TRISA2
TRISA1
TRISA0
122
Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module.
* Page provides register information.
DS40001440E-page 176
PIC16(L)F1825/9
21.0
FIGURE 21-1:
T1GSS<1:0>
T1G
T1GSPM
00
From Timer0
Overflow
01
sync_C1OUT
10
T1G_IN
T1GVAL
0
Single Pulse
D
sync_C2OUT
11
CK Q
R
TMR1ON
T1GPOL
T1GTM
Acq. Control
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
TMR1GE
TMR1ON
To Comparator Module
TMR1(2)
TMR1H
EN
TMR1L
T1CLK
Synchronized
clock input
1
TMR1CS<1:0>
T1OSO
OUT
T1OSC
T1OSI
Cap. Sensing
Oscillator
T1SYNC
11
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
To LCD and Clock Switching Modules
DS40001440E-page 177
PIC16(L)F1825/9
21.1
Timer1 Operation
21.2
21.2.1
TABLE 21-1:
TIMER1 ENABLE
SELECTIONS
Timer1
Operation
TMR1ON
TMR1GE
Off
21.2.2
Off
Always On
Count Enabled
TABLE 21-2:
TMR1CS1
TMR1CS0
T1OSCEN
Clock Source
DS40001440E-page 178
PIC16(L)F1825/9
21.3
Timer1 Prescaler
21.4
Timer1 Oscillator
21.5.1
21.6
Note:
21.5
Timer1 Operation in
Asynchronous Counter Mode
Timer1 Gate
21.6.1
TABLE 21-3:
T1CLK
T1GPOL
T1G
Timer1 Operation
Counts
Holds Count
Holds Count
Counts
DS40001440E-page 179
PIC16(L)F1825/9
21.6.2
TABLE 21-4:
T1GSS
00
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
21.6.2.1
21.6.2.2
21.6.2.3
21.6.2.4
21.6.3
21.6.4
21.6.5
21.6.6
DS40001440E-page 180
PIC16(L)F1825/9
21.7
Timer1 Interrupt
Note:
21.8
21.9
Section 24.0
FIGURE 21-2:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
DS40001440E-page 181
PIC16(L)F1825/9
FIGURE 21-3:
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
FIGURE 21-4:
N+1
N+2
N+3
N+4
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
DS40001440E-page 182
N+4
N+8
PIC16(L)F1825/9
FIGURE 21-5:
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
Cleared by software
N+1
N+2
Set by hardware on
falling edge of T1GVAL
Cleared by
software
DS40001440E-page 183
PIC16(L)F1825/9
FIGURE 21-6:
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
DS40001440E-page 184
Cleared by software
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
N+4
Cleared by
software
PIC16(L)F1825/9
21.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 21-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 21-1:
R/W-0/u
R/W-0/u
R/W-0/u
TMR1CS<1:0>
R/W-0/u
T1CKPS<1:0>
R/W-0/u
R/W-0/u
U-0
R/W-0/u
T1OSCEN
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
bit 2
TMR1CS<1:0> = 0X:
This bit is ignored.
bit 1
Unimplemented: Read as 0
bit 0
DS40001440E-page 185
PIC16(L)F1825/9
21.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 21-2, is used to control Timer1 Gate.
REGISTER 21-2:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
R/W-0/u
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
DS40001440E-page 186
PIC16(L)F1825/9
TABLE 21-5:
Name
ANSELA
PIE1
PIR1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA2
ANSA1
ANSA0
DC1B<1:0>
P2M<1:0>
CCP2CON
INTCON
Bit 5
P1M<1:0>
CCP1CON
INLVLA
Bit 6
CCP1M<3:0>
DC2B<1:0>
INLVLA5
INLVLA4
INLVLA2
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Legend:
124
ADIE
TMR1L
T1GCON
INLVLA0
GIE
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON
224
INLVLA1
TMR1GIE
TMR1H
TRISA
123
224
CCP2M<3:0>
INLVLA3
Register on
Page
TMR1CS<1:0>
TMR1GE
T1GPOL
TRISA5
TRISA4
T1CKPS<1:0>
T1GTM
T1GSPM
92
181*
181*
TRISA3
TRISA2
TRISA1
TRISA0
T1OSCEN
T1SYNC
TMR1ON
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
122
185
186
Unimplemented location, read as 0. Shaded cells are not used by the Timer1 module.
* Page provides register information.
DS40001440E-page 187
PIC16(L)F1825/9
22.0
TIMER2/4/6 MODULES
FIGURE 22-1:
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
2
TMRx
Comparator
Sets Flag
bit TMRxIF
Reset
EQ
Postscaler
1:1 to 1:16
TxCKPS<1:0>
PRx
4
TxOUTPS<3:0>
DS40001440E-page 188
PIC16(L)F1825/9
22.1
Timer2/4/6 Operation
22.3
Timer2/4/6 Output
22.4
22.2
Timer2/4/6 Interrupt
DS40001440E-page 189
PIC16(L)F1825/9
22.5
REGISTER 22-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TxOUTPS<3:0>
R/W-0/0
R/W-0/0
TMRxON
bit 7
R/W-0/0
TxCKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
DS40001440E-page 190
PIC16(L)F1825/9
TABLE 22-1:
Name
CCP2CON
Bit 6
P2M<1:0>
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
DC2B<1:0>
CCP2M<3:0>
224
CCP4CON
DC4B<1:0>
CCP4M<3:0>
224
CCP6CON
DC6B<1:0>
CCP6M<3:0>
224
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIE3
CCP4IE
CCP3IE
TMR6IE
TMR4IE
90
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
CCP4IF
CCP3IF
TMR6IF
TMR4IF
INTCON
PIR3
94
PR2
188*
PR4
188*
PR6
188*
T2CON
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
190
T4CON
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
190
T6CON
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
190
TMR2
188*
TMR4
188*
TMR6
188*
Legend: Unimplemented location, read as 0. Shaded cells are not used for Timer2/4/6 module.
* Page provides register information.
DS40001440E-page 191
PIC16(L)F1825/9
23.0
FIGURE 23-1:
Carrier Synchronization
Carrier Source Polarity Select
Carrier Source Pin Disable
Programmable Modulator Data
Modulator Source Pin Disable
Modulated Output Polarity Select
Slew Rate Control
MDCH<3:0>
VSS
MDCIN1
MDCIN2
CLKR
CCP1
CCP2
CCP3
CCP4
Reserved
No Channel
Selected
MDEN
0000
0001
0010
0011
0100
0101 CARH
0110
0111
1000
*
*
1111
EN
Data Signal
Modulator
MDCHPOL
D
SYNC
MDMS<3:0>
MDBIT
MDMIN
CCP1
CCP2
CCP3
CCP4
Comparator C1
Comparator C2
MSSP1 SDO1
MSSP2 SDO2
EUSART
Reserved
No Channel
Selected
Q
0000
0001
0010
0011
0100
0101
0110 MOD
0111
1000
1001
1010
0011
*
*
1111
0
MDCHSYNC
MDOUT
MDOPOL
MDOE
D
SYNC
MDCL<3:0>
VSS
MDCIN1
MDCIN2
CLKR
CCP1
CCP2
CCP3
CCP4
Reserved
No Channel
Selected
DS40001440E-page 192
Q
0000
0001
0010
0011
0100
0101 CARL
0110
0111
1000
*
*
1111
0
MDCLSYNC
MDCLPOL
PIC16(L)F1825/9
23.1
DSM Operation
23.2
CCP1 Signal
CCP2 Signal
CCP3 Signal
CCP4 Signal
MSSP1 SDO1 Signal (SPI Mode Only)
MSSP2 SDO2 Signal (SPI Mode Only)
Comparator C1 Signal
Comparator C2 Signal
EUSART TX Signal
External Signal on MDMIN pin
MDBIT bit in the MDCON register
23.3
CCP1 Signal
CCP2 Signal
CCP3 Signal
CCP4 Signal
Reference Clock Module Signal
External Signal on MDCIN1 pin
External Signal on MDCIN2 pin
VSS
23.4
Carrier Synchronization
DS40001440E-page 193
PIC16(L)F1825/9
FIGURE 23-2:
EXAMPLE 23-1:
FIGURE 23-3:
CARH
CARL
CARH
CARL
DS40001440E-page 194
CARH
both
CARL
CARH
both
CARL
PIC16(L)F1825/9
FIGURE 23-4:
FIGURE 23-5:
CARH
CARL
CARH
CARL
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 1
Active Carrier
State
CARH
CARL
CARH
CARL
DS40001440E-page 195
PIC16(L)F1825/9
23.5
23.6
23.7
23.8
23.9
DS40001440E-page 196
PIC16(L)F1825/9
REGISTER 23-1:
R/W-0/0
R/W-0/0
R/W-1/1
R/W-0/0
R-0/0
U-0
U-0
R/W-0/0
MDEN
MDOE
MDSLR
MDOPOL
MDOUT
MDBIT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
Note 1:
2:
The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
MDBIT must be selected as the modulation source in the MDSRC register for this operation.
DS40001440E-page 197
PIC16(L)F1825/9
REGISTER 23-2:
R/W-x/u
U-0
U-0
U-0
MDMSODIS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDMS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3-0
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
DS40001440E-page 198
PIC16(L)F1825/9
REGISTER 23-3:
R/W-x/u
R/W-x/u
R/W-x/u
U-0
MDCHODIS
MDCHPOL
MDCHSYNC
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
DS40001440E-page 199
PIC16(L)F1825/9
REGISTER 23-4:
R/W-x/u
R/W-x/u
R/W-x/u
U-0
MDCLODIS
MDCLPOL
MDCLSYNC
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDCL<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
TABLE 23-1:
Name
Bit 5
Bit 4
MDCARH
MDCHODIS
MDCHPOL
MDCHSYNC
MDCH<3:0>
199
MDCARL
MDCLODIS
MDCLPOL
MDCLSYNC
MDCL<3:0>
200
MDCON
MDEN
MDOE
MDSLR
MDOPOL
MDSRC
MDMSODIS
Legend:
Unimplemented, read as 0. Shaded cells are not used in the Data Signal Modulator mode.
DS40001440E-page 200
Bit 3
MDOUT
Bit 2
Bit 1
MDMS<3:0>
Bit 0
Register
on Page
Bit 7
MDBIT
197
198
PIC16(L)F1825/9
24.0
CAPTURE/COMPARE/PWM
MODULES
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to ECCP1,
ECCP2, CCP3 and CCP4. Register
names, module signals, I/O pins, and bit
names may use the generic designator x
to indicate the use of a numeral to
distinguish a particular module, when
required.
TABLE 24-1:
PWM RESOURCES
Device Name
PIC16(L)F1825/9
ECCP1
ECCP2
CCP3
CCP4
Enhanced PWM
Full-Bridge
Enhanced PWM
Half-Bridge
Standard PWM
Standard PWM
DS40001440E-page 201
PIC16(L)F1825/9
24.1
24.1.2
Capture Mode
24.1.1
FIGURE 24-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCPxIF
(PIRx register)
CCPx
pin
CCPRxH
24.1.3
Note:
24.1.4
TMR1H
CCP PRESCALER
EXAMPLE 24-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCPxCON
CLRF
MOVLW
CCPRxL
Capture
Enable
MOVWF
and
Edge Detect
TMR1L
CCPxM<3:0>
System Clock (FOSC)
DS40001440E-page 202
PIC16(L)F1825/9
24.1.5
24.1.6
TABLE 24-2:
Name
APFCON1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDO2SEL(2)
SS2SEL(2)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
CCP1CON
P1M<1:0>(1)
CCP2CON
P2M<1:0>(1)
DC1B<1:0>
Register on
Page
119
CCP1M<3:0>
224
DC2B<1:0>
CCP2M<3:0>
224
CCP3CON
DC3B<1:0>
CCP3M<3:0>
224
CCP4CON
DC4B<1:0>
CCP4M<3:0>
CCPRxL
CCPRxH
CMxCON0
CxON
CxOUT
CMxCON1
CxINTP
CxINTN
INLVLA
(2)
INLVLC
INLVLC7
(2)
CxPOL
CxPCH<1:0>
202*
CxSP
CxHYS
CxSYNC
CxNCH<1:0>
171
172
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
135
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
89
INTCON
INLVLC6
CxOE
224
202*
PIE3
CCP4IE
CCP3IE
TMR6IE
TMR4IE
90
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
PIR3
CCP4IF
CCP3IF
TMR6IF
TMR4IF
94
T1OSCEN
T1SYNC
TMR1ON
T1GGO/DONE
T1GVAL
T1CON
TMR1CS<1:0>
T1GCON
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1GSS<1:0>
185
186
181*
181*
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISC
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
Legend:
Note
1:
2:
Unimplemented location, read as 0. Shaded cells are not used by Capture mode.
DS40001440E-page 203
PIC16(L)F1825/9
24.2
24.2.2
Compare Mode
FIGURE 24-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPxM<3:0>
Mode Select
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPRxH CCPRxL
CCPx
Pin
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
24.2.1
DS40001440E-page 204
24.2.3
24.2.4
TABLE 24-3:
Device
PIC16(L)F1825/9
CCP4
PIC16(L)F1825/9
24.2.5
24.2.6
TABLE 24-4:
Name
APFCON1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDO2SEL(2)
SS2SEL(2)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
Register on
Page
119
CCP1CON
(1)
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
224
CCP2CON
P2M<1:0>(1)
DC2B<1:0>
CCP2M<3:0>
224
CCP3CON
DC3B<1:0>
CCP3M<3:0>
224
CCP4CON
DC4B<1:0>
CCP4M<3:0>
CCPRxL
CCPRxH
224
202*
202*
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INLVLC
INLVLC7(2)
INLVLC6(2)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
89
PIE3
CCP4IE
CCP3IE
TMR6IE
TMR4IE
90
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
PIR3
CCP4IF
CCP3IF
TMR6IF
TMR4IF
94
T1OSCEN
T1SYNC
TMR1ON
185
T1GGO/DONE
T1GVAL
T1CON
TMR1CS<1:0>
T1GCON
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1GSS<1:0>
186
181*
181*
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISC
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
Legend:
Unimplemented location, read as 0. Shaded cells are not used by Compare mode.
*
Note
1:
2:
3:
DS40001440E-page 205
PIC16(L)F1825/9
24.3
PWM Overview
FIGURE 24-3:
Period
Pulse Width
24.3.1
TMRx = 0
FIGURE 24-4:
CCPRxH(2) (Slave)
CCPx
R
Comparator
TMRx
(1)
S
TRIS
Comparator
TMRx = PRx
TMRx = CCPRxH:CCPxCON<5:4>
PRx
Note 1:
2:
Clear Timer,
toggle CCPx pin and
latch duty cycle
PRx registers
TxCON registers
CCPRxL registers
CCPxCON registers
DS40001440E-page 206
PIC16(L)F1825/9
24.3.2
4.
5.
6.
24.3.3
24.3.4
PWM PERIOD
EQUATION 24-1:
PWM PERIOD
24.3.5
EQUATION 24-2:
PULSE WIDTH
EQUATION 24-3:
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------4 PRx + 1
TOSC = 1/FOSC
DS40001440E-page 207
PIC16(L)F1825/9
24.3.6
PWM RESOLUTION
EQUATION 24-4:
TABLE 24-5:
Note:
1.95 kHz
7.81 kHz
31.25 kHz
125 kHz
250 kHz
333.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
TABLE 24-7:
log 4 PRx + 1
Resolution = ------------------------------------------ bits
log 2
PWM Frequency
TABLE 24-6:
PWM RESOLUTION
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
DS40001440E-page 208
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
PIC16(L)F1825/9
24.3.7
24.3.10
24.3.8
24.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 24-8:
Name
APFCON1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDO2SEL(2)
SS2SEL(2)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
CCP1CON
P1M<1:0>(1)
CCP2CON
P2M<1:0>(1)
DC1B<1:0>
CCP1M<3:0>
Register on
Page
119
224
DC2B<1:0>
CCP2M<3:0>
224
CCP3CON
DC3B<1:0>
CCP3M<3:0>
224
CCP4CON
DC4B<1:0>
CCP4M<3:0>
CCPTMRS
C4TSEL<1:0>
CCPR1L
C3TSEL<1:0>
C2TSEL<1:0>
224
C1TSEL<1:0>
INLVLA
(2)
INLVLC
INLVLC7
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
89
INTCON
INLVLC6
(2)
225
202*
PIE3
CCP4IE
CCP3IE
TMR6IE
TMR4IE
90
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
PIR3
CCP4IF
CCP3IF
TMR6IF
TMR4IF
94
PRx
188*
T2CON
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
190
T4CON
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
190
T6CON
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
190
TMRx
188*
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISC
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
Legend:
Unimplemented location, read as 0. Shaded cells are not used by the PWM.
*
Note
1:
2:
DS40001440E-page 209
PIC16(L)F1825/9
24.4
The PWM outputs are multiplexed with I/O pins and are
designated PxA, PxB, PxC and PxD. The polarity of the
PWM pins is configurable and is selected by setting the
CCPxM bits in the CCPxCON register appropriately.
PRx registers
TxCON registers
CCPRxL registers
CCPxCON registers
CCPxAS registers
PSTRxCON registers
PWMxCON registers
Single PWM
Half-Bridge PWM
Full-Bridge PWM, Forward mode
Full-Bridge PWM, Reverse mode
Single PWM with PWM Steering mode
FIGURE 24-5:
DCxB<1:0>
CCPxM<3:0>
4
PxM<1:0>
2
CCPRxL
CCPx/PxA
CCPx/PxA
TRISx
CCPRxH (Slave)
PxB
Comparator
Output
Controller
PxB
TRISx
PxC
TMRx
(1)
Comparator
PRx
Note
1:
PxC
TRISx
S
PxD
Clear Timer,
toggle PWM pin and
latch duty cycle
PxD
TRISx
PWMxCON
The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time
base.
DS40001440E-page 210
PIC16(L)F1825/9
TABLE 24-9:
ECCP Mode
PxM<1:0>
CCPx/PxA
PxB
PxC
PxD
Single
00
Yes(1)
Yes(1)
Yes(1)
Yes(1)
Half-Bridge
10
Yes
Yes
No
No
Full-Bridge, Forward
01
Yes
Yes
Yes
Yes
Full-Bridge, Reverse
11
Yes
Yes
Yes
Yes
Note 1:
FIGURE 24-6:
PxM<1:0>
Signal
PRX+1
Pulse
Width
Period
00
(Single Output)
PxA Modulated
Delay
Delay
PxA Modulated
10
(Half-Bridge)
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
DS40001440E-page 211
PIC16(L)F1825/9
FIGURE 24-7:
PxM<1:0>
Signal
PRx+1
Pulse
Width
Period
00
(Single Output)
PxA Modulated
PxA Modulated
10
(Half-Bridge)
Delay
Delay
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
DS40001440E-page 212
PIC16(L)F1825/9
24.4.1
HALF-BRIDGE MODE
Since the PxA and PxB outputs are multiplexed with the
PORT data latches, the associated TRIS bits must be
cleared to configure PxA and PxB as outputs.
FIGURE 24-8:
Period
Period
Pulse Width
PxA(2)
td
td
PxB(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
FIGURE 24-9:
PxA
Load
FET
Driver
PxB
FET
Driver
FET
Driver
PxA
FET
Driver
Load
FET
Driver
PxB
DS40001440E-page 213
PIC16(L)F1825/9
24.4.2
FULL-BRIDGE MODE
FIGURE 24-10:
FET
Driver
QC
QA
FET
Driver
PxA
Load
PxB
FET
Driver
PxC
FET
Driver
QD
QB
VPxD
DS40001440E-page 214
PIC16(L)F1825/9
FIGURE 24-11:
Forward Mode
Period
PxA
(2)
Pulse Width
PxB(2)
PxC(2)
PxD(2)
(1)
(1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1)
Note 1:
2:
(1)
DS40001440E-page 215
PIC16(L)F1825/9
24.4.2.1
FIGURE 24-12:
Signal
Period
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1:
2:
The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.
DS40001440E-page 216
PIC16(L)F1825/9
FIGURE 24-13:
t1
Reverse Period
PxA
PxB
PW
PxC
PxD
PW
TON
External Switch C
TOFF
External Switch D
Potential
Shoot-Through Current
Note 1:
T = TOFF TON
2:
3:
DS40001440E-page 217
PIC16(L)F1825/9
24.4.3
FIGURE 24-14:
Timer
Overflow
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
Shutdown
Event Occurs
DS40001440E-page 218
Shutdown
Event Clears
PWM
Resumes
CCPxASE
Cleared by
Firmware
PIC16(L)F1825/9
24.4.4
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PxRSEN bit in the PWMxCON register.
FIGURE 24-15:
Timer
Overflow
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
CCPxASE
Cleared by
Hardware
DS40001440E-page 219
PIC16(L)F1825/9
24.4.5
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 24-16:
Period
Period
Pulse Width
PxA(2)
td
td
PxB(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state
to the active state. See Figure 24-16 for illustration.
The lower seven bits of the associated PWMxCON
register (Register 24-4) sets the delay period in terms
of microcontroller instruction cycles (TCY or 4 TOSC).
FIGURE 24-17:
+
V
-
PxA
Load
FET
Driver
+
V
-
PxB
V-
DS40001440E-page 220
PIC16(L)F1825/9
24.4.6
Note:
FIGURE 24-18:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STRxA
PxA Signal
CCPxM1
PORT Data
PxA pin
STRxB
CCPxM0
PORT Data
STRxC
CCPxM1
PORT Data
PORT Data
PxB pin
TRIS
PxC pin
TRIS
STRxD
CCPxM0
TRIS
PxD pin
1
0
TRIS
Note 1:
2:
DS40001440E-page 221
PIC16(L)F1825/9
24.4.6.1
Steering Synchronization
24.4.7
START-UP CONSIDERATIONS
FIGURE 24-19:
24.4.8
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 24-20:
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
DS40001440E-page 222
PIC16(L)F1825/9
TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM
Name
APFCON1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
SDO2SEL(2)
SS2SEL(2)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
119
CCP1CON
P1M<1:0>(1)
DC1B<1:0>
CCP1M<3:0>
CCP2CON
P2M<1:0>(1)
DC2B<1:0>
CCP2M<3:0>
224
224
CCP3CON
DC3B<1:0>
CCP3M<3:0>
224
CCP4CON
DC4B<1:0>
CCP4M<3:0>
224
CCP1AS
CCP1ASE
CCP1AS<2:0>
PSS1AC<1:0>
PSS1BD<1:0>
226
CCP2AS
CCP2ASE
CCP2AS<2:0>
PSS2AC<1:0>
PSS2BD<1:0>
226
C2TSEL<1:0>
C1TSEL<1:0>
225
CCPTMRS
C4TSEL<1:0>
INLVLA
C3TSEL<1:0>
(1)
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
89
90
INLVLC
INLVLC7
INTCON
INLVLC6
(1)
INLVLA5
PIE3
CCP4IE
CCP3IE
TMR6IE
TMR4IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
PIR3
CCP4IF
CCP3IF
TMR6IF
TMR4IF
94
PRx
188*
PSTR1CON
STR1SYNC
STR1D
STR1C
STR1B
STR1A
228
PSTR2CON
STR2SYNC
STR2D
STR2C
STR2B
STR2A
228
PWM1CON
P1RSEN
P1DC<6:0>
PWM2CON
P2RSEN
P2DC<6:0>
227
227
T2CON
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
190
T4CON
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
190
T6CON
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
TMRx
190
188*
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISC
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
Legend:
Unimplemented location, read as 0. Shaded cells are not used by the PWM.
*
Note
1:
2:
DS40001440E-page 223
PIC16(L)F1825/9
24.5
REGISTER 24-1:
R/W-00
R/W-0/0
R/W-0/0
PxM<1:0>(1)
R/W-0/0
R/W-0/0
DCxB<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-0
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
1010 =
1011 =
Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
Compare mode: Special Event Trigger (ECCPx resets Timer, sets CCPxIF bit, starts A/D conversion
if A/D module is enabled)(1)
DS40001440E-page 224
PIC16(L)F1825/9
REGISTER 24-2:
R/W-0/0
R/W-0/0
R/W-0/0
C4TSEL<1:0>
R/W-0/0
R/W-0/0
C3TSEL<1:0>
R/W-0/0
R/W-0/0
C2TSEL<1:0>
bit 7
R/W-0/0
C1TSEL<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
DS40001440E-page 225
PIC16(L)F1825/9
REGISTER 24-3:
R/W-0/0
R/W-0/0
CCPxASE
R/W-0/0
R/W-0/0
CCPxAS<2:0>
R/W-0/0
R/W-0/0
R/W-0/0
PSSxAC<1:0>
R/W-0/0
PSSxBD<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3-2
bit 1-0
Note 1:
DS40001440E-page 226
PIC16(L)F1825/9
REGISTER 24-4:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxRSEN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxDC<6:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-0
Note 1:
Bit resets to 0 with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
DS40001440E-page 227
PIC16(L)F1825/9
PSTRxCON: PWM STEERING CONTROL REGISTER(1)
REGISTER 24-5:
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
STRxSYNC
STRxD
STRxC
STRxB
STRxA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.
DS40001440E-page 228
PIC16(L)F1825/9
25.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP1 AND
MSSP2) MODULE
25.1
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-chain connection of slave devices
FIGURE 25-1:
Write
SSPxBUF Reg
SDIx
SSPxSR Reg
SDOx
bit 0
SSx
SSx Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
SCKx
Edge
Select
TRIS bit
( TMR22Output )
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPxADD)
DS40001440E-page 229
PIC16(L)F1825/9
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited Multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDAx hold times
[SSPM 3:0]
Write
SSPxBUF
SDAx
Baud Rate
Generator
(SSPxADD)
Shift
Clock
SDAx in
SCLx
SCLx in
Bus Collision
DS40001440E-page 230
LSb
Clock Cntl
SSPxSR
MSb
FIGURE 25-2:
PIC16(L)F1825/9
FIGURE 25-3:
Write
SSPxBUF Reg
SCLx
Shift
Clock
SSPxSR Reg
SDAx
MSb
LSb
SSPMSK Reg
Match Detect
Addr Match
SSPxADD Reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT Reg)
DS40001440E-page 231
PIC16(L)F1825/9
25.2
its SDOx pin) and the slave device is reading this bit
and saving it as the LSb of its shift register, that the
slave device is also sending out the MSb from its shift
register (on its SDOx pin) and the master device is
reading this bit and saving it as the LSb of its shift
register.
After eight bits have been shifted out, the master and
slave have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
Master sends useful data and slave sends dummy
data.
Master sends useful data and slave sends useful
data.
Master sends dummy data and slave sends useful
data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it
deselects the slave.
Every slave device connected to the bus that has not
been selected through its slave select line must
disregard the clock and transmission signals and must
not transmit out any data of its own.
DS40001440E-page 232
PIC16(L)F1825/9
FIGURE 25-4:
SPI Master
SCKx
SCKx
SDOx
SDIx
SDIx
SDOx
General I/O
General I/O
SSx
General I/O
SCKx
SDIx
SDOx
SPI Slave
#1
SPI Slave
#2
SSx
SCKx
SDIx
SDOx
SPI Slave
#3
SSx
25.2.1
25.2.2
DS40001440E-page 233
PIC16(L)F1825/9
The MSSPx consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPxSR until the received data is ready. Once the
eight bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
Detect bit, BF of the SSPxSTAT register, and the
interrupt flag bit, SSPxIF, are set. This double-buffering
of the received data (SSPxBUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPxCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSPxBUF register to complete successfully.
FIGURE 25-5:
SDOx
SDIx
Shift Register
(SSPxSR)
MSb
LSb
SCKx
General I/O
Processor 1
DS40001440E-page 234
SDOx
Serial Clock
Slave Select
(optional)
Shift Register
(SSPxSR)
MSb
LSb
SCKx
SSx
Processor 2
PIC16(L)F1825/9
25.2.3
FIGURE 25-6:
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
SDOx
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDOx
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
DS40001440E-page 235
PIC16(L)F1825/9
25.2.4
Daisy-Chain Configuration
25.2.5
SLAVE SELECT
SYNCHRONIZATION
DS40001440E-page 236
PIC16(L)F1825/9
FIGURE 25-7:
SPI Master
SCK
SCK
SDOx
SDIx
SDIx
SDOx
General I/O
SPI Slave
#1
SSx
SCK
SDIx
SDOx
SPI Slave
#2
SSx
SCK
SDIx
SDOx
SPI Slave
#3
SSx
FIGURE 25-8:
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SSPxBUF to
SSPxSR
SDOx
bit 7
bit 6
bit 7
SDIx
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
DS40001440E-page 237
PIC16(L)F1825/9
FIGURE 25-9:
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDOx
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDIx
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
FIGURE 25-10:
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDOx
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDIx
bit 7
bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
DS40001440E-page 238
PIC16(L)F1825/9
25.2.6
TABLE 25-1:
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
129
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
134
APFCON0
RXDTSEL
SDO1SEL(2)
SS1SEL(2)
T1GSEL
TXCKSEL
118
APFCON1
SDO2SEL(1)
SS2SEL(1)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
119
INLVLA
INLVLA5(1)
INLVLA4(1)
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
Name
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
(1)
INLVLB
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
INLVLC
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1(1)
INLVLC0(1)
135
INTCON
PIE1
PIR1
SSP1BUF
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
233*
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SSP1STAT
SMP
CKE
D/A
R/W
TRISA5(1)
TRISA4(1)
TRISA3
TRISA2
TRISB7
TRISB6
TRISB5
TRISB4
128
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1(1)
TRISC0(1)
133
TRISA
TRISB(1)
TRISC
Legend:
Note
1:
2:
SSPM<3:0>
SDAHT
SBCDE
277
AHEN
DHEN
279
UA
BF
276
TRISA1
TRISA0
122
Unimplemented location, read as 0. Shaded cells are not used by the MSSP1 in SPI mode.
* Page provides register information.
PIC16(L)F1829 only.
PIC16(L)F1825 only.
DS40001440E-page 239
PIC16(L)F1825/9
25.3
VDD
SCLx
DS40001440E-page 240
I2C MASTER/
SLAVE CONNECTION
FIGURE 25-11:
SCLx
VDD
Master
Slave
SDAx
SDAx
PIC16(L)F1825/9
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a
logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCLx line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDAx line, it is called arbitration. Arbitration
ensures that there is only one master device
communicating at any single time.
25.3.1
CLOCK STRETCHING
25.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a
transmission on or about the same time. When this
occurs, the process of arbitration begins. Each
transmitter checks the level of the SDAx data line and
compares it to the level that it expects to find. The first
transmitter to observe that the two levels do not match,
loses arbitration, and must stop transmitting on the
SDAx line.
For example, if one transmitter holds the SDAx line to
a logical one (lets it float) and a second transmitter
holds it to a logical zero (pulls it low), the result is that
the SDAx line will be low. The first transmitter then
observes that the level of the line is different than
expected and concludes that another transmitter is
communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDAx
line. If this transmitter is also a master device, it also
must stop driving the SCLx line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDAx line continues with its
original transmission. It can do so without any
complications, because so far, the transmission
appears exactly as expected with no other transmitter
disturbing the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins
arbitration. When two master devices send messages
to the same slave address, and addresses can
sometimes refer to multiple slaves, the arbitration
process must continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
DS40001440E-page 241
PIC16(L)F1825/9
25.4
25.4.1
BYTE FORMAT
25.4.2
25.4.3
25.4.4
DS40001440E-page 242
TABLE 25-2:
TERM
Transmitter
PIC16(L)F1825/9
25.4.5
START CONDITION
25.4.7
25.4.6
RESTART CONDITION
STOP CONDITION
25.4.8
START/STOP CONDITION
INTERRUPT MASKING
FIGURE 25-12:
SDAx
SCLx
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
FIGURE 25-13:
Stop
Condition
Sr
Change of
Change of
Data Allowed
Restart
Data Allowed
Condition
DS40001440E-page 243
PIC16(L)F1825/9
25.4.9
ACKNOWLEDGE SEQUENCE
25.5
25.5.1
25.5.1.1
25.5.1.2
DS40001440E-page 244
PIC16(L)F1825/9
25.5.1.3
Slave Reception
25.5.1.4
25.5.1.5
DS40001440E-page 245
DS40001440E-page 246
SSPOV
BF
SSPxIF
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D4
D3
D2
D1
SSPxBUF is read
Cleared by software
D5
Receiving Data
D6
First byte
of data is
available
in SSPxBUF
D0 ACK D7
D4
D3
D2
D1
Cleared by software
D5
Receiving Data
D0
ACK = 1
FIGURE 25-14:
SCLx
SDAx
Receiving Address
PIC16(L)F1825/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
CKP
SSPOV
BF
SSPxIF
SCLx
A7
A6
A5
A4
A3
A2
A1
R/W=0 ACK
SEN
2
D6
D5
D4
D3
D2
D1
D0
SSPxBUF is read
Cleared by software
D7
Receive Data
ACK
SEN
3
D5
D4
D3
First byte
of data is
available
in SSPxBUF
D2
D1
Cleared by software
D6
D7
Receive Data
D0
ACK
FIGURE 25-15:
SDAx
Receive Address
PIC16(L)F1825/9
DS40001440E-page 247
DS40001440E-page 248
ACKTIM
CKP
ACKDT
BF
SSPxIF
Receiving Address
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPxIF is set
When AHEN=1:
CKP is cleared by hardware
and SCLx is stretched
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
ACKTIM cleared by
hardware in 9th
rising edge of SCLx
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCLx
SSPxIF is set on
9th falling edge of
SCLx, after ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
Slave software
sets ACKDT to
not ACK
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 25-16:
SCLx
SDAx
PIC16(L)F1825/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
ACKTIM
CKP
ACKDT
BF
SSPxIF
Receiving Address
4
5
6 7
When AHEN = 1;
on the 8th falling edge
of SCLx of an address
byte, CKP is cleared
Received
address is loaded into
SSPxBUF
2 3
A7 A6 A5 A4 A3 A2 A1
ACK
Receive Data
2 3
6 7
When DHEN = 1;
on the 8th falling edge
of SCLx of a received
data byte, CKP is cleared
Received data is
available on SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Receive Data
1
3 4
6 7
Set by software,
release SCLx
Slave sends
not ACK
SSPxBUF can be
read any time before
next byte is loaded
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt after
if not ACK
from Slave
Master sends
Stop condition
FIGURE 25-17:
SCLx
SDAx
R/W = 0
Master releases
SDAx to slave for ACK sequence
PIC16(L)F1825/9
DS40001440E-page 249
PIC16(L)F1825/9
25.5.2
SLAVE TRANSMISSION
25.5.2.2
7-bit Transmission
1.
25.5.2.1
DS40001440E-page 250
D/A
R/W
ACKSTAT
CKP
BF
SSPxIF
Receiving Address
Indicates an address
has been received
R/W = 1 Automatic
ACK
Received address
is read from SSPxBUF
A7 A6 A5 A4 A3 A2 A1
Transmitting Data
Automatic
Set by software
Data to transmit is
loaded into SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
CKP is not
held for not
ACK
BF is automatically
cleared after 8th falling
edge of SCLx
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
FIGURE 25-18:
SCLx
SDAx
Master sends
Stop condition
PIC16(L)F1825/9
DS40001440E-page 251
PIC16(L)F1825/9
25.5.2.3
DS40001440E-page 252
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPxIF
Receiving Address
Slave clears
ACKDT to ACK
address
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSPxBUF
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
A7 A6 A5 A4 A3 A2 A1
3
Cleared by software
Set by software,
releases SCLx
Data to transmit is
loaded into SSPxBUF
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCLx
Automatic
Transmitting Data
Masters ACK
response is copied
to SSPxSTAT
BF is automatically
cleared after 8th falling
edge of SCLx
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Master sends
Stop condition
FIGURE 25-19:
SCLx
SDAx
PIC16(L)F1825/9
DS40001440E-page 253
PIC16(L)F1825/9
25.5.3
3.
4.
5.
6.
7.
8.
25.5.4
9.
DS40001440E-page 254
CKP
UA
BF
SSPxIF
0 A9 A8
Set by hardware
on 9th falling edge
When UA = 1;
SCLx is held low
ACK
If address matches
SSPxADD it is loaded into
SSPxBUF
A7 A6 A5 A4 A3 A2 A1 A0 ACK
9
1
Data is read
from SSPxBUF
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCLx
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
FIGURE 25-20:
SCLx
SDAx
Master sends
Stop condition
PIC16(L)F1825/9
DS40001440E-page 255
DS40001440E-page 256
ACKTIM
CKP
UA
ACKDT
BF
A9
A8
Set by hardware
on 9th falling edge
If when AHEN = 1;
on the 8th falling edge
of SCLx of an address
byte, CKP is cleared
R/W = 0
ACK
UA
A6
A5
A4
A3
A2
A1
Update to SSPxADD is
not allowed until 9th
falling edge of SCLx
SSPxBUF can be
read anytime before
the next received byte
Cleared by software
A7
A0
ACK
UA
D6
D5
D4
D2
D1
Update of SSPxADD,
clears UA and releases
SCLx
D3
Receive Data
Cleared by software
D7
Received data
is read from
SSPxBUF
D6 D5
Receive Data
D0 ACK D7
FIGURE 25-21:
SSPxIF
SCLx
SDAx
PIC16(L)F1825/9
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPxIF
Set by hardware
Indicates an address
has been received
UA indicates SSPxADD
must be updated
SSPxBUF loaded
with received address
SCLx
1
3
7 8
After SSPxADD is
updated, UA is cleared
and SCLx is released
Cleared by software
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
4
7 8
Set by hardware
2 3
When R/W = 1;
CKP is cleared on
9th falling edge of SCLx
Received address is
read from SSPxBUF
Sr
1 1 1 1 0 A9 A8
ACK
Set by software
releases SCLx
Data to transmit is
loaded into SSPxBUF
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 25-22:
SDAx
Master sends
Restart event
PIC16(L)F1825/9
DS40001440E-page 257
PIC16(L)F1825/9
25.5.5
CLOCK STRETCHING
25.5.5.2
25.5.5.1
FIGURE 25-23:
25.5.5.3
Byte NACKing
25.5.6
Any time the CKP bit is cleared, the module will wait
for the SCLx line to go low and then hold it. However,
clearing the CKP bit will not assert the SCLx output
low until the SCLx output is already sampled low.
Therefore, the CKP bit will not assert the SCLx line
until an external I2C master device has already
asserted the SCLx line. The SCLx output will remain
low until the CKP bit is set and all other devices on the
I2C bus have released SCLx. This ensures that a write
to the CKP bit will not violate the minimum high time
requirement for SCLx (see Figure 25-23).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
DX 1
DX
SCLx
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPxCON1
DS40001440E-page 258
PIC16(L)F1825/9
25.5.7
respond.
reception
FIGURE 25-24:
and
call
SDAx
SCLx
S
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
GCEN (SSPxCON2<7>)
SSPxBUF is read
1
25.5.8
DS40001440E-page 259
PIC16(L)F1825/9
25.6
25.6.1
DS40001440E-page 260
PIC16(L)F1825/9
25.6.2
CLOCK ARBITRATION
FIGURE 25-25:
SDAx
DX 1
DX
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
25.6.3
DS40001440E-page 261
PIC16(L)F1825/9
25.6.4
FIGURE 25-26:
SDAx = 1,
SCLx = 1
TBRG
TBRG
SDAx
2nd bit
1st bit
TBRG
SCLx
S
DS40001440E-page 262
TBRG
PIC16(L)F1825/9
25.6.5
FIGURE 25-27:
Write to SSPxCON2
occurs here
SDAx = 1,
SCLx (no change)
SDAx = 1,
SCLx = 1
TBRG
TBRG
TBRG
1st bit
SDAx
Sr
TBRG
Repeated Start
DS40001440E-page 263
PIC16(L)F1825/9
25.6.6
25.6.6.1
BF Status Flag
25.6.6.3
25.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
25.6.6.2
DS40001440E-page 264
R/W
PEN
SEN
BF (SSPxSTAT<0>)
SSPxIF
SCLx
SDAx
A6
A5
A4
A3
A2
A1
Cleared by software
SSPxBUF written
D7
1
SCLx held low
while CPU
responds to SSPxIF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
ACKSTAT in
SSPxCON2 = 1
Cleared by software
ACK
FIGURE 25-28:
SEN = 0
PIC16(L)F1825/9
DS40001440E-page 265
PIC16(L)F1825/9
25.6.7
25.6.7.1
BF Status Flag
25.6.7.2
25.6.7.3
DS40001440E-page 266
25.6.7.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
RCEN
ACKEN
SSPOV
BF
(SSPxSTAT<0>)
SDAx = 0, SCLx = 1
while CPU
responds to SSPxIF
SSPxIF
SCLx
SDAx
A7
4
5
Cleared by software
A6 A5 A4 A3 A2
7
8
ACK
D0
ACK
RCEN cleared
automatically
5
6
Cleared by software
Cleared in
software
ACK
RCEN cleared
automatically
P
Set SSPxIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPxSTAT<4>)
and SSPxIF
PEN bit = 1
written here
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
Cleared by software
Cleared by software
D7 D6 D5 D4 D3 D2 D1
A1 R/W
RCEN = 1, start
next receive
FIGURE 25-29:
RCEN cleared
automatically
SEN = 0
Write to SSPxBUF occurs here,
ACK from Slave
start XMIT
Write to SSPxCON2<4>
to start Acknowledge sequence
SDAx = ACKDT (SSPxCON2<5>) = 0
PIC16(L)F1825/9
DS40001440E-page 267
PIC16(L)F1825/9
25.6.8
ACKNOWLEDGE SEQUENCE
TIMING
25.6.9
25.6.8.1
25.6.9.1
FIGURE 25-30:
TBRG
SDAx
ACK
D0
SCLx
SSPxIF
SSPxIF set at
the end of receive
Cleared in
software
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
FIGURE 25-31:
Write to SSPxCON2,
set PEN
Falling edge of
9th clock
TBRG
SCLx
SDAx
ACK
P
TBRG
TBRG
TBRG
DS40001440E-page 268
PIC16(L)F1825/9
25.6.10
SLEEP OPERATION
25.6.13
25.6.11
EFFECTS OF A RESET
25.6.12
MULTI-MASTER MODE
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
FIGURE 25-32:
SDAx
SCLx
BCLxIF
DS40001440E-page 269
PIC16(L)F1825/9
25.6.13.1
FIGURE 25-33:
SDAx
SCLx
Set SEN, enable Start
condition if SDAx = 1, SCLx = 1
SEN
BCLxIF
SSPxIF
SSPxIF and BCLxIF are
cleared by software
DS40001440E-page 270
PIC16(L)F1825/9
FIGURE 25-34:
TBRG
SDAx
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
SCLx
SEN
SCLx = 0 before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
by software
S
SSPxIF
FIGURE 25-35:
SDAx
Set SSPxIF
TBRG
SCLx
S
SCLx pulled low after BRG
time out
SEN
BCLxIF
SSPxIF
SDAx = 0, SCLx = 1,
set SSPxIF
Interrupts cleared
by software
DS40001440E-page 271
PIC16(L)F1825/9
25.6.13.2
FIGURE 25-36:
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
SDAx
SCLx
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
RSEN
BCLxIF
Cleared by software
S
SSPxIF
FIGURE 25-37:
TBRG
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
DS40001440E-page 272
PIC16(L)F1825/9
25.6.13.3
b)
FIGURE 25-38:
TBRG
TBRG
SDAx
SDAx sampled
low after TBRG,
set BCLxIF
SSPxIF
FIGURE 25-39:
TBRG
TBRG
SDAx
Assert SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
DS40001440E-page 273
PIC16(L)F1825/9
TABLE 25-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INLVLA5(1)
INLVLA4
INLVLA3(2)
INLVLA2
INLVLA1
INLVLA0
124
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
INLVLC
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3(2)
INLVLC2(2)
INLVLC1
INLVLC0
135
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
88
INLVLA
INLVLB(1)
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
CCP2IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
CCP2IF
93
SSP1ADD
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
280
SSP1BUF
TMR1IF
89
92
233*
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
278
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
279
SSP1MSK
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
280
SSP1STAT
SMP
CKE
D/A
R/W
UA
BF
276
122
TRISA
TRISB(1)
TRISC
Legend:
Note
1:
2:
SSPM<3:0>
277
TRISA2
TRISA1
TRISA0
TRISB7
TRISB6
TRISB5
TRISB4
128
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3(2)
TRISC2(2)
TRISC1
TRISC0
133
(1)
TRISA5
TRISA4
(2)
TRISA3
Unimplemented location, read as 0. Shaded cells are not used by the MSSP module in I2C mode.
* Page provides register information.
PIC16(L)F1829 only.
PIC16(L)F1825 only.
DS40001440E-page 274
PIC16(L)F1825/9
25.7
EQUATION 25-1:
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1 4
FIGURE 25-40:
SSPM<3:0>
Reload
SSPxADD<7:0>
Reload
Control
SCLx
SSPxCLK
FOSC/2
TABLE 25-4:
Note:
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical and timing specifications in Table 30-4 and Figure 30-7 to ensure the system
is designed to support the I/O requirements.
DS40001440E-page 275
PIC16(L)F1825/9
REGISTER 25-1:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
P: Stop bit
(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
bit 1
bit 0
DS40001440E-page 276
PIC16(L)F1825/9
REGISTER 25-2:
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV
SSPEN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
C = User cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDAx and SCLx pins must be configured as inputs.
SSPxADD values of 0, 1 or 2 are not supported for I2C Mode.
SSPxADD value of 0 is not supported. Use SSPM = 0000 instead.
DS40001440E-page 277
PIC16(L)F1825/9
REGISTER 25-3:
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6
bit 5
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
DS40001440E-page 278
PIC16(L)F1825/9
REGISTER 25-4:
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes Idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
bit 0
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
DS40001440E-page 279
PIC16(L)F1825/9
REGISTER 25-5:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
bit 0
REGISTER 25-6:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
Master mode:
bit 7-0
bit 7-3
Not used: Unused for Most Significant Address byte. Bit state of this register is a dont care. Bit
pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
bit 7-0
bit 7-1
bit 0
DS40001440E-page 280
PIC16(L)F1825/9
26.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 26-1:
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
TX/CK pin
LSb
(8)
Pin Buffer
and Control
TRMT
SPEN
TXEN
Baud Rate Generator
FOSC
+1
SPBRGH
TX9
BRG16
SPBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
DS40001440E-page 281
PIC16(L)F1825/9
FIGURE 26-2:
CREN
RX/DT pin
Data
Recovery
FOSC
BRG16
+1
SPBRGH
SPBRGL
RSR Register
MSb
Pin Buffer
and Control
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
Stop
RCIDL
OERR
(8)
LSb
0 START
RX9
n
n
FERR
RX9D
RCREG Register
8
FIFO
Data Bus
RCIF
RCIE
Interrupt
DS40001440E-page 282
PIC16(L)F1825/9
26.1
26.1.1.2
Transmitting Data
26.1.1.3
26.1.1
26.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
26.1.1.1
DS40001440E-page 283
PIC16(L)F1825/9
26.1.1.5
TSR Status
26.1.1.7
26.1.1.6
1.
2.
3.
FIGURE 26-3:
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS40001440E-page 284
4.
5.
6.
7.
8.
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
Word 1
Transmit Shift Reg.
PIC16(L)F1825/9
FIGURE 26-4:
Write to TXREG
TX/CK
pin
Start bit
bit 1
Word 1
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 2
Transmit Shift Reg.
TABLE 26-1:
Name
bit 0
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Note:
Word 2
Word 1
BRG Output
(Shift Clock)
APFCON0
RXDTSEL
BAUDCON
Bit 6
Bit 5
SDO1SEL(2) SS1SEL(2)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
T1GSEL
TXCKSEL
118
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
292
INLVLA(3)
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INLVLB(1)
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
INLVLC
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
291
RCSTA
SPBRGL
SPBRG<7:0>
SPBRGH
SPBRG<15:8>
TRISA
TRISB(1)
TRISC
TXREG
TXSTA
Note
1:
2:
3:
TRISA5
TRISA4
TRISA3
293*
TRISA2
TRISA1
TRISA0
122
TRISB7
TRISB6
TRISB5
TRISB4
128
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
293*
TX9
TXEN
283
290
Unimplemented location, read as 0. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
PIC16(L)F1829 only.
PIC16(L)F1825 only.
Unshaded cells apply to PIC16(L)F1825 only.
DS40001440E-page 285
PIC16(L)F1825/9
26.1.2
EUSART ASYNCHRONOUS
RECEIVER
26.1.2.1
26.1.2.2
Receiving Data
26.1.2.3
Receive Interrupts
DS40001440E-page 286
PIC16(L)F1825/9
26.1.2.4
26.1.2.5
26.1.2.7
Address Detection
26.1.2.6
DS40001440E-page 287
PIC16(L)F1825/9
26.1.2.8
26.1.2.9
1.
FIGURE 26-5:
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
bit 1
Start
bit
Word 1
RCREG
bit 0
Start
bit
Word 2
RCREG
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS40001440E-page 288
PIC16(L)F1825/9
TABLE 26-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
APFCON0
RXDTSEL
SDO1SEL(2)
SS1SEL(2)
T1GSEL
TXCKSEL
118
BAUDCON
Name
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
292
INLVLA(3)
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
INLVLB(1)
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
INLVLC
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
RCREG
RCSTA
RX9
SREN
SPBRGL
CREN
ADDEN
FERR
OERR
RX9D
SPBRG<7:0>
SPBRGH
TRISA
92
286*
291
293*
SPBRG<15:8>
293*
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
TRISB7
TRISB6
TRISB5
TRISB4
128
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
290
TRISB(1)
Legend:
Note
1:
2:
3:
Unimplemented location, read as 0. Shaded cells are not used for asynchronous reception.
* Page provides register information.
PIC16(L)F1829 only.
PIC16(L)F1825 only.
Unshaded cells apply to PIC16(L)F1825 only.
DS40001440E-page 289
PIC16(L)F1825/9
26.2
REGISTER 26-1:
R/W-/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS40001440E-page 290
PIC16(L)F1825/9
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (1)
REGISTER 26-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-x/x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001440E-page 291
PIC16(L)F1825/9
REGISTER 26-3:
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS40001440E-page 292
PIC16(L)F1825/9
26.3
EXAMPLE 26-1:
CALCULATING BAUD
RATE ERROR
DS40001440E-page 293
PIC16(L)F1825/9
TABLE 26-3:
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
SYNC
BRG16
BRGH
1
Legend:
Name
BAUDCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
292
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRGL
SPBRG<7:0>
SPBRGH
SPBRG<15:8>
TXSTA
FOSC/[4 (n+1)]
TABLE 26-4:
RCSTA
FOSC/[16 (n+1)]
CSRC
TX9
TXEN
SYNC
SENDB
291
293*
293*
BRGH
TRMT
TX9D
290
Legend: Unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
DS40001440E-page 294
PIC16(L)F1825/9
TABLE 26-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1200
0.00
143
2400
2404
0.16
207
2404
0.16
129
2400
0.00
119
2400
0.00
71
9600
9615
0.16
51
9470
-1.36
32
9600
0.00
29
9600
0.00
17
10417
10417
0.00
47
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
19.2k
19.23k
0.16
25
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
57.6k
55.55k
-3.55
57.60k
0.00
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
2400
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.64k
2.12
16
113.64k
-1.36
10
115.2k
0.00
115.2k
0.00
DS40001440E-page 295
PIC16(L)F1825/9
TABLE 26-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
0.00
6666
300.0
-0.01
4166
300.0
0.00
3839
300.0
0.00
2303
1200
1200
-0.02
3332
1200
-0.03
1041
1200
0.00
959
1200
0.00
575
2400
2401
-0.04
832
2399
-0.03
520
2400
0.00
479
2400
0.00
287
71
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.6k
2.12
16
113.636
-1.36
10
115.2k
0.00
115.2k
0.00
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
DS40001440E-page 296
PIC16(L)F1825/9
TABLE 26-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
0.00
26666
6666
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.01
3332
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9604
0.04
832
9597
-0.03
520
9600
0.00
479
9600
0.00
287
10417
10417
0.00
767
10417
0.00
479
10425
0.08
441
10433
0.16
264
19.2k
19.18k
-0.08
416
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
57.6k
57.55k
-0.08
138
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
115.2k
115.9k
0.64
68
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
832
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
DS40001440E-page 297
PIC16(L)F1825/9
26.3.1
AUTO-BAUD DETECT
TABLE 26-6:
FIGURE 26-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
Note:
BRG Value
RX pin
0000h
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS40001440E-page 298
PIC16(L)F1825/9
26.3.2
AUTO-BAUD OVERFLOW
26.3.3
AUTO-WAKE-UP ON BREAK
26.3.3.1
Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all 0s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
DS40001440E-page 299
PIC16(L)F1825/9
FIGURE 26-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
WUE bit
RX/DT Line
RCIF
Note 1:
FIGURE 26-8:
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS40001440E-page 300
PIC16(L)F1825/9
26.3.4
26.3.4.1
26.3.5
FIGURE 26-9:
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
Auto Cleared
DS40001440E-page 301
PIC16(L)F1825/9
26.4
26.4.1
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
26.4.1.3
26.4.1.4
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
26.4.1.1
26.4.1.2
1.
2.
3.
4.
5.
6.
Master Clock
7.
8.
Clock Polarity
DS40001440E-page 302
PIC16(L)F1825/9
FIGURE 26-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 26-11:
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 26-7:
Name
Bit 6
Bit 5
APFCON0
RXDTSEL
SDO1SEL(1)
BAUDCON
ABDOVF
Bit 0
Register on
Page
118
WUE
ABDEN
292
INTF
IOCIF
87
CCP1IE
TMR2IE
TMR1IE
88
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
ADDEN
FERR
OERR
RX9D
Bit 4
Bit 3
Bit 2
SS1SEL(1)
T1GSEL
TXCKSEL
RCIDL
SCKP
BRG16
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SPEN
RX9
SREN
CREN
INTCON
RCSTA
SPBRGL
SPBRG<7:0>
SPBRGH
TRISC
TRISC5
TRISC4
TRISC3
293*
TRISC2
TRISC1
TRISC0
TXSTA
CSRC
Legend:
Note
TRISC6
1:
TX9
291
293*
SPBRG<15:8>
TRISC7
TXREG
Bit 1
133
283*
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
290
Unimplemented location, read as 0. Shaded cells are not used for synchronous master transmission.
* Page provides register information.
PIC16(L)F1825 only.
DS40001440E-page 303
PIC16(L)F1825/9
26.4.1.5
26.4.1.6
Slave Clock
DS40001440E-page 304
26.4.1.7
26.4.1.8
26.4.1.9
1.
PIC16(L)F1825/9
FIGURE 26-12:
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 26-8:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON0
RXDTSEL
SDO1SEL(1)
SS1SEL(1)
T1GSEL
TXCKSEL
118
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
292
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
Name
INTCON
RCREG
RCSTA
RX9
SREN
286*
CREN
ADDEN
FERR
OERR
RX9D
291
SPBRGL
SPBRG<7:0>
293*
SPBRGH
SPBRG<15:8>
293*
CSRC
TXSTA
Legend:
Note
1:
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
290
Unimplemented location, read as 0. Shaded cells are not used for synchronous master reception.
* Page provides register information.
PIC16(L)F1825 only.
DS40001440E-page 305
PIC16(L)F1825/9
26.4.2
1.
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
2.
3.
4.
26.4.2.1
5.
26.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
TABLE 26-9:
Name
Bit 6
Bit 5
APFCON0
RXDTSEL
SDO1SEL(1)
BAUDCON
ABDOVF
Bit 0
Register on
Page
118
WUE
ABDEN
292
INTF
IOCIF
87
CCP1IE
TMR2IE
TMR1IE
88
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
CREN
ADDEN
FERR
OERR
RX9D
291
SYNC
SENDB
BRGH
TRMT
TX9D
Bit 4
Bit 3
Bit 2
SS1SEL(1)
T1GSEL
TXCKSEL
RCIDL
SCKP
BRG16
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SPEN
RX9
SREN
INTCON
RCSTA
TXREG
TXSTA
Note
Legend:
1:
Bit 1
TX9
TXEN
283*
290
Unimplemented location, read as 0. Shaded cells are not used for Synchronous Slave Transmission.
* Page provides register information.
PIC16(L)F1825 only.
DS40001440E-page 306
PIC16(L)F1825/9
26.4.2.3
26.4.2.4
1.
2.
Sleep
CREN bit is always set, therefore the receiver is
never Idle
SREN bit, which is a dont care in Slave mode
3.
4.
5.
6.
7.
8.
9.
Bit 7
Bit 6
Bit 5
APFCON0
RXDTSEL
SDO1SEL(1)
BAUDCON
ABDOVF
INTCON
Bit 1
Bit 0
Register on
Page
Bit 4
Bit 3
Bit 2
SS1SEL(1)
T1GSEL
TXCKSEL
118
RCIDL
SCKP
BRG16
WUE
ABDEN
292
87
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
92
RCREG
286*
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
291
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
290
Legend:
Note
1:
Unimplemented location, read as 0. Shaded cells are not used for synchronous slave reception.
* Page provides register information.
PIC16(L)F1825 only.
DS40001440E-page 307
PIC16(L)F1825/9
26.5
26.5.1
DS40001440E-page 308
26.5.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
26.5.3
PIC16(L)F1825/9
27.0
FIGURE 27-1:
Timer0 Module
FOSC/4
T0CKI
Set
TMR0IF
TMR0CS
T0XCS
0
TMR0
Overflow
CPSCH<3:0>
1
CPSRNG<1:0>
(2)
CPSON
CPSON
CPS0
Capacitive
Sensing
Oscillator
CPS1
CPSOSC
Timer1 Module
T1CS<1:0>
CPS2
CPS3
CPS4
CPS5
CPS6
CPS7
0
Ref-
DAC_output
CPSOUT
1
0
Ref+
CPS8(1)
CPS10(1)
Note 1:
2:
1 FVR
Buffer2
FOSC
FOSC/4
T1OSC/
T1CKI
EN
TMR1H:TMR1L
T1GSEL<1:0>
T1G
sync_C1OUT
sync_C2OUT
CPS9(1)
CPS11(1)
Int.
Ref.
CPSCLK
Timer1 Gate
Control Logic
CPSRM
Reference CPSCON1 register (Register 27-2) for channels implemented on each device.
If CPSON = 0, disabling capacitive sensing, no channel is selected.
DS40001440E-page 309
PIC16(L)F1825/9
FIGURE 27-2:
Oscillator Module
VDD
(1)
(2)
CPSx
(1)
Analog Pin
(2)
CPSCLK
Internal
References
Ref-
0
Ref+
1
DAC_output 1
FVR Buffer2
CPSRM
Note 1:
2:
DS40001440E-page 310
PIC16(L)F1825/9
27.1
Analog MUX
27.3
Voltage References
27.2
DS40001440E-page 311
PIC16(L)F1825/9
27.4
Current Ranges
TABLE 27-1:
CPSRM
Note 1:
selection.
The Noise Detection mode is unique in that it disables
the constant current source associated with the
selected input pin, but leaves the rest of the oscillator
circuitry and pin structure active. This eliminates the
oscillation frequency on the analog pin and greatly
reduces the current consumed by the Oscillator
module. When noise is introduced onto the pin, the
oscillator is driven at the frequency determined by the
noise. This produces a detectable signal at the
comparator stage, indicating the presence of activity
on the pin. Figure 27-2 shows a more detailed drawing
of the constant current sources and comparators
associated with the oscillator and input pin.
Fixed
Variable
CPSRNG<1:0>
Current Range(1)
00
Off
01
Low
10
Medium
11
High
00
Noise Detection
01
Low
10
Medium
11
High
DS40001440E-page 312
PIC16(L)F1825/9
27.5
Timer Resources
27.7
27.6
27.6.1
TIMER0
Software Control
27.7.1
NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
27.6.2
27.7.2
TIMER1
TABLE 27-2:
TMR1ON
TMR1GE
Timer1 Operation
Off
Off
On
REDUCED FREQUENCY
(ADDITIONAL CAPACITIVE LOAD)
DS40001440E-page 313
PIC16(L)F1825/9
27.7.3
FREQUENCY THRESHOLD
27.8
DS40001440E-page 314
PIC16(L)F1825/9
REGISTER 27-1:
R/W-0/0
R/W-0/0
U-0
U-0
CPSON
CPSRM
R/W-0/0
R/W-0/0
CPSRNG<1:0>
R-0/0
R/W-0/0
CPSOUT
T0XCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3-2
bit 0
DS40001440E-page 315
PIC16(L)F1825/9
REGISTER 27-2:
U-0
U-0
U-0
U-0
R/W-0/0(1)
R/W-0/0
R/W-0/0
R/W-0/0
CPSCH<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
TABLE 27-3:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
123
ANSELC
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
134
CPSCON0
CPSON
CPSRM
CPSOUT
T0XCS
315
CPSCON1
INLVLA
INLVLA5
INLVLA4
(1)
CPSRNG<1:0>
CPSCH<3:0>
INLVLA3
INLVLA2
INLVLA1
316
INLVLA0
124
INLVLB
INLVLB7
INLVLB6
INLVLB5
INLVLB4
129
INLVLC
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
135
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
87
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
176
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
185
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
122
OPTION_REG
TRISB(1)
TRISC
TRISB7
TRISB6
TRISB5
TRISB4
128
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
133
Legend: Unimplemented locations, read as 0. Shaded cells are not used by the CPS module.
Note 1:
PIC16(L)F1829 only.
DS40001440E-page 316
PIC16(L)F1825/9
28.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
28.1
FIGURE 28-1:
1
VPP
2
VDD
3
VSS
4
ICSP_DATA
5
ICSP_CLOCK
6
NC
RJ11-6PIN
To MPLAB ICD 2
R1
To Target Board
270 Ohm
LM431BCMX
1
2 A
K
3 A U1
6 A
NC 4
7 A
NC 5
R2
VREF
8
10k 1%
Note:
R3
24k 1%
DS40001440E-page 317
PIC16(L)F1825/9
28.2
FIGURE 28-2:
VDD
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
VPP/MCLR
VSS
Target
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
28.3
FIGURE 28-3:
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
DS40001440E-page 318
PIC16(L)F1825/9
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 28-4 for more
information.
FIGURE 28-4:
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
DS40001440E-page 319
PIC16(L)F1825/9
29.0
29.1
Read-Modify-Write Operations
Byte Oriented
Bit Oriented
Literal and Control
TABLE 29-1:
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
mm
TABLE 29-2:
ABBREVIATION
DESCRIPTIONS
Field
PC
Program Counter
TO
Time-out bit
C
DC
Z
PD
DS40001440E-page 320
Description
Carry bit
Digit carry bit
Zero bit
Power-down bit
PIC16(L)F1825/9
FIGURE 29-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
k (literal)
k (literal)
0
k (literal)
5 4
0
k (literal)
0
k (literal)
6
n
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS40001440E-page 321
PIC16(L)F1825/9
TABLE 29-3:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
01
01
2
2
1, 2
1, 2
f, b
f, b
1 (2)
1 (2)
01
01
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
DS40001440E-page 322
PIC16(L)F1825/9
TABLE 29-3:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
k
k
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
k[n]
1
1
11
00
2, 3
1
1
11
00
2
2, 3
11
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS40001440E-page 323
PIC16(L)F1825/9
29.2
Instruction Descriptions
ADDFSR
ANDLW
Syntax:
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operands:
0 k 255
Operation:
Operation:
FSR(n) + k FSR(n)
Status Affected:
Status Affected:
None
Description:
Description:
AND W with f
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW
ANDWF
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
Operation:
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
ADDWF
Add W and f
f,d
Status Affected:
Description:
ASRF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0 f 127
d 0,1
Operands:
0 f 127
d [0,1]
Operation:
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
f,d
Status Affected:
C, DC, Z
Description:
ADDWFC
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
DS40001440E-page 324
f {,d}
Status Affected:
C, Z
Description:
f {,d}
PIC16(L)F1825/9
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Syntax:
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
BRA
Relative Branch
BTFSS
Syntax:
Syntax:
Operands:
0 f 127
0b<7
Operands:
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
None
Status Affected:
None
Description:
Description:
BRW
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W) PC
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
f,b
Operation:
1 (f<b>)
Status Affected:
None
Description:
DS40001440E-page 325
PIC16(L)F1825/9
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
CALLW
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
f,d
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
DS40001440E-page 326
PIC16(L)F1825/9
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<6:3> PC<14:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
INCF f,d
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
IORWF
f,d
DS40001440E-page 327
PIC16(L)F1825/9
LSLF
MOVF
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Operation:
(f) (dest)
f {,d}
Status Affected:
C, Z
Description:
register f
Description:
Words:
Cycles:
Syntax:
[ label ] LSRF
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
DS40001440E-page 328
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
f {,d}
register f
MOVF f,d
Status Affected:
Example:
Move f
PIC16(L)F1825/9
MOVIW
Move INDFn to W
MOVLP
Syntax:
Syntax:
[ label ] MOVLP k
Operands:
0 k 127
Operands:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation:
INDFn W
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
Operation:
k PCLATH
Status Affected:
None
Description:
MOVLW
Move literal to W
Syntax:
[ label ]
0 k 255
Operation:
k (W)
Status Affected:
None
Description:
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
MOVLB
Syntax:
[ label ] MOVLB k
Operands:
0 k 15
Operation:
k BSR
Status Affected:
None
Description:
MOVLW k
Operands:
Predecrement
MOVLW
0x5A
After Instruction
W =
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
0x5A
Status Affected:
None
Description:
Words:
Cycles:
Example:
MOVWF
OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
DS40001440E-page 329
PIC16(L)F1825/9
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
Syntax:
[ label ]
Operands:
None
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Description:
No operation.
Words:
Cycles:
Operands:
Operation:
Status Affected:
W INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
None
Operation:
No operation
Status Affected:
None
Example:
NOP
OPTION
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION_REG
Status Affected:
None
Description:
Mode
Syntax
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Words:
Postdecrement
FSRn--
11
Cycles:
Example:
OPTION
Description:
mm
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
DS40001440E-page 330
NOP
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Status Affected:
None
Description:
PIC16(L)F1825/9
RETFIE
RETURN
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE
RETURN
Operands:
None
Operands:
Operation:
TOS PC,
1 GIE
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RETLW
Syntax:
[ label ]
Operands:
0 k 255
Operation:
k (W);
TOS PC
Status Affected:
None
Description:
Words:
Cycles:
Example:
TABLE
RETLW k
RLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
RLF
Operation:
Status Affected:
Description:
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
f,d
Words:
Cycles:
Example:
RLF
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
DS40001440E-page 331
PIC16(L)F1825/9
SUBLW
Syntax:
[ label ]
RRF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Status Affected:
Description:
Description:
RRF f,d
SUBLW k
Operands:
0 k 255
Operation:
k - (W) W)
Register f
C=0
Wk
C=1
Wk
DC = 0
W<3:0> k<3:0>
DC = 1
W<3:0> k<3:0>
SLEEP
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Description:
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
DS40001440E-page 332
SUBWF f,d
C=0
Wf
C=1
Wf
DC = 0
W<3:0> f<3:0>
DC = 1
W<3:0> f<3:0>
SUBWFB
Syntax:
SUBWFB
Operands:
0 f 127
d [0,1]
Operation:
f {,d}
Status Affected:
C, DC, Z
Description:
PIC16(L)F1825/9
SWAPF
Swap Nibbles in f
XORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
(W) .XOR. k W)
Status Affected:
Description:
Operation:
SWAPF f,d
Status Affected:
None
Description:
XORWF
TRIS
XORLW k
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
XORWF
f,d
Syntax:
[ label ] TRIS f
Operands:
5f7
Operation:
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
DS40001440E-page 333
PIC16(L)F1825/9
30.0
ELECTRICAL SPECIFICATIONS
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS40001440E-page 334
PIC16(L)F1825/9
PIC16F1825/9 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
FIGURE 30-1:
VDD (V)
5.5
2.5
1.8
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator modes supported frequencies.
VDD (V)
FIGURE 30-2:
3.6
2.5
1.8
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator modes supported frequencies.
DS40001440E-page 335
PIC16(L)F1825/9
FIGURE 30-3:
125
5%
Temperature (C)
85
3%
60
25
2%
0
-20
-40
1.8
5%
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 336
PIC16(L)F1825/9
30.1
PIC16LF1825/9
PIC16F1825/9
Param.
No.
D001
Sym.
VDD
Characteristic
VDR
Max.
Units
Conditions
PIC16LF1825/9
1.8
2.5
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
PIC16F1825/9
1.8
2.5
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
D002*
D002B*
Typ
D001
D002*
Min.
PIC16LF1825/9
1.5
PIC16F1825/9
1.7
1.6
VPOR*
VPORR*
0.8
PIC16F1825/9
1.5
D003
VADFVR
-8
D003A
VCDAFVR
-11
D003C*
TCVFVR
-130
ppm/C
D003D*
VFVR/
VIN
0.270
%/V
D004*
SVDD
0.05
V/ms
Note
DS40001440E-page 337
PIC16(L)F1825/9
FIGURE 30-4:
VDD
VPOR
VPORR
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
DS40001440E-page 338
TPOR(3)
PIC16(L)F1825/9
30.2
PIC16LF1825/9
PIC16F1825/9
Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
VDD
Note
5.5
15
1.8
7.8
18
3.0
20
55
1.8
25
60
3.0
27
65
5.0
D011
83
140
1.8
130
230
3.0
D011
105
160
1.8
160
250
3.0
230
320
5.0
220
310
1.8
378
540
3.0
240
300
1.8
400
500
3.0
500
760
5.0
D013
46
160
1.8
90
230
3.0
D013
70
180
1.8
120
240
3.0
190
320
5.0
192
250
1.8
336
430
3.0
210
275
1.8
356
450
3.0
430
650
5.0
D010
D010
D012
D012
D014
D014
Note 1:
2:
3:
4:
5:
FOSC = 32 kHz
LP Oscillator mode
FOSC = 32 kHz
LP Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode, Medium-Power mode
FOSC = 1 MHz
EC Oscillator mode
Medium-Power mode
FOSC = 4 MHz
EC Oscillator mode,
Medium-Power mode
FOSC = 4 MHz
EC Oscillator mode
Medium-Power mode
DS40001440E-page 339
PIC16(L)F1825/9
30.2
PIC16LF1825/9
PIC16F1825/9
Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
VDD
Note
6.5
18
1.8
9.0
20
3.0
20
60
1.8
25
65
3.0
27
70
5.0
D016
110
170
1.8
130
200
3.0
D016
125
180
1.8
155
250
3.0
160
280
5.0
0.6
0.85
mA
1.8
0.9
1.25
mA
3.0
0.6
0.85
mA
1.8
0.96
1.35
mA
3.0
D017*
D017*
1.03
1.55
mA
5.0
D018
0.9
1.2
mA
1.8
1.4
1.95
mA
3.0
D018
0.92
1.2
mA
1.8
1.49
1.9
mA
3.0
1.58
2.4
mA
5.0
2.8
3.6
mA
3.0
3.4
3.9
mA
3.6
2.8
4.0
mA
3.0
3.0
4.5
mA
5.0
D019
D019
*
Note 1:
2:
3:
4:
5:
FOSC = 31 kHz
LFINTOSC mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
FOSC = 32 MHz
HFINTOSC mode (Note 3)
FOSC = 32 MHz
HFINTOSC mode (Note 3)
DS40001440E-page 340
PIC16(L)F1825/9
30.2
PIC16LF1825/9
PIC16F1825/9
Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
VDD
Note
Note 1:
2:
3:
4:
5:
2.7
3.6
mA
3.0
3.2
4.2
mA
3.6
2.7
4.0
mA
3.0
3.2
4.3
mA
5.0
222
350
1.8
400
690
3.0
240
500
1.8
416
800
3.0
497
900
5.0
FOSC = 32 MHz
HS Oscillator mode (Note 4)
FOSC = 32 MHz
HS Oscillator mode (Note 4)
FOSC = 4 MHz
EXTRC mode (Note 5)
FOSC = 4 MHz
EXTRC mode (Note 5)
DS40001440E-page 341
PIC16(L)F1825/9
30.3
PIC16LF1825/9
PIC16F1825/9
Param
No.
Device Characteristics
Power-down Base Current
Min.
Conditions
Max.
+85C
Max.
+125C
Units
0.02
1.0
2.7
Typ
VDD
D022
0.05
1.75
3.3
3.0
D022
17.8
37
44
1.8
20.5
42
48
3.0
21.7
45
65
5.0
0.3
1.5
3.0
1.8
0.5
2.0
3.7
3.0
18
38
44
1.8
20.9
43
48
3.0
D023
D023
D023A
D023A
Note
(IPD)(2)
1.8
22.1
48
65
5.0
12.6
22
25
1.8
12.8
24
27
3.0
32.7
62
65
1.8
39
72
75
3.0
69
115
120
5.0
D024
14
16
3.0
D024
24
47
50
3.0
27
55
70
5.0
D025
0.65
4.5
1.8
1.3
5.5
3.0
D025
19
39
45
1.8
21.6
42
65
3.0
23
47
52
5.0
0.05
1.5
3.0
1.8
0.07
2.0
3.5
3.0
17.8
38
45
1.8
21
45
50
3.0
22
50
65
5.0
D026
D026
Note 1:
2:
3:
DS40001440E-page 342
PIC16(L)F1825/9
30.3
PIC16LF1825/9
PIC16F1825/9
Param
No.
Device Characteristics
Min.
D027
D027
D027A
D027A
D027B
D027B
Typ
Conditions
Max.
+85C
Max.
+125C
Units
VDD
250
1.8
250
3.0
280
1.8
280
3.0
280
5.0
2.3
1.8
3.5
3.0
20
41
45
1.8
23
47
55
3.0
25
55
75
5.0
10
1.8
6.5
13
14
3.0
23
44
47
1.8
26
53
60
3.0
29
57
71
5.0
13
22
24
1.8
35
45
47
3.0
30
58
65
1.8
55
84
90
3.0
59
95
110
5.0
D028
6.8
16
17
1.8
7.3
18
19
3.0
D028
24
45
50
1.8
27
56
61
3.0
29
60
80
5.0
28
46
48
1.8
29
48
49
3.0
60
80
85
1.8
62
85
90
3.0
64
90
105
5.0
D028B
D028B
Note 1:
2:
3:
Note
(2)
Comparator Current
High-Power mode (Note 1)
Comparator Current,
High-Power mode (Note 1)
DS40001440E-page 343
PIC16(L)F1825/9
30.4
DC Characteristics: PIC16(L)F1825/9-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Typ
Max.
Units
Conditions
0.8
0.15 VDD
0.2 VDD
0.3 VDD
D030
D030A
D031
0.8
0.2 VDD
0.3 VDD
D040
2.0
0.25 VDD +
0.8
0.8 VDD
0.7 VDD
D040A
D041
2.1
D042
MCLR
0.8 VDD
D043A
0.7 VDD
D043B
0.9 VDD
IIL
D060
I/O ports
125
nA
1000
nA
D061
MCLR(3)
50
200
nA
25
25
100
140
200
300
0.6
VDD - 0.7
15
pF
50
pF
IPUR
D070*
VOL
D080
VOH
D090
D101A* CIO
*
Note 1:
2:
3:
4:
DS40001440E-page 344
PIC16(L)F1825/9
30.5
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
VIHH
8.0
9.0
D111
IDDVPP
10
mA
D112
VBE
2.7
VDDMAX
D113
VPEW
VDDMIN
VDDMAX
D114
1.0
mA
D115
5.0
mA
D116
ED
Byte Endurance
D117
VDRW
(Note 3, 4)
E/W
VDDMIN
VDDMAX
-40C to +85C
D118
TDEW
4.0
5.0
ms
D119
TRETD
Characteristic Retention
40
Year
Provided no other
specifications are violated
D120
TREF
1M
10M
E/W
-40C to +85C
10K
E/W
VDDMIN
VDDMAX
EP
Cell Endurance
D122
VPRW
D123
TIW
2.5
ms
D124
TRETD
Characteristic Retention
40
Year
Note 1:
2:
3:
4:
Provided no other
specifications are violated
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Self-write and Block Erase.
Refer to Section 11.2 Using the Data EEPROM for a more detailed discussion on data EEPROM endurance.
Required only if single-supply programming is disabled.
The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed
between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2.
DS40001440E-page 345
PIC16(L)F1825/9
30.6
Thermal Considerations
TH02
TH03
TH04
TH05
Sym.
Characteristic
JA
JC
TJMAX
PD
Typ.
Units
Conditions
70.0
C/W
95.3
C/W
100
C/W
45.7
C/W
31.8
C/W
62.2
C/W
77.7
C/W
87.3
C/W
43.0
C/W
32.8
C/W
32.8
C/W
31.0
C/W
24.4
C/W
6.3
C/W
24.4
C/W
27.5
C/W
23.1
C/W
31.1
C/W
5.3
C/W
27.4
C/W
150
PD = PINTERNAL + PI/O
TH06
PI/O
TH07
PDER
Derated Power
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature.
DS40001440E-page 346
PIC16(L)F1825/9
30.7
FIGURE 30-5:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCKx
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
DS40001440E-page 347
PIC16(L)F1825/9
30.8
AC Characteristics: PIC16(L)F1825/9-I/E
FIGURE 30-6:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 30-1:
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
Oscillator Period(1)
OS03
TCY
OS04*
TosH,
TosL
TosR,
TosF
OS05*
Min.
Typ
Max.
Units
Conditions
DC
0.5
MHz
DC
MHz
DC
32
MHz
32.768
kHz
LP Oscillator mode
0.1
MHz
XT Oscillator mode
MHz
20
MHz
DC
MHz
RC Oscillator mode
27
LP Oscillator mode
250
ns
XT Oscillator mode
50
ns
HS Oscillator mode
31.25
ns
EC Oscillator mode
30.5
LP Oscillator mode
250
10,000
ns
XT Oscillator mode
50
1,000
ns
HS Oscillator mode
250
ns
RC Oscillator mode
125
DC
ns
TCY = FOSC/4
LP oscillator
100
ns
XT oscillator
20
ns
HS oscillator
ns
LP oscillator
ns
XT oscillator
ns
HS oscillator
DS40001440E-page 348
PIC16(L)F1825/9
TABLE 30-2:
OSCILLATOR PARAMETERS
Sym.
HFOSC
OS08A MFOSC
Freq.
Tolerance
Min.
Typ
Max.
Units
Conditions
2%
16.0
MHz
3%
16.0
MHz
5%
16.0
MHz
-40C TA +125C
2%
500
kHz
3%
500
kHz
5%
500
kHz
-40C TA +125C
25%
31
kHz
-40C TA +125C
20
30
Characteristic
OS09
LFOSC
OS10*
TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
MFINTOSC
Wake-up from Sleep Start-up Time
TABLE 30-3:
Param
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
F10
MHz
F11
FSYS
16
32
MHz
F12
TRC
F13*
CLK
ms
-0.25%
+0.25%
Conditions
FIGURE 30-7:
Cycle
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS16
OS13
OS18
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS40001440E-page 349
PIC16(L)F1825/9
TABLE 30-4:
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
70
ns
VDD = 3.3-5.0V
72
ns
VDD = 3.3-5.0V
OS11
TosH2ckL
OS12
(1)
OS13
TckL2ioV
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18* TioR
OS19* TioF
(1)
20
ns
TOSC + 200 ns
50
50
70*
ns
ns
ns
20
ns
25
25
40
15
28
15
72
32
55
30
ns
OS20* Tinp
OS21* Tioc
FIGURE 30-8:
ns
VDD = 3.3-5.0V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
ns
ns
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
DS40001440E-page 350
PIC16(L)F1825/9
FIGURE 30-9:
VDD
VBOR and VHYST
VBOR
37
Reset
(due to BOR)
33(1)
DS40001440E-page 351
PIC16(L)F1825/9
TABLE 30-5:
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
12
16
20
ms
1024
Tosc
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.55
1.80
2.70
1.9
2.85
2.05
V
V
36*
VHYST
20
35
75
mV
-40C to +85C
37*
35
VDD VBOR
30
TMCL
31
32
TOST
33*
VDD = 3.3V-5V,
1:16 Prescaler used
BORV = 0
BORV = 1
FIGURE 30-10:
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
DS40001440E-page 352
PIC16(L)F1825/9
TABLE 30-6:
Sym.
TT0H
Characteristic
T0CKI High-Pulse Width
Min.
No Prescaler
TT0L
No Prescaler
TT0P
T0CKI Period
45*
TT1H
ns
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
Asynchronous
TT1L
46*
T1CKI Low
Time
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
47*
TT1P
48
FT1
49*
Asynchronous
Units
10
With Prescaler
42*
Max.
0.5 TCY + 20
With Prescaler
41*
Typ
60
ns
32.4
32.768
33.1
kHz
2 TOSC
7 TOSC
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
FIGURE 30-11:
CCP
(Capture mode)
CC01
CC02
CC03
Note:
TABLE 30-7:
Characteristic
CCP Input Low Time
CCP Input High Time
CCP Input Period
Min.
Typ
Max.
Units
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
3TCY + 40
N
ns
Conditions
N = prescale value
DS40001440E-page 353
PIC16(L)F1825/9
TABLE 30-8:
Characteristic
Min.
Typ
Max.
Units
Conditions
AD01
NR
Resolution
10
AD02
EIL
Integral Error
1.7
AD03
EDL
Differential Error
AD04
2.5
AD05
EGN
AD06
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
Note 1:
2:
3:
4:
Gain Error
bit
LSb VREF = 3.0V
LSb No missing codes
VREF = 3.0V
2.0
1.8
VDD
VSS
VREF
10
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Total Absolute Error includes integral, differential, offset and gain errors.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.
ADC Reference Voltage (REF+) is the selected input, VREF+ pin, VDD pin or the FVR Buffer1. When the FVR is selected as
the reference input, the FVR Buffer1 output selection must be 2.048 or 4.096V (ADFVR<1:0> = 1x).
TABLE 30-9:
Sym.
AD130* TAD
AD131
TCNV
AD132* TACQ
Characteristic
Min.
Typ
Max.
Units
Conditions
1.0
9.0
TOSC-based
1.0
2.5
6.0
11
TAD
Acquisition Time
5.0
DS40001440E-page 354
PIC16(L)F1825/9
FIGURE 30-12:
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
7
A/D Data
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 30-13:
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
7
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS40001440E-page 355
PIC16(L)F1825/9
TABLE 30-10: COMPARATOR SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25C
Param
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
Comments
7.5
60
mV
High-Power mode
VICM = VDD/2
CM01
VIOFF
CM02
VICM
VDD
CM03
CMRR
50
dB
CM04A
400
800
ns
High-Power mode
CM04B
200
400
ns
High-Power mode
1200
ns
Low-Power mode
550
ns
Low-Power mode
10
65
mV
TRESP(1)
CM04C
CM04D
CM05
TMC2OV
CM06
Note 1:
2:
CxHYS = 1
Sym.
Characteristics
Min.
Typ.
Max.
Units
DAC01*
CLSB
Step Size(2)
VDD/32
DAC02*
CACC
Absolute Accuracy
1/2
LSb
DAC03*
CR
5K
DAC04*
CST
Settling Time(1)
10
*
Note 1:
Comments
Characteristic
Min.
Typ
Max.
Units
LD001
3.2
LD002
0.1
Conditions
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS40001440E-page 356
PIC16(L)F1825/9
FIGURE 30-14:
CK
US121
US121
DT
US122
US120
Note:
Symbol
Characteristic
Min.
Max.
Units
3.0-5.5V
80
ns
1.8-5.5V
100
ns
US121 TCKRF
3.0-5.5V
45
ns
1.8-5.5V
50
ns
3.0-5.5V
45
ns
1.8-5.5V
50
ns
US122 TDTRF
FIGURE 30-15:
Conditions
US125
DT
US126
Note: Refer to Figure 30-5 for load conditions.
Symbol
Characteristic
Min.
Max.
Units
10
ns
15
ns
Conditions
DS40001440E-page 357
PIC16(L)F1825/9
FIGURE 30-16:
SSx
SP70
SCKx
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCKx
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDOx
LSb
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 30-5 for load conditions.
FIGURE 30-17:
SSx
SP81
SCKx
(CKP = 0)
SP71
SP72
SP79
SP73
SCKx
(CKP = 1)
SP80
SDOx
MSb
bit 6 - - - - - -1
SP78
LSb
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 30-5 for load conditions.
DS40001440E-page 358
PIC16(L)F1825/9
FIGURE 30-18:
SSx
SP70
SCKx
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCKx
(CKP = 1)
SP80
MSb
SDOx
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 30-5 for load conditions.
FIGURE 30-19:
SSx
SCKx
(CKP = 0)
SP71
SP72
SCKx
(CKP = 1)
SP80
SDOx
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 30-5 for load conditions.
DS40001440E-page 359
PIC16(L)F1825/9
TABLE 30-15: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min.
Typ
2.25 TCY
ns
SP71* TSCH
TCY + 20
ns
SP72* TSCL
TCY + 20
ns
100
ns
100
ns
SP75* TDOR
SP76* TDOF
3.0-5.5V
10
25
ns
1.8-5.5V
25
50
ns
10
25
ns
SP77* TSSH2DOZ
10
50
ns
SP78* TSCR
3.0-5.5V
10
25
ns
1.8-5.5V
25
50
ns
SP79* TSCF
10
25
ns
3.0-5.5V
50
ns
1.8-5.5V
145
ns
Tcy
ns
50
ns
1.5TCY + 40
ns
SP82* TSSL2DOV
DS40001440E-page 360
PIC16(L)F1825/9
FIGURE 30-20:
SCLx
SP93
SP91
SP90
SP92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-5 for load conditions.
Symbol
SP90*
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
SP93
Characteristic
Typ
Max. Units
Start condition
4700
Setup time
600
Start condition
4000
Hold time
600
Stop condition
4700
Setup time
600
4000
600
Min.
Conditions
ns
ns
ns
ns
FIGURE 30-21:
SCLx
SP100
SP90
SP102
SP101
SP106
SP107
SP91
SDAx
In
SP92
SP110
SP109
SP109
SDAx
Out
Note: Refer to Figure 30-5 for load conditions.
DS40001440E-page 361
PIC16(L)F1825/9
TABLE 30-17: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
SP100* THIGH
SP101* TLOW
SP102* TR
SP103* TF
SP106* THD:DAT
SP107* TSU:DAT
SP109* TAA
SP110*
SP111
*
Note 1:
2:
TBUF
CB
Characteristic
Min.
Max.
Units
Conditions
4.0
0.6
SSPx module
1.5TCY
4.7
1.3
SSPx module
1.5TCY
1000
ns
20 + 0.1CB
300
ns
250
ns
20 + 0.1CB
250
ns
ns
0.9
250
ns
100
ns
3500
ns
ns
4.7
1.3
400
pF
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
DS40001440E-page 362
PIC16(L)F1825/9
30.9
Condition
Value
Source
15 mA
Sink
15 mA
Source
5 mA
Sink
5 mA
-65C to 155C
+155C
-40C to +150C
Note:
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure above maximum
rating conditions for extended periods may affect device reliability.
DS40001440E-page 363
PIC16(L)F1825/9
PIC16F1825/9 VOLTAGE FREQUENCY GRAPH, -40C TA +150C
FIGURE 30-22:
VDD (V)
5.5
2.5
1.8
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator modes supported frequencies.
FIGURE 30-23:
150
10%
No Operation
Temperature (C)
125
85
25
5%
-40
1.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 364
PIC16(L)F1825/9
TABLE 30-19: DC CHARACTERISTICS FOR PIC16F1825/9-H (High Temp.)
Standard Operating Conditions: (unless otherwise stated)
Operating Temperature: -40C TA +150C for High Temperature
PIC16F1825/9
Param
No.
Sym.
Characteristics
Supply Voltage
Min.
Typ.
Max.
Units
Condition
2.5
5.5
2.1
5.5
D001
VDD
D002*
VDR
D003
-10
-13
(1)
DS40001440E-page 365
PIC16(L)F1825/9
TABLE 30-20: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC16F1825/9-H (High
Temp.)
Standard Operating Conditions: (unless otherwise stated)
Operating Temperature: -40C TA +150C for High Temperature
PIC16F1825/9
Param
No.
Condition
Device Characteristics
Min.
Typ.
Max.
Units
VDD
D010
D011
D012
D013
D014
D016
D017
D018
D019
Note
(1,2)
13
58
2.0
19
67
3.0
32
92
5.0
135
316
2.0
185
400
3.0
300
537
5.0
240
495
2.0
360
680
3.0
0.660
1.20
mA
5.0
75
158
2.0
155
338
3.0
345
792
5.0
185
357
2.0
325
625
3.0
0.665
1.30
mA
5.0
245
476
2.0
360
672
3.0
0.620
1.10
mA
5.0
395
757
2.0
0.620
1.20
mA
3.0
1.20
2.20
mA
5.0
175
332
2.0
285
518
3.0
530
972
5.0
2.20
4.10
mA
4.5
2.80
4.80
mA
5.0
FOSC 32 kHz
LP Oscillator mode
FOSC 1 MHz
XT Oscillator mode
FOSC 4 MHz
XT Oscillator mode
FOSC 1 MHz
EC Oscillator mode
FOSC 4 MHz
EC Oscillator mode
FOSC 4 MHz
INTOSC mode
FOSC 8 MHz
INTOSC mode
FOSC 4 MHz
EXTRC mode
FOSC 20 MHz
HS Oscillator mode
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rage, oscillator type, internal code execution pattern, and temperature, also have
an impact on the current consumption.
DS40001440E-page 366
PIC16(L)F1825/9
TABLE 30-21: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC16F1825/9-H (High
Temp.)
PIC16F1825/9
Param
No.
Device Characteristics
Min.
Typ.
Max.
Units
Note
VDD
Power-Down Base Current (IPD)
D020E
D021E
(2)
0.05
12
2.0
0.15
13
3.0
0.35
14
5.0
0.5
20
2.0
2.5
25
3.0
9.5
36
5.0
5.0
28
3.0
6.0
36
5.0
105
195
2.0
110
210
3.0
116
220
5.0
50
105
2.0
55
110
3.0
60
125
5.0
30
58
2.0
45
85
3.0
75
142
5.0
39
76
2.0
59
114
3.0
98
190
5.0
5.5
30
2.0
D026E
7.0
35
3.0
8.5
45
5.0
D027E
0.2
12
3.0
0.3
15
5.0
D022E
D023E
D024E
D025E
IPD Base
WDT Current
BOR Current
IPD Current (both comparators
enabled)
IPD Current (one comparator
enabled)
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rage, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: A/D oscillator source is FRC.
DS40001440E-page 367
PIC16(L)F1825/9
TABLE 30-22: MEMORY PROGRAMMING REQUIREMENTS FOR PIC16F1825/9-H (High Temp.)
PIC16F1825/9
Param
No.
Sym.
Characteristic
Min.
Typ.
Max.
Units
Conditions
D116
ED
Byte Endurance
50K
E/W
-40C to +150C
D118
TDEW
6.0
ms
-40C to +150C
D119
TRETD
Data Retention
20
D121
EP
Cell Endurance
D124
TRETD
Data Retention
20
Years
PIC16F1825/9
Param
No.
OS08
Sym.
Characteristic
OS09
Frequency
Tolerance
Min.
Typ.
Max.
Units
5%
16.0
MHz
-40C TA 125C
VDD 2.5V
10%
16.0
MHz
-40C TA 150C
VDD 2.5V
5%
500
kHz
-40C TA 125C
VDD 2.5V
10%
500
kHz
-40C TA 150C
VDD 2.5V
35%
31
kHz
-40C TA 150C
VDD 2.5V
Conditions
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
TABLE 30-24: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS FOR PIC16F1825/9-H (High Temp.)
Standard Operating Conditions: (unless otherwise stated)
Operating Temperature: -40C TA +150C for High Temperature
PIC16F1825/9
Param
No.
Sym.
Characteristic
31
35
VBOR
Min.
Typ.
Max.
Units
Conditions
20
70
ms
VDD = 3.3V-5V
1:16 Prescaler used
2.50
2.70
2.90
BORV = 0
BORV = 1
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS40001440E-page 368
PIC16(L)F1825/9
TABLE 30-25: A/D CONVERTER (ADC) CHARACTERISTICS FOR PIC16F1825/9-H (High Temp.)
Standard Operating Conditions: (unless otherwise stated)
Operating Temperature: -40C TA +150C for High Temperature
PIC16F1825/9
Param
No.
AD04
Sym.
EOFF
Characteristic
Offset Error
Min.
Typ.
Max. Units
3.5
Conditions
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.
PIC16F1825/9
Param
No.
CM01
Sym.
VIOFF
Characteristic
Min.
Typ.
Max.
Units
70
mV
Conditions
High-Power mode,
VICM = VDD/2
TABLE 30-27: CAP SENSE OSCILLATOR SPECIFICATIONS FOR PIC16F1825/9-H (High Temp.)
Standard Operating Conditions: (unless otherwise stated)
Operating Temperature: -40C TA +150C for High Temperature
PIC16F1825/9
Param
No.
All
Sym.
All
Characteristic
All
Min.
Typ.
Max. Units
Conditions
DS40001440E-page 369
PIC16(L)F1825/9
31.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at 25C. MAXIMUM, Max., MINIMUM or Min. represents
(mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range.
DS40001440E-page 370
PIC16(L)F1825/9
FIGURE 31-1:
12
Max: 85C + 3
Typical: 25C
10
Max.
IDD (A)
8
Typical
6
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-2:
45
Max: 85C + 3
Typical: 25C
40
Max.
35
IDD (A)
30
Typical
25
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 371
PIC16(L)F1825/9
FIGURE 31-3:
400
4 MHz XT
Typical: 25C
350
4 MHz EXTRC
300
IDD (A)
250
200
1 MHz XT
150
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-4:
450
Max: 85C + 3
400
4 MHz XT
350
4 MHz EXTRC
IDD (A)
300
250
200
1 MHz XT
150
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001440E-page 372
PIC16(L)F1825/9
FIGURE 31-5:
500
4 MHz EXTRC
Typical: 25C
450
4 MHz XT
400
350
IDD (A)
300
250
200
150
1 MHz XT
100
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-6:
600
Max: 85C + 3
4 MHz EXTRC
500
4 MHz XT
IDD (A)
400
300
200
1 MHz XT
100
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001440E-page 373
PIC16(L)F1825/9
FIGURE 31-7:
350
4 MHz
Typical: 25C
300
IDD (A)
250
200
150
1 MHz
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
3.4
3.6
3.8
VDD (V)
FIGURE 31-8:
400
Max: 85C + 3
350
4 MHz
300
IDD (A)
250
200
150
1 MHz
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
VDD (V)
DS40001440E-page 374
PIC16(L)F1825/9
FIGURE 31-9:
450
4 MHz
400
Typical: 25C
350
IDD (A)
300
250
200
1 MHz
150
100
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.5
6.0
VDD (V)
FIGURE 31-10:
500
4 MHz
Max: 85C + 3
450
400
IDD (A)
350
300
250
200
1 MHz
150
100
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (V)
DS40001440E-page 375
PIC16(L)F1825/9
FIGURE 31-11:
12
Max.
10
Typical
IDD (A)
4
Max: 85C + 3
Typical: 25C
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-12:
40
Max.
35
IDD (A)
30
Typical
25
20
15
10
Max: 85C + 3
Typical: 25C
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 376
PIC16(L)F1825/9
FIGURE 31-13:
160
Max.
Max: 85C + 3
Typical: 25C
150
Typical
IDD (A)
140
130
120
110
100
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-14:
240
Max.
Max: 85C + 3
Typical: 25C
220
Typical
IDD (A)
200
180
160
140
120
100
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 377
PIC16(L)F1825/9
FIGURE 31-15:
3.5
32 MHz (PLL)
Typical: 25C
3.0
IDD (mA)
2.5
2.0
16 MHz
1.5
8 MHz
1.0
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
3.6
3.8
VDD (V)
FIGURE 31-16:
3.5
32 MHz (PLL)
Max: 85C + 3
3.0
IDD (mA)
2.5
2.0
16 MHz
1.5
8 MHz
1.0
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
VDD (V)
DS40001440E-page 378
PIC16(L)F1825/9
FIGURE 31-17:
3.0
32 MHz (PLL)
Typical: 25C
2.5
IDD (mA)
2.0
16 MHz
1.5
8 MHz
1.0
0.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.5
6.0
VDD (V)
FIGURE 31-18:
3.0
32 MHz (PLL)
Max: 85C + 3
2.5
2.0
IDD (mA)
16 MHz
1.5
8 MHz
1.0
0.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (V)
DS40001440E-page 379
PIC16(L)F1825/9
FIGURE 31-19:
3.5
Max
3.0
Typical: 25C
Typical
IDD (mA)
2.5
2.0
1.5
1.0
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-20:
3.5
Max
3.0
Typical: 25C
2.5
Typical
IDD (mA)
2.0
1.5
1.0
0.5
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001440E-page 380
PIC16(L)F1825/9
FIGURE 31-21:
0.40
0.35
Max.
IPD (A)
0.30
Max: 85C + 3
Typical: 25C
0.25
0.20
0.15
0.10
Typical
0.05
0.00
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
5.0
5.5
VDD (V)
FIGURE 31-22:
50
Max: 85C + 3
M
3
Typical: 25C
45
40
IPD (A)
35
Max.
30
25
20
Typical
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
DS40001440E-page 381
PIC16(L)F1825/9
FIGURE 31-23:
0.9
Max.
Max: 85C + 3
Typical: 25C
0.8
0.7
IPD (A)
0.6
0.5
0.4
Typical
0.3
0.2
0.1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-24:
35
Max.
Max: 85C + 3
M
3
Typical: 25C
30
IPD (A
A)
25
20
Typical
yp
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 382
PIC16(L)F1825/9
FIGURE 31-25:
18
16
Max.
14
12
IPD (A
A)
Typical
10
8
6
4
Max: 85C + 3
yp
Typical:
25C
2
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-26:
90
Max
Max.
80
Max: 85C + 3
Typical: 25C
70
IPD (A)
60
Typical
50
40
30
20
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 383
PIC16(L)F1825/9
FIGURE 31-27:
11
Max.
Max: 85C + 3
Typical: 25C
10
9
IPD (A)
8
7
Typical
6
5
4
18
1.8
2
0
2.0
2
2
2.2
2
4
2.4
2
6
2.6
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
VDD (V)
FIGURE 31-28:
40
Max.
Max: 85C + 3
Typical: 25C
35
30
25
IPD (A)
Typical
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 384
PIC16(L)F1825/9
FIGURE 31-29:
6.0
Max: 85C + 3
Typical: 25C
5.0
Max.
IPD (A
A)
4.0
3.0
Typical
2.0
1.0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-30:
35
30
Max.
IPD (A)
25
Typical
20
15
10
Max: 85C + 3
Typical: 25C
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 385
PIC16(L)F1825/9
FIGURE 31-31:
6
Max: 85C + 3
M
3
Typical: 25C
Max.
IPD (A
A)
4
Typical
yp
3
0
1
6
1.6
1
8
1.8
2
0
2.0
2
2
2.2
2
4
2.4
2
6
2.6
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
VDD (V)
FIGURE 31-32:
40
Max.
Max: 85C + 3
Typical: 25C
35
30
IPD (A
A)
25
Typical
yp
20
15
10
5
0
15
1.5
2
0
2.0
2
5
2.5
3
0
3.0
3
5
3.5
4
0
4.0
4
5
4.5
5
0
5.0
5
5
5.5
VDD (V)
DS40001440E-page 386
PIC16(L)F1825/9
FIGURE 31-33:
10
Max
Max.
Max: 85C + 3
Typical: 25C
9
8
7
Typical
IPD
D (A)
6
5
4
3
2
1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-34:
40
Max.
35
30
Typical
IPD (A
A)
25
20
15
10
Max: 85C + 3
yp
Typical:
25C
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 387
PIC16(L)F1825/9
FIGURE 31-35:
40
Max.
Max: 85C + 3
M
3
Typical: 25C
35
30
Typical
IPD (A
A)
25
20
15
10
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-36:
80
Max: 85C + 3
Typical: 25C
70
Max.
60
Typical
IPD (A
A)
50
40
30
20
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 388
PIC16(L)F1825/9
FIGURE 31-37:
10
9
Max.
8
7
IPD (A)
Typical
6
5
4
3
2
Max: 85C + 3
Typical: 25C
1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-38:
45
Max
Max.
40
35
IPD (A)
30
Typical
yp
25
20
15
10
Max: 85C + 3
yp
Typical:
25C
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 389
PIC16(L)F1825/9
FIGURE 31-39:
30
Max.
25
IPD (A
A)
20
Typical
15
10
Max: 85C + 3
Typical: 25C
0
16
1.6
1
8
1.8
2
0
2.0
2
2
2.2
2
4
2.4
2
6
2.6
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
VDD (V)
FIGURE 31-40:
60
Max.
50
40
IPD (A
A)
Typical
30
20
Max: 85C + 3
Typical: 25C
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001440E-page 390
PIC16(L)F1825/9
FIGURE 31-41:
6
Graph represents
3 Limits
VOH (V)
4
-40C
3
125C
Typical
0
-30
-25
-20
-15
-10
-5
IOH (mA)
FIGURE 31-42:
Graph represents
3 Limits
VOL (V)
3
-40C
2
Typical
125C
0
0
10
20
30
40
IOL (mA)
50
60
70
80
DS40001440E-page 391
PIC16(L)F1825/9
FIGURE 31-43:
3.5
Graph represents
3 Limits
3.0
VOH (V)
2.5
2.0
1.5
125C
Typical
1.0
-40C
0.5
0.0
-14
-12
-10
-8
-6
-4
-2
IOH (mA)
FIGURE 31-44:
3.0
Graph represents
3 Limits
2.5
VOL (V)
2.0
-40C
Typical
1.5
125C
1.0
0.5
0.0
0
10
15
20
25
30
IOL (mA)
DS40001440E-page 392
PIC16(L)F1825/9
FIGURE 31-45:
2.0
Graph represents
3 Limits
1.8
1.6
VOH (V)
1.4
1.2
125C
1.0
0.8
Typical
-40C
0.6
0.4
0.2
0.0
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
IOH (mA)
FIGURE 31-46:
1.8
Graph represents
3 Limits
1.6
1.4
VOL (V)
1.2
1.0
125C
Typical
0.8
-40C
0.6
0.4
0.2
0.0
0
10
IOL (mA)
DS40001440E-page 393
PIC16(L)F1825/9
FIGURE 31-47:
1.70
1.68
Max.
1.66
Voltage (V)
1.64
Typical
1.62
Min.
1.60
1.58
1.56
Max: Typical + 3
Typical: 25C
Min: Typical - 3
1.54
1.52
1.50
-40
-20
20
40
60
80
100
120
100
120
Temperature (C)
FIGURE 31-48:
1.54
Max: Typical + 3
Typical: 25C
Min: Typical - 3
1.52
1.50
Max.
Voltage (V)
1.48
1.46
1.44
Typical
1.42
1.40
Min.
1.38
1.36
1.34
-40
-20
20
40
60
80
Temperature (C)
DS40001440E-page 394
PIC16(L)F1825/9
FIGURE 31-49:
2.10
Max: Typical + 3
Min: Typical - 3
2.05
2.00
Voltage (V)
Max.
1.95
1.90
Min.
1.85
1.80
1.75
1.70
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
FIGURE 31-50:
70
Max.
60
Voltage (mV)
50
Typical
40
30
Min.
20
Max: Typical + 3
Typical: 25C
Min: Typical - 3
10
0
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
DS40001440E-page 395
PIC16(L)F1825/9
FIGURE 31-51:
2.90
2.85
Max: Typical + 3
Min: Typical - 3
2.80
Max.
Voltage (V)
2.75
2.70
2.65
Min.
2.60
2.55
2.50
2.45
2.40
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
DS40001440E-page 396
PIC16(L)F1825/9
FIGURE 31-52:
24
22
Max.
Time (mS)
20
18
Typical
16
14
Min.
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
12
10
1.5
2.5
3.5
4.5
5.5
Voltage (V)
FIGURE 31-53:
PWRT PERIOD
110
100
Max.
Time (mS)
90
80
Typical
70
Min.
60
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
50
40
1.5
2.5
3.5
4.5
5.5
Voltage (V)
DS40001440E-page 397
PIC16(L)F1825/9
FIGURE 31-54:
80
70
Max.
Hysteresis (mV)
60
Typical
50
40
Min.
30
20
Max: Typical + 3
Typical: 25C
Min: Typical - 3
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-55:
16
14
Max.
Hysteresis (mV)
12
Typical
10
8
Min.
6
4
Max: Typical + 3
Typical: 25C
Min: Typical - 3
2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001440E-page 398
PIC16(L)F1825/9
FIGURE 31-56:
350
300
Time (nS)
250
Max.
200
Typical
150
100
Max: Typical + 3
Typical: 25C
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-57:
400
Graph represents
3 Limits
350
Time (nS)
300
250
125C
200
150
Typical
100
-40C
50
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001440E-page 399
PIC16(L)F1825/9
FIGURE 31-58:
50
40
30
Max.
20
10
Typical
0
Min.
-10
-20
Max: Typical + 3
Typical: 25C
Min: Typical - 3
-30
-40
-50
0.0
1.0
2.0
3.0
4.0
5.0
DS40001440E-page 400
PIC16(L)F1825/9
32.0
DEVELOPMENT SUPPORT
32.1
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
DS40001440E-page 401
PIC16(L)F1825/9
32.2
MPLAB XC Compilers
32.3
MPASM Assembler
32.4
32.5
DS40001440E-page 402
PIC16(L)F1825/9
32.6
32.7
32.8
32.9
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineers PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming (ICSP).
DS40001440E-page 403
PIC16(L)F1825/9
32.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
DS40001440E-page 404
PIC16(L)F1825/9
33.0
PACKAGING INFORMATION
33.1
Example
PIC16LF1825
-E/P e3
1110017
Example
PIC16F1825
-E/SL e3
1110017
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40001440E-page 405
PIC16(L)F1825/9
33.1
Example
XXXXXXXX
YYWW
NNN
L1825EST
1110
017
PIN 1
Example
PIN 1
PIN 1
DS40001440E-page 406
PIC16
LF1825
E/ML e3
110017
Example
PIN 1
PIC16
LF1825
E/ML e3
110017
PIC16(L)F1825/9
33.1
Example
PIC16LF1829-E/P e3
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
1110017
Example
1110017
PIC16F1829
-E/SO e3
1110017
Example
PIC16LF1829
-E/SS e3
1110017
DS40001440E-page 407
PIC16(L)F1825/9
33.1
PIN 1
Example
PIN 1
PIC16
LF1829
E/ML e
110017
3
PIN 1
Example
PIN 1
PIC16
LF1829
E/ML e
110017
3
DS40001440E-page 408
PIC16(L)F1825/9
33.2
Package Details
3
%&
%! %4" ) ' %
4$%
%"%
%%255)))&
&54
NOTE 1
E1
D
E
A2
L
A1
b1
b
eB
6%
&
9&%
7!&(
$
7+8-
7
7:
;
%
%
%
<
<
""4
4
0
,
0
1 %
%
0
<
<
!" %
!" ="%
,
,0
""4="%
-
0
>
: 9%
,0
0
0
%
%
0
,
0
9" 4
>
0
(
0
?
>
1
<
<
6 9"="%
9
) 9"="%
:
)*
1+
,
!"#$%! & '(!%&! %(
%")%%%"
*$%+ % %
, &
"-"
%!"&
"$
% !
"$
% !
%#". "
&
"%
-/0
1+21 &
%#%!
))%
!%%
) +01
DS40001440E-page 409
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 410
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 411
PIC16(L)F1825/9
3
%&
%! %4" ) ' %
4$%
%"%
%%255)))&
&54
DS40001440E-page 412
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 413
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 414
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 415
PIC16(L)F1825/9
!
" #
$
%& ' (()* "#
3
%&
%! %4" ) ' %
4$%
%"%
%%255)))&
&54
D2
D
EXPOSED
PAD
e
E2
E
2
TOP VIEW
N
NOTE 1
BOTTOM VIEW
A3
A
A1
6%
&
9&%
7!&(
$
99-
-
7
7:
;
?
%
: 8%
>
%"
$$
0
+
%%
4
,
: ="%
-#
""="%
-
: 9%
-#
""9%
?01+
-3
1+
0
?0
>
1+
0
?0
+
%%="%
0
,
,0
+
%%9%
,
0
+
%%%
-#
""
V
<
!"#$%! & '(!%&! %(
%")%%%"
4 ) !%"
, &
"%
-/0
1+2 1 &
%#%!
))%
!%%
-32 $ &
'! !)%
!%%
'$
$
&%
!
>
<
) +1
DS40001440E-page 416
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 417
PIC16(L)F1825/9
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
SEATING
PLANE
A1
0.10 C
C
A
16X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
0.10
C A B
E2
2
e
2
NOTE 1
K
16X b
0.10
L
e
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-257A Sheet 1 of 2
DS40001440E-page 418
PIC16(L)F1825/9
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.45
0.00
2.50
2.50
0.25
0.30
0.20
MILLIMETERS
NOM
16
0.65 BSC
0.50
0.02
0.127 REF
4.00 BSC
2.60
4.00 BSC
2.60
0.30
0.40
-
MAX
0.55
0.05
2.70
2.70
0.35
0.50
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-257A Sheet 2 of 2
DS40001440E-page 419
PIC16(L)F1825/9
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body
[UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
16
1
2
C2 Y2
Y1
X1
E
SILK SCREEN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X16)
X1
Contact Pad Length (X16)
Y1
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
2.70
2.70
4.00
4.00
0.35
0.80
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2257A
DS40001440E-page 420
PIC16(L)F1825/9
+
3
%&
%! %4" ) ' %
4$%
%"%
%%255)))&
&54
E1
NOTE 1
3
D
E
A2
A1
b1
b
eB
e
6%
&
9&%
7!&(
$
7+8-
7
7:
;
%
%
%
<
<
""4
4
0
,
0
1 %
%
0
<
<
!" %
!" ="%
,
,
,0
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-
0
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: 9%
>
,
?
%
%
0
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0
9" 4
>
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(
0
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>
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9
) 9"="%
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%")%%%"
*$%+ % %
, &
"-"
%!"&
"$
% !
"$
% !
%#". "
&
"%
-/0
1+2 1 &
%#%!
))%
!%%
) +1
DS40001440E-page 421
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 422
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 423
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 424
PIC16(L)F1825/9
+
,-.% , /
,, 0) ,,/
3
%&
%! %4" ) ' %
4$%
%"%
%%255)))&
&54
D
N
E
E1
NOTE 1
1 2
e
b
c
A2
A1
L1
6%
&
9&%
7!&(
$
L
99-
-
7
7:
;
%
: 8%
<
?01+
<
""4
4
?0
0
>0
%"
$$
0
<
<
: ="%
>
>
""4="%
-
0
0,
0?
: 9%
?
0
%9%
00
0
0
% %
9
0-3
9" 4
<
%
W
W
0
>W
9"="%
<
,>
!"#$%! & '(!%&! %(
%")%%%"
&
"-"
%!"&
"$
% !
"$
% !
%#"&& "
, &
"%
-/0
1+2 1 &
%#%!
))%
!%%
-32 $ &
'! !)%
!%%
'$
$
&%
!
) +1
DS40001440E-page 425
PIC16(L)F1825/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001440E-page 426
PIC16(L)F1825/9
+
" #
$
%& ' (()* "#
3
%&
%! %4" ) ' %
4$%
%"%
%%255)))&
&54
D2
EXPOSED
PAD
e
E2
2
E
b
1
K
N
N
NOTE 1
TOP VIEW
BOTTOM VIEW
A
A1
A3
6%
&
9&%
7!&(
$
99-
-
7
7:
;
%
: 8%
>
%"
$$
0
+
%%
4
,
: ="%
-#
""="%
-
: 9%
-#
""9%
01+
-3
1+
?
>
1+
?
>
+
%%="%
>
0
,
+
%%9%
,
0
+
%%%
-#
""
<
<
!"#$%! & '(!%&! %(
%")%%%"
4 ) !%"
, &
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-/0
1+2 1 &
%#%!
))%
!%%
-32 $ &
'! !)%
!%%
'$
$
&%
!
) +?1
DS40001440E-page 427
PIC16(L)F1825/9
3
%&
%! %4" ) ' %
4$%
%"%
%%255)))&
&54
DS40001440E-page 428
PIC16(L)F1825/9
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
SEATING
PLANE
A1
0.10 C
C
A
20X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
0.10
C A B
E2
2
NOTE 1
20X b
0.10
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-255A Sheet 1 of 2
DS40001440E-page 429
PIC16(L)F1825/9
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
Overall Length
D
D2
Exposed Pad Length
Terminal Width
b
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.45
0.00
2.60
2.60
0.20
0.30
0.20
MILLIMETERS
NOM
20
0.50 BSC
0.50
0.02
0.127 REF
4.00 BSC
2.70
4.00 BSC
2.70
0.25
0.40
-
MAX
0.55
0.05
2.80
2.80
0.30
0.50
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-255A Sheet 2 of 2
DS40001440E-page 430
PIC16(L)F1825/9
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
20
1
2
C2 Y2
G1
Y1
X1
E
SILK SCREEN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X20)
X1
Contact Pad Length (X20)
Y1
Contact Pad to Center Pad (X20)
G1
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
2.80
2.80
4.00
4.00
0.30
0.80
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2255A
DS40001440E-page 431
PIC16(L)F1825/9
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (08/2010)
Original release.
Revision B (05/2011)
Revised Electrical Specifications.
Revision C (06/2012)
Updated the Family Types table; Updated Figures 1, 2
and 3; Updated Table 3-3; Changed all instances of
SDO into SDO1, SDOSEL into SDO1SEL and SSSEL
into SS1SEL; Added PIR3, PIR4, PIE3 and PIE4 to
Table 3-3; Updated Register 4-2; Updated Sections
5.2.2.5 and 5.5.3; Added Note 1 to Table 11-3; Updated
Figure 13-1 and Equation 16-1; Updated Section 19.9;
Added charts to the DC and AC Characteristics Graphs
section; Revised the Electrical Specifications section;
Updated the Packaging Information section; Updated
the Product Identification System section; Other minor
corrections.
Revision D (05/2014)
Added new UQFN packages: 16-Lead, UQFN,
4x4x0.5, (JQ) and 20-Lead, UQFN, 4x4x0.5, (GZ)
packages. Minor corrections.
Revision E (4/2015)
APPENDIX B:
MIGRATING FROM
OTHER PIC
DEVICES
B.1
PIC16F648A to PIC16F1825/9
TABLE B-1:
FEATURE COMPARISON
Feature
PIC16F648A
PIC16F1825/9
Max. Operating
Speed
20 MHz
32 MHz
Max. Program
Memory (Words)
4K
8K
256
1024
Max. EEPROM
(Bytes)
256
256
A/D Resolution
10-bit
10-bit
Timers (8/16-bit)
2/1
4/1
Brown-out Reset
Internal Pull-ups
RB<7:0>
PIC16F1825:
RA<5:0>, RC<5:0>
PIC16F1829:
RA<5:0>, RB<7:4>,
RC<7:0>
Interrupt-on-change
RB<7:4>
PIC16F1825:
RA<5:0>, Edge
Selectable
PIC16F1829:
RA<5:0>, RB<7:4>,
Edge Selectable
Comparator
AUSART/EUSART
2
0/1
Extended WDT
Software Control
Option of WDT/BOR
48 kHz or
4 MHz
31 kHz - 32 MHz
INTOSC
Frequencies
Clock Switching
Capacitive Sensing
2/0
2/2
MSSPx/SSPx
2/0
Reference Clock
Data Signal
Modulator
SR Latch
Voltage Reference
DAC
CCP/ECCP
Enhanced PIC16
CPU
DS40001440E-page 432
2
1/0
PIC16(L)F1825/9
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://www.microchip.com/support
DS40001440E-page 433
PIC16(L)F1825/1829
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
[X]
/XX
XXX
Temperature
Range
Package
Pattern
PIC16F1825, PIC16LF1825
PIC16F1829T, PIC16LF1829
Temperature
Range:
I
E
Package:(2)
GZ
JQ
ML
P
SL
SO
SS
ST
Pattern:
=
=
=
=
=
=
=
=
b)
(Industrial)
(Extended)
DS40001440E-page 434
a)
c)
Device:
= -40C to +85C
= -40C to +125C
Examples:
Note 1:
2:
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
2010-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-254-1
== ISO/TS 16949 ==
2010-2015 Microchip Technology Inc.
DS40001440E-page 435
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
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