Tutorial for Design Compiler

Design Compiler:
The process that Design Compiler does is RTL synthesis. This means, converting a gate level logic Verilog
file to transistor level Verilog with the help of Technology library provided by the foundry.

How to use the Tool:

1. Source the file from the folder where bash file is present: $ source .bashrc.cadence
Note:
Download .bashrc.cadence file from http://aimlab.seas.wustl.edu/courses/.bashrc.cadence :
Create an empty file in your home directory.
Copy the content from above link
Paste it to the empty file you created
Rename the empty file to .bashrc.cadence
2. Make your Verilog model files ready
Write your logic gate level Verilog code
Conduct a brief verification (by testing all possible cases writing a test bench and
verifying the behavior of model files) using tools like vcs.
3. Writing constraints file - .tcl file
Command lines where modifications are required specific to model
Set Path to Verilog files
Top module of the design have to be specified (To specify the Hierarchy)
Specifying the clock port used in the model
Clock frequency at which the model is operated
Input Delay: Models delay from source to design input port (Use if needed)
Output Delay: Models delay from design output port to signal destination
Command lines where modifications are not required
Set paths to the Technology library files (Use Default path)
Commands to Analyze, Elaborate and Compile
Specifying the name to Report files for Area, Timing and Power
Note: Please go through the provided .tcl file provided to check other options which are available below
.tcl Code Link: https://wustl.box.com/compiledctcl

4. Technology Library
Files provided by the vendor (db and sdb files) comes in a PDK package.
Design compiler will map the cells in the design to available standard cells.
Using the dc_shell tool:

Make sure you have all the files (Verilog or VHDL and constraints file) in the same folder.
(recommended not compulsory)
The .tcl file you created has the sequence of commands which are used in dc_shell (Design
Compiler) to synthesize your model.
Run the script using the following command $dc_shell-t -f compiledc.tcl

Most common modifications in the script needed are the following:

Set your Verilog files. If multiple separate them by a space. (eg: [list verilog1.v verilog2.v ])

Set the top module in the design. If design is hierarchical you should mention the name of top module.

Set the operation frequency of the module. 50000ps = 20 MHz

Set clock to your model by giving the name of port to the clock created in design compiler.
Reading report file:
Timing Analysis:
Make sure the timing report requirements are MET. Also you can observe which module in the design is
giving the maximum delay and optimize accordingly.
Example:

Power Analysis:
Design Compiler gives the detailed information about the static and dynamic power.
Example:

Area Analysis:
Area report file generated using design compiler contains detail information about the size of each cell
used for this model. Units for Virginia tech library are micro meters.
Example:

Design Analysis:
Important information found in this report is the operating conditions. VT library only support normal
conditions for operation. But in technology libraries provided by the vendor there are some extreme
conditions (WCCO worst case conditions) available for getting the maximum values to verify the
performance of the model.
Example: