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From Wikipedia, the free encyclopedia
The PIC instruction set refers to the set of instructions that a Microchip Techn
ology PIC or dsPIC microcontroller supports. The instructions are usually progra
mmed into the Flash memory of the processor, and automatically executed by the m
icrocontroller on startup.
PICmicro chips have a Harvard architecture, and instruction words are unusual si
zes. Originally, 12-bit instructions included 5 address bits to specify the memo
ry operand, and 9-bit branch destinations. Later revisions added opcode bits, al
lowing additional address bits.
Memory operands are also referred to as "registers". Most are simply general-pur
pose storage (RAM), while some locations are reserved for special function regis
ters. Except for a single accumulator (called W), almost all other registers are
memory-mapped, even registers like the program counter and ALU status register.
(The other exceptions, which are not memory-mapped, are the return address stac
k, and the tri-state registers used to configure the GPIO pins.)
The instruction set does not contain conditional branch instructions. Instead, i
t contains conditional skip instructions which cause the following instruction t
o be ignored. A conditional skip followed by an unconditional branch performs a
conditional branch. The skip instructions test any bit of any register. The ALU
status register is one possibility.
Memory operands are specified by absolute address; the location is fixed at comp
ile time. To provide indirect addressing, a pair of special function registers a
re provided:
The file select register (FSR) is written with the address of the desired memory
operand, after which
The indirect file register (INDF) becomes an alias for the operand pointed to by
the FSR.
This mechanism also allows up to 256 bytes of memory to be addressed, even when
the instruction set only allows 5- or 7-bit memory operands. Models with more re
gisters (special function registers plus RAM) than fit into the instruction prov
ide multiple banks of memory, and use one of two mechanisms for accessing them:
Most baseline core devices, and some mid-range core devices, use the high-order
bits of the file select register to select the current register bank.
More recent models have a separate bank select register, and a MOVLB instruction
to set it.
PIC processors with more than 256 words of program use paged memory. The interna
l program counter and return stack are as wide as necessary to address all memor
y, but only the low 8 bits are visible to software in the PCL ("PC low") registe
r. There is an additional PCLATH ("PC latch high") register which is only modifi
ed by software. Any operation which does not specify the full destination addres
s (such as a 9-bit GOTO or an 8-bit write to the PC register) fills in the addit
ional high bits from the corresponding part of PCLATH. (Some PIC18 processors ex
tend this beyond 16 bits with a PCLATU register to supply bits 16 23.)
In the instruction set tables that follow, register numbers are referred to as "
f", while constants are referred to as "k". Bit numbers (0 7) are selected by "b".
The "d" bit selects the destination: 0 indicates W, while 1 indicates that the

result is written back to source register f. The C and Z status flags may be set
based on the result; otherwise they are unmodified. Add and subtract (but not r
otate) instructions that set C also set the DC (digit carry) flag, the carry fro
m bit 3 to bit 4, which is useful for BCD arithmetic.
Contents [hide]
1
Baseline core devices (12 bit)
2
ELAN Microelectronics clones (13 bit)
3
Mid-range core devices (14 bit)
4
Enhanced mid-range core devices (14 bit)
5
PIC18 high end core devices (16 bit)
6
PIC24 and dsPIC 16-bit microcontrollers
7
References
Baseline core devices (12 bit)[edit]
12-bit PIC instruction set
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Mnemonic
C
?
Z
?
Description
0
0
0
0
0
0
0
opcode Miscellaneous in
structions
0
0
0
0
0
0
0
0
0
0
0
0
NOP
No operation (MOVW 0,W)
0
0
0
0
0
0
0
0
0
0
1
0
OPTION
Copy W to OPTION register
0
0
0
0
0
0
0
0
0
0
1
1
SLEEP
Go into standby mode
0
0
0
0
0
0
0
0
0
1
0
0
CLRWDT
Restart watchdog timer
0
0
0
0
0
0
0
0
0
1
f
TRIS f
Copy W to tri-state register (f = 1, 2 or 3)
0
0
0
0
0
0
0
1
0
k
MOVLB k*
Set bank select register to k
0
0
0
0
0
0
0
1
1
1
Return from subroutine, W unmodified
1
0
RETURN
0
0
0
0
0
0
0
1
1
1
1
1
RETFIE
Return from interrupt; return & enable i
nterrupts
0
0
opcode d
register
ALU operations: dest ? OP(f,W)
0
0
0
0
0
0
1
f
MOVWF f
dest ? W
0
0
0
0
0
1
d
f
CLR f,d
Z
dest ? 0, usually written CLRW or CLRF f
0
0
0
0
1
0
d
f
SUBWF f,d
C
Z
dest ? f-W (dest ? f+~W+1)
0
0
0
0
1
1
d
f
DECF f,d
Z
dest ? f-1
0
0
0
1
0
0
d
f
IORWF f,d
Z
dest ? f | W, logical inclusive or

0
0
0
1
0
1
d
f
ANDWF f,d
Z
dest ? f & W, logical and
0
0
0
1
1
0
d
f
XORWF f,d
Z
dest ? f ^ W, logical exclusive or
0
0
0
1
1
1
d
f
ADDWF f,d
C
Z
dest ? f+W
0
0
1
0
0
0
d
f
MOVF f,d
Z
dest ? f
0
0
1
0
0
1
d
f
COMF f,d
Z
dest ? ~f, bitwise complement
0
0
1
0
1
0
d
f
INCF f,d
Z
dest ? f+1
0
0
1
0
1
1
d
f
DECFSZ f,d
dest ? f-1, then skip if zero
0
0
1
1
0
0
d
f
RRF f,d C
dest ? CARRY<<7 | f>>1, rotate right through carry
0
0
1
1
0
1
d
f
RLF f,d C
dest ? F<<1 | CARRY, rotate left through carry
0
0
1
1
1
0
d
f
SWAPF f,d
dest ? f<<4 | f>>4, swap nibbles
0
0
1
1
1
1
d
f
INCFSZ f,d
dest ? f+1, then skip if zero
0
1
opc
bit
register
Bit operations
0
1
0
0
bit
f
BCF f,b
Clear bi
t b of f
0
1
0
1
bit
f
BSF f,b
Set bit
b of f
0
1
1
0
bit
f
BTFSC f,b
Skip if bit b of f is clear
0
1
1
1
bit
f
BTFSS f,b
Skip if bit b of f is set
1
0
opc
k
Control transfers
1
0
0
0
k
RETLW k
Set W ? k, then
return from subroutine
1
0
0
1
k
CALL k
Call subroutine,
8-bit address k
1
0
1
k
GOTO k
Jump to 9-bit address k[
1]
1
1
opc
8-bit immediate Operations with W and 8-bit literal: W ?
OP(k,W)
1
1
0
0
k
MOVLW k
W ? k
1
1
0
1
k
IORLW k
Z
W ? k | W, bitwi
se logical or
1
1
1
0
k
ANDLW k
Z
W ? k & W, bitwi
se and
1
1
1
1
k
XORLW k
Z
W ? k ^ W, bitwi
se exclusive or
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Mnemonic
C

?
Z
?
Description
*: Extended instruction, not available on most 12-bit PICs. Of the models with e
xtended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using th
e high-order bits of the FSR. A few (e.g. PIC12F529T39A) have a separate bank se
lect register which can be set with this instruction.
: Extended instruction, only available on "enhanced baseline" PICs. Only the very
few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack
) include these instructions. All such models also include MOVLB.
ELAN Microelectronics clones (13 bit)[edit]
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