Part - 2

Introduction to ARCHITECTURE of
Fixed point DSPs (TMS320C54X series)

KEY FEATURES OF DSPs - TMS320C54X Processor

Bit size of the processor: What do you infer from the bit size?
I - 16-bit fixed point DSP

1. The instruction word (IW) - 16-bits (IW opcode combined with operand)
The size of Program bus (PB)

16 bits

Program data bus (PDB)

16 bits

Program address bus (PAB)

Normally 16 bits (but it can be more)

The program word size can be greater than 16-bits

e.g. large instruction word (32-64 bits), VLIW very large instruction

word (256 bits)

2. Data word (DW)/data size

16 bits

The size of Data bus (DB)

16 bits

Data data bus (DDB)

16 bits

Data address bus (DAB)

Normally 16 bits (but it can be more)

The data word size can never greater than 16-bits

Key features of TMS320C54X Processor contd..

3. The internal processing size ?

CPU size (specific ALU size)

In conventional Ps and Cs the size of the internal processing or
size of CPU is same as the bit size of the processor.
In DSPs the size internal processing or size of the CPU is never
the same as the bit size of the processor, It will be twice or more
than twice the bit size. Very important concept to be remembered
Data from
memory (DM)

Data from
memory (DM)

Data from
Memory (DM)

16

16

Data from
memory(DM)
16

16
32

CPU/
ALU
(16-bits)
16
Result to Data
memory

16

ALU (16)
16

CPU/ALU
(>16-bits)
(32,40,64-bits)

Result to Data
memory

ALU of Ps and Cs

32

Accumulator (32)
ACCH (16)

Accumulator (16)
16

ALU (32)

16
Result to Data
memory

ACCL(16)

16

Result to Data
memory

ALU of DSPs

Why it is so? What are the benefits due to increased processing size?

Key features of TMS320C54X Processor contd..

CPU of the processor?

II 40 bit CPU (The size of CPU is greater than twice or more than twice
the bit size of the processor)
1. ALU - Same as CPU size - In `C54X, 40-bit CPU Size of ALU is 40 bits.
(DSPs have more than one ALU units multiple ALU units)
2. Accumulator - The size of Accumulator is same as the ALU size. The
number of accumulators in DSPs is more than one. In `C54X there are two
accumulators A and B each of 40 bit size.
3. Multiplier/MAC - DSPs should have Multiplier/multiply and accumulate
unit (MAC). The size of the multiplier/MAC unit in DSPs is same as bit size
of the processor.
In `54X 17x17 bit multiplier with a 40 bit adder (MAC unit)
5. Barrel shift register Shift left and shift right any number of bits in one
clock cycle.
6. Auxiliary register unit (ARUs) Only DSPs have ARUs. One are two ARUs
with 8 Auxiliary register ARs (AR0-AR7). In `C54X Two ARUs

Key features of TMS320C54X Processor contd..

II Memory and Bus architecture
1. Memory space - `C54X 16 bit processor, 16 bit address lines
216 - 64 K words (64K x 16 bits) of memory size.
64K words of Program memory (PM), 64K words of Data Memory (DM)
& 64K words of I/O memory (IOM).Total addressable space 192K words
2. Extended Memory space - Program Memory extended up 23 address lines
8 M word of PM space
3. Memory type - DSPs have on-chip ROM, RAM and cache
ROM for program and data space
RAM Single Access RAM (SARAM), Dual Access RAM (DARAM) for
program and data space
Cache Program cache and Data cache.
4. Bus architecture Advanced Modified Harvard architecture in `C54X
Harvard architecture 1PB (PAB&PDB), 1DB (DAB & DDB)
Modified Harvard architecture 1 PB, 1 DB ( 2 DAB & DDB)
Advanced modified Harvard 1 PB, 3DB (2 for Read & 1 for write) - `C54X

Key features of TMS320C54X Processor contd..

III Other details

1. Technology - Fabricated in CMOS technology
2. Base architecture - The architecture design is based on TMS320C50
3. Source compatibility - Compatibility with `C5X, `C2XX DSPs
4. The `C54X generation - Consists of `541, `C542, `C543, `C545, `C546,
`C548, `C549, `C5402, `C5410, `C5416 and `C5420 DSPs

(Architecture is same for all the processors and the difference is in

on-chip memory)
5. Speed - Execute up to 200 MIPS (Million Instructions Per Second)
6. Power - Reduced power consumption, two operating voltages 5V and
3.3V and power down modes.
7. Application specific hardware and instructions
Two application Specific units
CSSU (Compare Select and Store Unit) and Exponent encoder
On-chip peripherals and highly specialized instruction set
(Ex. MAC, MACD and FIRS)

Major Blocks
1.
2.
3.
4.

CPU
On-chip Memory
Internal Buses
On-chip Peripherals

1.

Arithmetic and Logic Unit (ALU)

2.

Multiplier/Multiplier with adder (MAC)

3.

Barrel Shift Registers

4.

Auxiliary Register Arithmetic Unit (ARAU)

5.

Memory Mapped Registers (MMREGS)

6.

Parallel Logic Unit (PLU)

7.

Control Unit

8.

CSSU and Exponent encoder

CPU

Design of ALU unit

Design specifications
i)

Bit size

ii)

Number of buses

iii) Number of Accumulators

i) Bit size Depends on the CPU size
ii) Number of buses Input and output buses
1) Input bus Depends on Data memory
Depends on the RAM
SARAM input bus 1
DARAM input bus 2
2) Input bus Program memory SARAM only input bus - 1
3) Output bus - 1
iii) Number of Accumulators one or more than one

Design of ALU unit (Ps and Cs)

Design specifications
i) Bit size - 16 bit ii) Number of buses - 1 (DB) iii) Number of Accumulators - 1

Points to be remembered for the design

Data from
memory(DM)

Size of CPU/ALU is same as bit size

16

of the processor.
16

ALU (16)
16
Accumulator (16)
16
Result to Data
memory

The size of Accumulator is same

as ALU size.
All the buses in ALU are same
as ALU size.
Instruction ADD src ; ST dst

Design of ALU unit (DSPs) Case-1

Design specifications Single operand ALU DM only
i) Bit size - 16 bit (ALU size > 16 bits) ii) Number of buses - 1 (DB)
iii) Number of Accumulators - 1
Data from
memory (DM)
16

32

ALU (32)
32
Accumulator (32)
ACCH (16) ACCL(16)

16

16
16 line 2:1
Multiplexer

16
Result to Data
memory

Points to be remembered for the design

Size of CPU/ALU is greater than bit size
of the processor (e.g. - 32 bits).
The size of Accumulator is same
as ALU size.
All the buses in ALU are same
as ALU size but more than bit size of the
processor
Single Operand ALU

Instruction ADD *ar2

STL *ar3 , STH *ar4

10

Design of ALU unit (DSPs) Case-2

Design specifications Dual operand ALU DM only
i) Bit size - 16 bit (ALU size > 16 bits) ii) Number of buses - 2 (DB1 & DB2)
iii) Number of Accumulators - 1
Data from (DM)
(DB2)

16

32

Data from (DM)

(DB1)

16

32

32

ALU (32)
32
Accumulator (32)
ACCH (16) ACCL(16)

16

16
16 line 2:1
Multiplexer

16
Result to Data
memory

32 line 2:1
Multiplexer

Points to be remembered for the design

Size of CPU/ALU is greater than bit size
of the processor (e.g. 32-bits).
The size of Accumulator is same
as ALU size.
All the buses in ALU are same
as ALU size but more than bit size of
the processor
Dual operand ALU
It should support single operand as
default
Dual operand is an additional feature
Instruction ADD *ar2, *ar3
STL *ar4, STH *ar5

11

Design of ALU unit (DSPs) Case-3

Design specifications Single operand ALU DM and PM
i) Bit size - 16 bit (ALU size > 16 bits) ii) Number of buses - 1 (DB) & 1 (PB)
iii) Number of Accumulators - 1
Points to be remembered for the design
Data
From (DM)
(DB1)

16 line 2:1
Multiplexer

Size of CPU/ALU is greater than bit size

16
of the processor (e.g. 32-bits).
The size of Accumulator is same
as ALU size.
16
All the buses in ALU are same
as ALU size but more than bit size of
32
the processor
ALU (32)
32
Single operand ALU
It should support single operand from
Accumulator (32)
ACCH (16) ACCL(16)
data memory as default
16
16
The data from program memory is only
16 line 2:1
for immediate addressing mode and it is
Multiplexer
an additional feature
16
Instruction ADD *ar2 & ADD #10h
Result to Data
memory
STL *ar3, STH *ar4
Data from
Program memory
(PM)
16

12

Design of ALU unit (DSPs) Case-4

Design specifications Single
operand ALU DM only- 2ACCU

B(32)
A(32)
Data from
memory(DM)

16

i) Bit size - 16 bit (ALU size > 16 bits)

ii) Number of buses - 1 (DB)
iii) Number of Accumulators - 2

32
32 line 2:1
Multiplexer

32

ALU (32)
32

ACCU- A (32)

ACCU- B (32)
BH (16)

32 line 1:2
De-Multiplexer

AH (16)

AL(16)

16

16

BL(16)
16

16
16 line 2:1

16

16 Multiplexer

16 line 2:1
Multiplexer

16
16
16 line 2:1

16 Multiplexer
Result to Data
memory

32

Points to be remembered for the design

Size of CPU/ALU is greater than bit
size of the processor (e.g. - 32 bits).
The size of Accumulator is same
as ALU size.
All the buses in ALU are same as ALU
size but more than bit size of the
processor
Single Operand ALU
The destination register to be
specified in the instruction
Instruction ADD *ar2,A ; ADD *ar2,B
STL A,*ar3 ; STH A,*ar4
STL B,*ar3 ; STH B,*ar4

13

Design of ALU unit (DSPs) Case-5

Design specifications Dual operand ALU 2 operand from DM and one from PM 2ACCU
i) Bit size - 16 bit (ALU size > 16 bits)
ii) Number of buses - 2 (DB1 & DB2) ; 1 (PB)
iii) Number of Accumulators - 2

Design of ALU unit (DSPs) Case-6

Design specifications - Dual operand ALU 2 operand from DM and one from PM 4 ACCU
i) Bit size - 16 bit (ALU size > 16 bits)
ii) Number of buses - 2 (DB1 & DB2) ; 1 (PB)
iii) Number of Accumulators - 4
For Accumulators more than 4, Register file concept used

14

Design of Multiplier unit (Only in DSPs) Case 1

Design specifications Single operand multiplier DM only
i)

Bit size - 16 bit ii) Number of buses - 1 (DB)

Multiplier

Multiplicand

16

Points to be remembered for the design

16

Size of multiplier is same as bit size of

Multiplier
16 x 16 bits

32
Product
Data from memory
16
16 line 1:2
De-Multiplexer

16
16

TREG
16

Multiplier
16 x 16 bits
32
Product Register
(PREG) (32)

the processor 16 x 16 bits.

For multiplication two operands are
needed - multiplicand and multiplier
At the same time two operands can not
be obtained from memory
One after the other it is read from
memory
First operand stored in temporary
register (TREG)
Second operand obtained from memory
and multiplied, result stored in product register
(PREG)
Single Operand multiplier
Instruction LD *ar2, T
MPY *ar3

15

Design of Multiplier unit (Only in DSPs) Case 2

16

Design specifications Dual operand multiplier DM only

i)

Bit size - 16 bit ii) Number of buses - 2 (DB1 & DB2)

Points to be remembered for the design

Size of multiplier is same as bit size of

Data from DM
(DB)
16

Data from DM
(DB1)

16 line 1:2
De-Multiplexer

16

16
16

TREG
16
16 line 2:1
Multiplexer

16
16

Multiplier
16 x 16 bits
32
Product Register
(PREG) (32)

Data from
DM (DB2)
16
16 line 2:1
Multiplexer

the processor 16 x 16 bits.

For multiplication two operands are
needed - multiplicand and multiplier
Dual operand multiplier should support
single operand multiply. Dual operand
multiply is an additional feature1
At the same time two operands can be
obtained from memory through DB1
and DB2
Temporary register (TREG) is bypassed
Both operands multiplied, result stored
in product register (PREG)
Dual Operand multiplier
Instruction MPY *ar2,*ar3

Design of Multiplier unit (Only in DSPs) Case 3

17

Design specifications Single operand multiplier DM & PM

i)

Bit size - 16 bit ii) Number of buses - 1 (DB & PB)

Points to be remembered for the design

Data from
Program Memory
(PM)

Data from
(DM)

16

16 line 2:1
Multiplexer

16

16
16 line 1:2
De-Multiplexer

16
16

TREG
16

Multiplier
16 x 16 bits
32

Product Register
(PREG) (32)

Size of multiplier is same as bit size of the processor

16 x 16 bits.
For multiplication two operands are needed multiplicand and multiplier
At the same time two operands can not be obtained
from memory, One after the other it is read from
memory
First operand stored in temporary register (TREG)
Second operand obtained from memory and multiplied,
result stored in product register (PREG)
Single Operand multiplier
It should support single operand from data memory as
default
The data from program memory is only for immediate
addressing mode and it is an additional feature
Instruction LD *ar2,T; MPY *ar3
LD #10h,T ; MPY #20h,T (Immediate addressing mode)

Design of Multiplier unit (Only in DSPs) Case-4

18

Design specifications Dual operand Multiplier 2 operand from DM and one from PM
i) Bit size - 16 bit (ALU size > 16 bits)
ii) Number of buses - 2 (DB1 & DB2) ; 1 (PB)

Design of Multiply and Accumulate unit (MAC) (Only in DSPs)

Some DSPs have multiplier & ALU and some have independent
Multiply and accumulate unit (MAC) & ALU
In DSPs having multiplier unit, the MAC operation is done by
combined use of multiplier and ALU. The product after
multiplication is sent to ALU unit for accumulation
In DSPs having independent MAC unit, it has multiplier and an
independent adder for accumulation. The MAC unit will not use
ALU for MAC operations. MAC and ALU operations can be done
at the same time.

Design of MAC unit (Only in DSPs) Case 1

Design specifications Multiplier and ALU
i)

Bit size - 16 bit ii) Number of buses - 1 (DB)

PREG (32)

Data from
memory

40
Data from
memory

16
16 line 1:2
De-Multiplexer

40 line 2:1
Multiplexer

16

40

40

16

ALU (40)
16

40

TREG
Accumulator (40)
16

Guard (8) ACCH (16) ACCL(16)

Multiplier
16 x 16 bits
32
Product Register
(PREG) (32)
32

16

16

16

Result to Data
memory

16 line 2:1
Multiplexer

Points to be remembered
for the design
Size of multiplier is same as bit
size of the processor 16 x 16
bits.
The product is 32 bits, the ALU
size should be more than the
product
MAC instruction uses multiplier
followed by ALU
The product is accumulated in
ALU
Single Operand multiplier and
ALU

19

Design of MAC unit (Only in DSPs) Case 2

20

Design specifications Independent MAC and ALU

i)

Bit size - 16 bit ii) Number of buses - 1 (DB)

Data from
memory

Data from
(DM)

16

Points to be remembered for the design

16
16 line 1:2
De-Multiplexer

32

16

ALU (32)
16
32

TREG

Accumulator (32)

16

ACCH (16) ACCL(16)

Multiplier
16 x 16 bits

16

16
16 line 2:1
Multiplexer

40

32

16

Adder (40)
40

40

Result to Data
memory

ALU unit
Regiter1 (40)
40

MAC unit
MAC output

Size of multiplier is same as bit size of

the processor 16 x 16 bits.

The ALU size should be more than the
bit size of the processor
MAC unit has independent adder
The size of the adder should be more the
product size
MAC instruction uses independent MAC
unit
The product is accumulated in the adder
Single Operand MAC and ALU
MAC operation and ALU operation
can be done at the same time

Example of Multiplier and ALU unit TMS320C5x

Multiplier unit

ALU unit

21

Example of MAC unit and ALU unit TMS320C54x

ALU unit

MAC unit

22

Barrel shift register TMS320C54x

23

40 bit barrel shifter

It can perform left and right shifts
in one clock cycle irrespective of
the number of bits.
The barrel shifter is used for
scaling operations such as:
Pre-scaling an input data-memory
operand or the accumulator
value before an ALU operation
Performing a logical or arithmetic
shift of the accumulator value
Normalizing the accumulator
Post-scaling the accumulator
before storing the accumulator
value into data memory

Auxiliary Register Arithmetic Unit (ARU/ARAU)

Data memory address processing unit/ Address generation unit
Dedicated Unit for Indirect Addressing
Mode of Operation only
Arithmetic Unit 16-bits - Two units
ARU0 and ARU1
Auxiliary Registers (ARs) 8 Registers
(AR0-AR7) 16-bits
Index Register AR0 or separate Index

Registers (INDX)
Circular Buffer one
ARU can process only the address of

data memory Never it can process

data
ARU is also used as event counter

24

Memory Mapped Registers (MMREGS)

25

Meaning Registers mapped to

Memory.
Which registers? CPU and
Peripheral registers.
Which memory? Data Memory.

CPU and Peripheral registers are

mapped to the first page of the
DATA Memory is called MMREGS.
Data memory READ and WRITE
instructions are enough to
access these MMREGS.
Hence, Reduces the instruction
set size.

Parallel Logic Unit (PLU)

The parallel logic unit (PLU) can directly
set, clear, test, or toggle single or
multiple bits in a control/status register
or any data memory location.

The PLU provides a direct logic

operation path to data memory values

without affecting the contents

of the ACC or the PREG

26

Assignment 1 Question Weightage 5 Marks

27

1. Get the data sheet of any one processor of your choice.

2. It could be a microprocessor or a microcontroller or a DSP from
any family of processors. eg. P 8086,8087 Pentium etc. ;
C 8051, ARM etc; DSPs TI, ADSP etc
3. The processor selected by each one should be different.
4. No ones choice of processor should be the same.
a) Write the KEY features of the processor such as PM, DM
size, ALU/Multiplier, MAC etc.
b) Draw the diagram of the ALU, Multiplier/MAC units present in
that processor.
c) Finally find the category of ALU, Multiplier/MAC
eg. Single operand DM/PM, Dual operand etc.
5. Along with the assignment, submit the print copy of first 2 pages
of data sheet of the processor.

28

End of Part-2