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    Field Effect Transistor Summary - a type of transistor commonly used for weak-signal amplification

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    Field Effect Transistor Summary - a type of transistor commonly used for weak-signal amplification

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    © All Rights Reserved
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    10 views17 pages

    FET's

    Uploaded by

    Kit Jason Monje
    Field Effect Transistor Summary - a type of transistor commonly used for weak-signal amplification

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    © All Rights Reserved
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    LECTURE 1: IELD EFFECT TRANSISTORS The field effect transistor, FET, is an extremely high input impedance device. It is often a low-noise device. There are two types of FET's. The JFET, or dunction FET, involves a gate electrode separated from the other two electrodes by a p-n junction. The MOSFET or Metal-Oxide-Semiconductor FET, has an insulating layer between the gate and the other electrodes. An n-channel JEBT is manufactured by placing p-type regions on an n-type bar of silicon: Source Gate Let us imagine the source to be grounded while the drain is 15 volts positive and the gate is near ground. Under these circumstances, the gate is surrounded by n-type silicon several volts more positive than the gate. Thus the p-n junction formed by the n and p type silicon is reverse biased. Negative carriers in the n-type silicon are repelled by the more negative gate. Usually the p-type is heavily doped while the n-type is moderately doped. In regions between the dashed lines and the p-type material, there will be very few carriers (the depletion region of a reverse-biased diode). As a result, the n-type channel through which current from drain to source must pass is constricted, limiting the current. If the gate voltage is raised, the reverse bias decreases and the depleted region retreats. The conducting channel is widened and the source-drain current increases. Similarly if the gate voltage is lowered, the drain-source current decreases. For either case, the gate current is tiny; that of a reverse-biased diode. Often, as you might guess, source and drain are interchangeable There are also p-channel, n-type gate FET's. A similar analysis would hold with voltages and currents reversed. An analysis similar to the h-parameter analysis is useful. However, since the input current is tiny, the proper independent variables are the input voltage (as opposed to input current for bipolar transistors) and the output voltage. The resulting parameters have the dimensions of inverse ohms and are called y-parameters. d, a, dl, = Soa! av, =m! dV, MT Bicearmtin” BV au cme 19-2 di, = a | Vin + Ae! Vout Vig Waxconsan Fou |v qcomstant Letting dlout=iouts dVout = Vout: dlin= iin, dVin = Vin, and also aa oy, Ale av, Og “2 al, . we get: av, 72 Ova 7% ME 9° out = ¥¢vin * YoYout ay jin = Yivin * Ye%out At low frequencies we can usually ignore the second equation; at high frequencies the charges moving in and out of the depletion region cannot be ignored and the second equation must be used. As before, if we want to hold the source at a constant potential, very possibly ground, we add an "s" to the subscripts to indicate common source: jout = Yfs¥in + YosYout {2) jin = Yis¥in + YrsVout Common Source Voltage Gain If we let Ro be the parallel equivalent of Rp and the load resistance, then jigyt =-Vou/Ro. (Remember that in the y-parameter analysis the currents are defined to be positive into the device.) “v our ~VYout/Ro = ¥8Vin + YosVout Yow =Yu Vin Yor + YR 19-3 From the specifications for the 2N5457, we find that a typical value of yg (also called gf) is 3500 wmho while the value of Yo is 4.0 umho. If we let Ry = 5000 2 the gain i Mout -3500_x_ 10% Vin 40x10 + 1/5000 = -17 Exercise 1 Calculate the gain for the VNIOKM with Ro = 50 Q. Use the value of yg at Vpg = 15 V and Vgg = 5 V. Yos must be estimated from the curves. [Ans: From the curves around Vqg = 5 volts we get yf = Alu/AVin = (.7 = .3)/(6 - 4) = 0.2 Q* and Yos = Alout/AVout * 0 as close as can be seen. Therefore the gain = - 0.2/(0 + 1/50) = -10.) Exercise 2 At room temperature, what is the largest gate resistor we could use for the VN1OKY if the gate voltage is to be within 0.1 volts of ground? (You will have to use the specification sheet and guess a little.) (ans: The data sheets list the maximum gate leakage current at 10 na. This current must flow through the gate resistor to ground. Thus Rmax = Vax‘l = (0.1/(10 * 10%) = 107 Q = 10 MQ.) FET-Input Op Amps There are now available op amps with field-effect transistor inputs. The LF351 gets its high input resistance (10? Q) from a matched pair of field-effect transistors in the op amp. The MOSFET The MOSFET's have several advantages and disadvantages compared to the JFET's. The insulation in the gate allows either polarity for the gate-source voltage for either n-channel or p-channel devices. By varying the channel doping we can obtain devices that normally (Vqg=0) conduct or normally do not conduct from drain to source. We end up with four possible MOSFET devices. N channel, +Vgs turns on, off at Vgs < 0 (enhancement mode} (Note: the VNIOKM is this type of device.) N channel, -Vgg turns off, on at VGg > 0 (depletion mode) P channel, +Vgg turns off, on at Vgg S 0 (depletion mode) P channel, -Vgg turns on, off at Vgs 2 0 (enhancement mode) 194 Such flexibility obviously makes the biasing arrangements easy. A disadvantage of MOSFET's is that static electricity can very easily destroy the insulation, Most devices are internally protected (at some loss of input impedance), but this protection is far from absolute. The Field-Effect Transistor as a Variable Resistor The principal use of the FET is as a high-input impedance amplifier, either in the common source or in the common drain (source follower) configuration. However, the FET has other, less common, but fascinating uses. The drain-source current-voltage characteristics of an N channel JFET are shown below. The different lines are for different gate voltages. Ip The characteristic curves are very linear in the vicinity of the origin. Thus the FET can be regarded as a resistor for small drain-to-source voltages. The resistance is set by the gate-to-source voltage. Resistances may range from as little as 20 Q to more than 10° Q. This suggests a number of applications, a few of which we will consider. Analog Switch When the gate voltage is zero, the drain to source part of the FET represents a resistor with R << 10 kQ, so Vout = Vin. When the gate voltage is at -20 V, the drain to source part of the FET represents a resistor with R >> 10 kM, 80 Vom *=0. Thus the device represents a switch, open when Vgate ~ -20 V, closed when Vgaie = 0. 19-5 N Channel JFET or Signin N Channel Depletion D Mode MOSFET 1S__ our 10kQ Sample and Hold Circuit It is often desirable to determine the voltage of a time-varying signal at a particular instant in time. This is done by sampling the voltage at the given time and holding the sample for analysis: FET Input |, D> Op Amp] SL Vie L Vs D s R = = C* 100 1000 pF Same type FST as in example above. 0 -20 Sample Initially, the gate of the FET is at 0 volts, so the drain to source part of the FET represents a small resistance through which C is charged to the signal voltage via the input voltage follower. At time tsample the gate voltage is lowered to -20 volts and the FET is essentially turned off (it becomes a huge resistance). Now the voltage on the capacitor C remains at what it was, at tsample- Vout is the same as the capacitor voltage and is available for analysis. Eventually, the input current to the FET-input op amp and the tiny leakage current through the FET will change the capacitor voltage. By then the analysis of Voy must be complete. Unless the capacitor is chosen carefully, its leakage current might exceed the other currents. 19-6 Sine Wave Oscillator The Wein bridge oscillator, described in Lecture 11, required an amplifier with a gain of exactly 3 to avoid distortion. One can use an FET to adjust the gain automatically. (Va a Initially, the gate of the FET is at zero volts and the FET represents a small resistance. We choose R3 to be slightly more than twice Rp plus the zero-gate-voltage resistance of the FET. Thus the gain is a little more than 3 and the circuit begins to oscillate. As it does so, C) is charged negatively through the diode D and the FET resistance rises, lowering the op amp gain until it is just the required 3. If one wished a certain amplitude output, a Zener diode of the required breakdown voltage could be placed in the output. Ry bt D R G = = sv 7D Ry ANA R ; if 4tE-—-Wv UE C1 is now charged only when Vo is more negative than the zener breakdown voltage. CHAPTER 19B: BIASING AND OPERATION OF FIELD EFFECT TRANSISTORS (FET's) 1.4 N-channel FET's N-channel FBT's are constructed of n-type silicon sandwiched between two layers of p-type material (Figure 1). The n-type material has been doped with enough donor atoms so that there is a large supply of free electrons in the conduction band and hence the n-type material is fairly conductive. Drain shaded = depletion region Drain Gate — : Gate ip Source See Symbol Figure 1. Internal structure and operation of the n-channel FET. The FET has three terminals: the Source (S), the Drain (D) and the Gate (G). When in operation, positive current ip flows from one end of the n-type material (the "Drain") to the other end (the "Source") through a channel of n-type material (hence the name "n-channel") between the two slices of p-type material. Notice that the names "Drain" and "Source" make sense if we remember that = positive current in one direction is actually a flow of electrons in the reverse direction. The two layers of the p-type material are connected to a single terminal and this terminal is suggestively called the "Gate". The voltage between the Gate and the Source VGg is used to control the flow of current through the n-channel. 1.1.1 OPERATION WITH SMALL Vps: THE TRIODE REGION How does Vgg control the current flow ip? Consider the situation where Ivpsl_<< 1 Volt and Vgs = 0. At the junction between the p-type material and the n-type material a depletion region forms similar to the depletion region around the p-n junction of the simple diode. However, the depletion regions on each side of the channel are fairly narrow and therefore do not bridge the n-channel. 19-6 Now we decrease Vgg. This reverse biases the Gate-to-Source p-n junction. As we recall from the simple diode, reverse biasing a p-n junction simply widens the depletion region. The reverse biased p-n junction or diode therefore carries very little current. This means that the gate input has very high input impedance, on the order of 100 MQ. Several changes occur as Vgg decreases: the depletion region widens, the conductive region of the n-channel narrows, and the resistance between the source and the drain increases. Since the resistance Rpg depends upon Vgg we effectively have a voltage-controlled resistor. A FET operating in this manner is said to be operating in the Triode region. The current ip as a function of Vpg and Vgg is illustrated in Figure 2. At the “pinch-off voltage" Vp, the two depletion regions meet and the n-channel has no carriers for the current. The current ip = 0 in this case. The channel is said to be "pinched off" in this case (Figure 3). The n-channel FET is said to be a depletion mode device as the control voltage depletes the current through the device. Depletion-mode devices will conduct current even when the control voltage or current is zero. The property is called 'self-biasing', meaning that the device works without having to supply a bias (turn-on Or operating) voltage or current. As you may remember, the bipolar (NPN or PNP) transistor does not work unless the base to emitter junction is biased with a 0.6 V potential. Bipolar transistors are therefore enhancement-mode devices, meaning that the control voltage or current enhances or increases the current through the device. Without a small bias voltage there are no carriers to carry the current in the device, shaded = depletion region Channel is pinched-off for Vos = Vp Figure 2. ip vs Vos in the Triode region. Figure 3, N-channel pinch-off in the Triode region. 1-9 1.1.2 OPERATION WITH LARGE Vj;: THE PINCH-OFF REGION Consider the n-channel FET with Vgg = 0 but Vpg >> 1 volt (Figure 4). Since Vp >> Vs, the donors in the n-type material are attracted to the drain as well as the gate. The depletion region is therefore no longer of uniform thickness along the n-channel; it has an extended width near the drain. As Vgg decreases (reverse-biasing the Gate-to-Source junction), only one end of the channel gets pinched off. If Vps is large, ip + 0 as carriers can drift through the small pinch-off region and pass through the n-channel. A device which is operating in this manner is said to be operating in the “pinch-off* region. This behavior is quite different from the triode region, where the pinch-off extended along the entire channel when Vgg = Vp, thereby Preventing any current from flowing between the source and the drain. [Prin Pinch-offat one end only! Tape shaded = depletion region bo G Source + ja Figure 4. N-channel operation in the pinch-off region, For operation with large Vps, ip can be approximated by: <8) iy Ipss_and Vp are FET parameters which depend upon FET size and fabrication technique. These two parameters are specified by the data sheet for the FET. If the data sheets provide a plot of ip versus Vge you can directly read off Ipsg and Vgg from the graph (Figure 5). Specifically, Ipsg is the 2 4) Ipss). Vp is the pinch-off voltage; when Vgg=Vp then ip = These two points are respectively the y and the x intercepts of the ip versus Vqg graph. current ip when Vgg = 0 (i.e. ip = ss 19-19 ip inss (Vos= 0) Figure 5. ip vs Vos in the pinch-off region. Figure 6 illustrates the equivalent circuit for an FET operating in the pinch-off region. One can calculate a circuit response by substituting the equivalent circuit wherever one finds the FET in the circuit. Notice that the Gate and the Source are unconnected. The reverse bias of the Gate-to-Source junction results in an extremely high input impedance (>100 M®) which is essentially an open circuit FET's are therefore very useful for amplifying signals with high output impedances. FET's are also used on the input stages of Op-Amps as they provide the high input impedance necessary for a nearly ideal Op-Amp . Figure 6. Equivalent FET circuit model in the pinch-off region. For applications as an amplifier, the F&T is usually operated in the pinch-off region. This requires the drain voltage to be above the gate voltage by at least |Vp| so that the carriers have sufficient energy to drift through the pinch-off region of the n-channel. This requirement can also be written as Vpg2|Vpll or equivalently Vps> Vos +IVpl-. ag-12 1.1.3 AMPLIFIER DESIGN AND BIASING Consider the simple amplifier design of Figure 7. The symbol for the n-channel FET is the [-shape with the arrow pointing inward. +12V +12V 3% F—> Vo | Vo Cie Ws vs Ry Se [ -12V 2 Figure 7. Simple FET amplifier circuit, Here are the steps you will follow to properly bias the FET. 1, Determine what ip you want. Many times this is given to you. 2. Use ji vy toss('X2] to determine the necessary Vag. Ipsg and Vp are determined from the data sheets. 3. Remember drain voltage must be higher than gate by at least [Vp|- 4, If a specific gain is called for, use this information as an additional constraint into the calculation of the resistances. 5. Using 2, 3, and 4, pick Vs, VG, and Vp. Note that sometimes there are not enough constraints so you are allowed to freely pick one of these voltages. Once the voltages are known, the resistors can be chosen since you already know the currents through the resistors. Example: Suppose we want ip = 2 mA for an FET with Ipsg = 20 mA and Vp = -5 V for the circuit in Figure 7. From step 1, we use ip to calculate V@s: therefore: 19-12 There will be no current flow ip unless VGS>Vp = -5 V. Therefore, we need to take the more positive root of the equation: 1 Ves = 5 1] = -341V (ke } Therefore Vg=Vg - 3.3 Vv. We also need Vp>Vg- Vp for the FET to operate in the pinch-off region. Let us pick Vg = 0 (arbitrarily, since we do not have enough constraints for a unique solution). This then requires Vg = 3.3 V. The pinch-off region requirement becomes Vp > 5 V. So I will choose Vp = 7 V (anything greater than 5 V will do). To get Vg = 0 just choose R1=Rg. These can be quite large, but not as large as the input impedance of the FET (100 MQ). One possible choice would be R]=Rz = 5 MQ. 12-7 with ip = 2 mA and Vp = 7 V, we therefore need Rp= 2-7 ~ 2500 0. Similarly, Vs = 3.3 V requires Rg= ao = 7650 2. What is the voltage gain of this circuit Vp/Vg at this bias point? This calculation is difficult to solve exactly as the power law dependence of iq on Vgg complicates the calculation. However, for small variations of Vc about the operating point of the FET we can use a linear approximation for the ig on Vgg dependence: a 1 2, af 42h Jo 8nd Ves we This linearized (small signal) model for the FET is illustrated in Figure 8. where: 19-13 Figure 8. Linear FET circuit model in the pinch-off region. The simple FET amplifier circuit using the small signal FET model approximation is illustrated in Figure 9. +12V a Rp Pw +12. V BnVoos | sv, -12V Figure 9. Linear circuit model of the simple FET amplifier. Using standard CL and KVL analysis, we derive the following equations: Vp= 12-ipRp Vas = VG - Vs = Vg - (-12+ ipRs) ip=8mVGs Solving these equations for Vp as a function of Vg we find: Rp(Vo +12) ers 7 mR 19-14 The gain is actually the slope of this line: BeRp I+e,Rs Notice that if gmRs >> 1 then: R, gain = -=2 identical to the simple bipolar transistor amplifier. However, for FETs, usually gm * 0.01 - 0.001 U so unless Rg >> 10,000 9 this approximation will give the wrong answer. In our simple example, we calculate: - sboxe*fi-22]2) = 272%103 6 With Rp = 2500 and Rs = 7650 Q, we calculate: 2.72107 (2500) 1+2.72*107 (7650) 03 1.2 P-channel FET's Pochannel FETs (Figure 10) operate in a similar manner to n-channel FET's. These devices are also depletion mode devices, and operate in the same manner by reverse biasing the Gate-Source junction to pinch off the conduction channel. However since the gate is made of n-type material and the channel is made of p-type material, the reverse bias means that VGs must be positive for operation, not negative. The Pinch-off voltage will be a positive voltage. Furthermore, the Drain voltage is kept lower than the Source voltage for the p-channel device, reverse from the n-channel device. 19-15 Source shaded = depletion region piype Pea Source Gate Gate_—_| Gy ip + Vso =~ Drain ics eee Symbol Figure 10. Internal structure and operation of the p-channel FET. Figure 11 illustrates the variation of ip with Vsq in the pinch-off region. The relationship is: Notice that the equation is identical to the equation for the n-channel FET. ip ips Figure 11. ip ¥s Veo in the pinch-off region, The requirement for operation in the pinch-off region is: VGs>Vps*+IVpl 19-16 1.3 Metal Oxide Semiconductor FET's (MOSFETS) MOSFETS have a different construction and operation mode than n-channel and p-channel FET's (Figure 12). These devices have Source, Drain and Gate terminal, and an additional terminal called the Body terminal. A thin oxide (non-conducting) layer separates the gate from the other device material. The oxide layer is constructed so that no current can flow into the gate so these devices have very high input impedance (again >100 MO). With zero voltage between the source and the gate, the channel between the source and the drain is narrow enough that the depletion region completely covers the channel, thereby allowing current to flow between the Drain and the Source (ip = 0). Applying a small positive voltage between the gate and the source terminal, however, decrease the size of the depletion region. Above a well-defined threshold voltage Vj, the depletion region narrows sufficiently to allow a small conductive path to form between the source and the drain. If the voltage between the Drain and the Gate is sufficient (Vp>Vg-V) the device will also operate in the pinch-off region. The resulting Vgg versus ip curve in the pinch-off region is illustrated in Figure 13, and is well defined by the equation: ip=K(V@s - Vo? where K and Vj are parameters that are supplied by the data sheet of the device. Vos Source - Garay) Drain M gate voltage induces 77x ° cartier concentration Cy: Wall s (allows conduction 0 ‘os Figure 13, jp versus Vos for n-type MOSFET (NMOS). Since the applied voltage is used to create a conducting path, the MOSFET is an enhancement mode device, similar to the bipolar transistor. Circuit design and analysis with the enhancement mode FET is similar to the process used in the depletion mode FETs, except that the ip vsVGg equation and the pinch-off region requirement equation are different. The enhancement mode device also needs to be actively biased as ip = 0 if Vas

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