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Transistors (MOSFETs)
Tipos de MOSFETS:
JFET Junction FET
Depletion - Depleo
Enhancement - Crescimento
Copyright 2004 by Oxford University Press, Inc.
tox = 2 a 50 nm
W = 0.2 a 100 m
L = 0.1 a 3 m
Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) crosssection. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the
range of 2 to 50 nm.
Copyright 2004 by Oxford University Press, Inc.
Criao do canal
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts
as a resistance whose value is determined by vGS. Specifically, the channel conductance is
proportional to vGS Vt and thus iD is proportional to (vGS Vt) vDS. Note that the depletion
region is not shown (for simplicity).
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Figure 4.4 The iDvDS characteristics of the MOSFET in Fig. 4.3 when the voltage
applied between drain and source, vDS, is kept small. The device operates as a linear
resistor whose value is controlled by vGS.
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Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel
acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant
at a value > Vt.
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Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type
NMOS transistor operated with vGS > Vt.
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Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS
reaches vGS Vt the channel is pinched off at the drain end. Increasing vDS above vGS Vt has little
effect (theoretically, no effect) on the channels shape.
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10
11
Cox = ox
tox
ox = 3.45 1011 F / m
tox
E( x) =
dv( x )
dx
12
dx
dv( x )
= n E ( x ) = n
dx
dt
A corrente de drift resultante pode ser calculada como
i=
dq dq dx
dv( x )
=
= nCoxW [vGS v( x ) Vt ]
dt dx dt
dx
iD = i = nCoxW [vGS v( x ) Vt ]
dv( x )
dx
13
v DS
iD = ( nCox )(
1 2
W
)[(vGS Vt )vDS vDS
]
2
L
K n' = nCox
14
Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a
separate n-type region, known as an n well. Another arrangement is also possible in which an n-type
body is used and the n device is formed in a p well. Not shown are the connections made to the p-type
body and to the n well; the latter functions as the body terminal for the p-channel device.
15
Smbolos do MOSFET
Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit
symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device
polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the
body or when the effect of the body on device operation is unimportant.
Copyright 2004 by Oxford University Press, Inc.
16
Carracterstica iD x vDS
i D = K n' (
W
1
iD = K n' ( )(vGS Vt )2
L
2
1 2
W
)[(vGS Vt )v DS v DS
]
2
L
iD = K n' (
W
)(vGS Vt )vDS
L
Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal
directions of current flow indicated. (b) The iDvDS characteristics for a device with kn (W/L) = 1.0 mA/V2.
Copyright 2004 by Oxford University Press, Inc.
17
Caracterstica iD x vDS
1
W
iD = K n' ( )(vGS Vt )2
2
L
iD = K n' (
1 2
W
)[(vGS Vt )vDS vDS
]
L
2
iD = K n' (
rDS =
W
)(vGS Vt )vDS
L
1
K n'
W
(VGS Vt )
L
VOV = VGS Vt
1
W
K n' VOV
L
18
Regio de saturao
1
W
iD = K n' ( )(vGS Vt )2
2
L
Figure 4.12 The iDvGS characteristic for an enhancement-type NMOS transistor in saturation
(Vt = 1 V, kn W/L = 1.0 mA/V2).
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19
Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation
region.
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20
Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for
operation in the triode region and in the saturation region.
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21
1
W
iD = K n' ( )(vGS Vt )2
2
L
Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from
the drain, thus reducing the effective channel length (by DL).
Copyright 2004 by Oxford University Press, Inc.
22
VA
ro =
VA
VA
=
I D 1 K ' (W )(v V )2
n
GS
t
2
L
1
W
I D = K n' ( )(vGS Vt )2
2
L
iD = I D +
1
1
ID
1
W
vDS = I D (1 +
vDS ) = K n' ( )(vGS Vt )2 (1 +
vDS )
2
VA
VA
L
VA
Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the
process technology and, for a given process, is proportional to the channel length L.
Copyright 2004 by Oxford University Press, Inc.
23
ro =
VA
VA
=
I D 1 K ' (W )(v V )2
n
GS
t
L
2
Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating
the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by
Eq. (4.22).
Copyright 2004 by Oxford University Press, Inc.
24
Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an
arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to
the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that vGS
and vDS are negative and iD flows out of the drain terminal.
Copyright 2004 by Oxford University Press, Inc.
25
Regio de Triodo:
vGS Vt
iD = K 'p (
vDS vGS Vt
1 2
W
)[(vGS Vt )vDS vDS
]
2
L
iD = K 'p (
vDS vGS Vt
W
)(vGS Vt )vDS
L
26
Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for
operation in the triode region and in the saturation region.
Copyright 2004 by Oxford University Press, Inc.
27
Exerccio 4.8
Vt = -1 V
Kp = 60 A/V2
W/L = 10
Figure E4.8
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28
Body Effect
Em um circuito integrado do tipo NMOS o substrato conectado
tenso mais negativa do circuito, impedindo assim a conduo do diodo
de substrato para fonte.
Esta polarizao reversa (VSB) tem como efeito, a reduo da
profundidade do canal, afetando portanto a corrente de dreno.
O efeito de VSB geralmente representado como uma alterao na
tenso de limiar. Vt cresce com o aumento de VSB.
29
Efeitos da Temperatura
Vt cai 2 mV para cada 1oC de aumento da temperatura.
K diminui com o aumento da temperatura.
A corrente de dreno diminui com o aumento da temperatura.
30
Breakdown (Avalanche)
31
Table 4.1
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32
Exemplo 4.2
Faa ID = 0,4 mA e VD = 0,5V
Dados:
Vt = 0,7 V
nCox = 100 A/V2
L = 1 m
W = 32 m
33
Exemplo 4.3
Faa ID = 80 A. Calcule R e VD.
Dados:
Vt = 0,6 V
nCox = 200 A/V2
L = 0,8 m
W = 4 m
34
Exerccio 4.12
Como continuao do exemplo
anterior, com R = 25 K, ID = 80 A
em Q1.
Calcule a corrente de dreno em Q2.
Dados:
Vt = 0,6 V
nCox = 200 A/V2
L = 0,8 m
W = 4 m
Figure E4.12
Copyright 2004 by Oxford University Press, Inc.
35
Exemplo 4.4
Faa VD = 0,1V e projete o circuito.
Qual a resistncia entre dreno e
source neste ponto de operao?
Dados:
Vt = 1 V
Kn(W/L) = 1 mA/V2
36
Exemplo 4.5
Analise o circuito.
Dados:
Vt = 1 V
Kn(W/L) = 1 mA/V2
Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.
Copyright 2004 by Oxford University Press, Inc.
37
Exemplo 4.6
38
Exemplo 4.7
Calcule iDN, iDP e vo para:
vI = 0 V, 2,5 V e -2,5 V.
Dados:
- Vtp = Vtn = 1 V
Kn(W/L) = Kp(W/L) =1 mA/V2
39
Exerccio 4.16
Figure E4.16
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40
Caracterstica de
Transferncia
iD =
VDD
1
vDS
RD RD
Reta de carga
Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to
determine the transfer characteristic of the amplifier in (a).
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41
Caracterstica de
Transferncia
Av =
dvo
dt vi =VIQ
Ganho do Amplificador
Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.
Copyright 2004 by Oxford University Press, Inc.
42
Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room
for positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the
triode region and might not allow for sufficient negative signal swing.
Copyright 2004 by Oxford University Press, Inc.
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44
45
1
W
I D = nCox (VGS Vt )2
2
L
Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID.
Devices 1 and 2 represent extremes among units of the same type.
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46
ID =
VG VGS
RS
Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a)
basic arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply; (d)
coupling of a signal source to the gate using a capacitor CC1; (e) practical implementation using two
supplies.
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47
ID =
VSS VGS
RS
48
ID = 0,5 mA
Dados:
VDD = 15 V
Vt = 1 V
Kn(W/L) = 1 mA/V2
49
ID =
VDD VGS
RD
Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
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50
I REF =
1 W
I D1 = K n' (VGS Vt )2
2 L 1
1 W
I D 2 = K n' (VGS Vt )2
2 L 2
I D 2 = I REF
(W / L )2
(W / L )1
Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the
constant-current source I using a current mirror.
Copyright 2004 by Oxford University Press, Inc.
51
Anlise C.C.
1 W
I D = K n' (VGS Vt )2
2
L
VD VGS Vt
vGS = VGS vgs
1 W
iD = K n' (VGS + v gs Vt )2
2
L
1 W
1 W
W
iD = K n' (VGS Vt )2 + K n' (VGS Vt )v gs + K n' vgs 2
2
2
L
L
L
distoro
Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.
52
1 W
W
(VGS Vt )v gs >> K n' vgs 2
2
L
L
g m = K n'
W
(VGS Vt )vgs = g mvgs
L
W
W
(VGS Vt ) = K n' VOV
L
L
ganho de transcondutncia
53
gm =
id
vGS
vGS =VGS
54
vD = VDD RDiD
vD = VDD RD ( I D + id )
vd = RDid = g m RD vgs
Av =
vd
= g m RD
vgs
Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34.
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55
id = g mvgs
g m = K n'
ro =
| VA |
ID
W
2I D
(VGS Vt ) =
L
VGS Vt
Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation
(the channel-length modulation effect); and (b) including the effect of channel-length modulation, modeled
by output resistance ro = |VA| /ID.
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56
Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.
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Modelo T
Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been
omitted but can be added between D and S in the T model of (d).
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Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An
alternative representation of the T model.
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g mb =
iD
vBS
vGS = const .
v DS = const .
Transcondutncia do corpo
Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to
the body.
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Table 4.2
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Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier
configurations.
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Figure E4.30
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Table 4.3
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Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the
amplifier for small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with
the MOSFET model implicitly utilized.
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Figure 4.44 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal
equivalent circuit with ro neglected.
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Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent
circuit of the amplifier in (a). (c) The common-gate amplifier fed with a current-signal input.
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Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model.
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71
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Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the
case in which the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with
Cdb neglected (to simplify analysis).
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Table 4.5
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Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response
of the amplifier in (a) delineating the three frequency bands of interest.
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Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit;
(b) the circuit of (a) simplified at the input and the output;
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Figure 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent
capacitance Ceq; (d) the frequency response plot, which is that of a low-pass single-time-constant circuit.
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Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro
is neglected.
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Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break
frequencies are sufficiently separated for their effects to appear distinct.
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Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH);
(b) graphical construction to determine the operating point; (c) equivalent circuit.
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Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL);
(b) graphical construction to determine the operating point; (c) equivalent circuit.
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Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output
waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d)
equivalent circuit during the capacitor discharge.
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Figure 4.58 The current in the CMOS inverter versus the input voltage.
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Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol
applicable for the case the substrate (B) is connected to the source (S).
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Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = 4
V and kn(W/L) = 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iDvDS
characteristics; (c) the iDvGS characteristic in saturation.
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Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in
the triode and the saturation regions. The case shown is for operation in the enhancement mode (vGS is
positive).
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90
Figure 4.62 Sketches of the iDvGS characteristics for MOSFETs of enhancement and depletion types, of
both polarities (operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also
note that for generality somewhat different values of |Vt| are shown for n-channel and p-channel devices.
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Figure E4.51
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Figure E4.52
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Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with CS = 10 mF and CS = 0
(i.e., CS removed).
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Figure P4.18
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Figure P4.33
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Figure P4.36
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Figure P4.37
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Figure P4.38
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Figure P4.41
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Figure P4.42
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Figure P4.43
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Figure P4.44
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Figure P4.45
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Figure P4.46
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Figure P4.47
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Figure P4.48
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Figure P4.54
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Figure P4.61
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Figure P4.66
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Figure P4.74
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Figure P4.75
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Figure P4.77
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Figure P4.86
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Figure P4.87
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Figure P4.88
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Figure P4.97
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Figure P4.99
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Figure P4.101
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Figure P4.104
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Figure P4.117
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Figure P4.120
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Figure P4.121
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Figure P4.123
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