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UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
3 Description
2 Applications
PACKAGE
SOIC (8)
UCC25600
VS
8
GD1
OC
GD2
RT
VCC
DT
GND
SS
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2011) to Revision C
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Page
Page
UCC25600
www.ti.com
DT
GD1
RT
VCC
OC
GND
SS
GD2
NO.
DT
GD1
GD2
GND
OC
I/O
DESCRIPTION
This pin sets the dead time of high-side and low-side switch driving signals. Connect a resistor to
ground. With internal 2.25-V voltage reference, the current flowing through the resistor sets the
dead time. To prevent shoot through when this pin is accidentally shorted to ground, the
minimum dead time is set to 120 ns. Any dead time setting less than 120 ns will automatically
have 120-ns dead time.
High-side and low-side switch gate driver. Connect gate driver transformer primary side to these
two pins to drive the half-bridge.
Ground
Overcurrent protection pin. When the voltage on this pin is above 1 V, gate driver signals are
actively pulled low. After the voltage falls below 0.6 V, the gate driver signal recovers with softstart. When OC pin voltage is above 2 V, the device is latched off. Bringing VCC below the
UVLO level resets the overcurrent latch to off.
RT
The current flowing out of this pin sets the frequency of the gate driver signals. Connect the optocoupler collector to this pin to control the switching frequency for regulation purposes. Parallel a
resistor to ground to set the minimum current flowing out of the pin and set the minimum
switching frequency. To set the maximum switching frequency limiting, simply series a resistor
with the opto-coupler transistor. This resistor sets the maximum current flowing out of the pin and
limits the maximum switching frequency.
SS
Soft-start pin. This pin sets the soft-start time of the system. Connect a capacitor to ground.
Pulling this pin below 1 V will disable the device to allow easy ON/OFF control. The soft-start
function is enabled after all fault conditions, including bias supply OV, UVLO, overcurrent
protection, and overtemperature protection.
VCC
Bias Supply. Connect this pin to a power supply less than 20 V. Parallel a 1-F capacitor to
ground to filter out noise.
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
22
VCC + 0.5
0.5
25
mA
Current, RT
mA
Current, DT
0.7
mA
260
40
125
65
150
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrostatic discharge
(1)
UNIT
2000
500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
11.5
MIN
18.0
RT resistance
8.666
DT resistance
3.3
39
SS capacitor
0.01
NOM
(1)
D (SOIC)
UNIT
8 PINS
RJA
118.5
C/W
RJC(top)
72.5
C/W
RJB
58.9
C/W
JT
24.1
C/W
JB
58.4
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
UCC25600
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
1.5
7.5
100
400
UNIT
VUVLO
VOVP
SS = 0 V
SS = 5 V, CGD1 = CGD2 = 1 nF
VCC = 9 V
9.9
10.5
11.1
8.9
9.5
10.1
UVLO hysteresis
Measured at VCC
0.7
1.3
18
20
22
16
18
20
OVP hysteresis
Measured at VCC
1.5
2.5
RDT = 16.9 k
390
420
450
2.5
mA
A
Dead time
ns
OSCILLATOR
FSW(min)
40C to 125C
40.04
41.70
43.36
20C to 105C
40.45
41.70
42.95
KICO
60
80
100
Hz/A
50
ns
FSW_BM
FSW(start)
50
SS = 5 V
300
350
400
SS = 5 V
280
330
380
40C to 125C
122
142.5
162
20C to 105C
125
142.5
160
1.3
kHz
kHz
ISS
Enable threshold
Measure at SS rising
1.1
1.2
Disable threshold
Measured at SS falling
0.85
Disable hysteresis
Measured at SS
0.15
250
500
750
VSS = 0.5 V
225
175
125
VSS = 1.35 V
5.5
4.5
1.1
0.35
ns
A
0.9
1.1
VOC2(off)
1.8
2.0
2.2
VOC1(on)
0.5
0.6
0.7
Td_OC
Propagation delay
60
200
500
ns
IOC
OC bias current
200
nA
VOC = 0.8 V
200
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE DRIVE
GD1, GD2 output voltage high
IGD1, IGD2 = 20 mA
IGD1, IGD2 = 20 mA
11
12
30
IGD1, IGD2 = 20 mA
0.08
0.2
IGD1, IGD2 = 20 mA
10
1 V to 9 V, CLOAD = 1 nF
18
35
9 V to 1 V, CLOAD = 1 nF
12
25
0.5
1.75
ns
V
THERMAL SHUTDOWN
160
140
UCC25600
www.ti.com
350
Fsw - Switching Frequency - kHz
0.9
0.8
0.7
0.6
0.5
0.4
0.3
OC Open
0.2
300
250
200
150
100
-40 C
25 C
50
0.1
125 C
10
11
12
13
14
IRT - RT Current - mA
1000
1000
- 40 C
900
900
25 C
800
800
125 C
DT - Dead Time -
DT - Dead Time -
700
600
500
400
700
600
500
400
300
300
200
200
100
100
-40 C
25 C
125 C
0
100
200
300
400
500
600
700
IDT - DT Current - uA
45
1.2
12
0.6
10
0.6
0.4
0.2
0
-2
500
400
40
0.8
0.8
300
35
14
200
30
1.4
100
25
16
10
20
1.6
Gate Drive
Voltage
Gate Drive Sink
Current
12
15
16
14
10
0.4
0.3
0.2
0.1
-0.2
600
-2
0
200
400
600
800
-0.1
1000
Time - ns
Time - ns
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
300
UVLO Threshold -
Propagation Delay - ns
250
200
150
10
100
9
50
8
-60 -40 -20
20
40
60
20
40
60
80
22
2.5
OVP Off Threshold - VCC Rising
21
Tj - Junction Temperature - C
Tj - Junction Temperature - C
20
19
18
2
OC Off Threshold - Voc Rising
OC On Threshold - Voc Falling
1.5
0.5
17
16
0
-60 -40 -20
20
40
60
80
Tj - Junction Temperature - C
20
40
60
Tj - Junction Temperature - C
100
On Time Mismatch - ns
80
60
40
20
0
0
50
100
150
200
250
300
350
UCC25600
www.ti.com
7 Detailed Description
7.1 Overview
Due to high power density and high efficiency requirements, LLC topology is employed in many applications. The
LLC resonant converter has many unique characteristics and improvements compared with hard-switch bridge
topology and phase-shift full bridge. For example, LLC has a simple structure, and could achieve primary
MOSFET zero voltage switching (ZVS) and the secondary rectifier zero current switching (ZCS) from no load to
full load.
The UCC25600 device is an LLC-resonant half-bridge controller which integrates built-in, state-of-the-art
efficiency boost features with high-level protection features to provide cost-effective solutions.
DT
T
J
160oC/140oC
+
TSD
Thermal
ShutDown
OV
+
10.5V
9.5V
Dead time
generator
RDT
20V
18V
UVLO
7 VCC
2.5V
Feed
back
RT
Ic
8 GD1
OSC
Vss
UVLO
OV
OC
TSD
SET
VCC
5 GD2
FAULT
Q
CLR
5uA
6 GND
GD_Stop
6V
170uA
OC
SS
OC
1V
Vss
4
Css
OC_latch
+
2V
1.2V/1V
FAULT
S
SET
CLR
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
1.2V
Vss
Gate driver
t ss _ delay
t ss
tSS _ delay =
10
1.2V
CSS
175m A
(1)
UCC25600
www.ti.com
fS =
1
2
1
6ns 1A
I RT
+ 1.81mA - SS
2.2 k W
+ 150ns
(2)
After the SS pin voltage reaches 4 V, the soft-start period is finished and switching frequency becomes the same
as demanded by the RT pin current. The time used to charge the SS pin from 1.2 V to 4 V is defined as soft-start
time and can be calculated as:
tSS =
2.8V
CSS
5m A
(3)
To ensure reliable operation, the gate drivers restart with GD2 turning high. This prevents uncertainty during
system start up.
7.3.2 Overcurrent Protection
To prevent power stage failure under excessive load current condition, the UCC25600 includes an overcurrent
protection function. With a dedicated OC pin, the power stage is shut down when OC pin voltage is above 1 V.
Once the OC pin voltage becomes lower than 0.6 V, the gate driver recovers with a soft start. To enhance
system safety, the UCC25600 latches up the whole system when the OC pin becomes above 2 V. Bring VCC
below the UVLO level to reset the device.
The current can be indirectly sensed through the voltage across the resonant capacitor by using the sensing
network shown in Figure 13.
Lr
From half bridge
TR
Lm
Cp
Rs
D2
To OC
Rp
Cs
D1
Cr
VCr _ pk =
jf L Q + 1
4
nVo n n2 e
p
f n Ln
(4)
Therefore, the resonant capacitor voltage reaches its maximum value at the minimum switching frequency and
maximum load. According to this equation, the current sensing network components can be calculated. Due to
the nature of FHA, the final circuit parameters need to be verified through actual hardware test.
Submit Documentation Feedback
11
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
FUNCTION
DESIGN EQUATION
2
RS
CS
RP
CP
Filter capacitor
Rs =
Cs =
Rp =
Cp =
VCr _ pk (max )
2 PRs (max)
(5)
10
Rs f min
Rs
VCr _ pk (max )
10
R p f min
(6)
p
(7)
(8)
12
UCC25600
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13
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
Cr
Lr
n:1:1
Lm
Vge
Lr
Lm
Re
Voe
UCC25600
www.ti.com
Re =
8 2
n R
p2
(9)
Based on this equivalent circuit, the converter gain at different switching frequencies can be calculated as:
jw Lm Re
Vo
jw Lm + Re
=
jw Lm Re
1
VDC / 2
+
+ jw Lr
jw Lm + Re jwCr
(10)
In this equation VDC/2 is the equivalent input voltage due to the half-bridge structure.
Table 3. Circuit Definition Calculations
NORMALIZED GAIN
M=
Vo
VDC / 2
RESONANT
FREQUENCY
f0 =
QUALITY FACTOR
1
2p Lr Cr
(11)
Qe =
(12)
Lr / Cr
Re
NORMALIZED
FREQUENCY
fn =
f
f0
INDUCTOR RATIO
Ln =
(14)
Lm
Lr
(13)
(15)
Following the definitions in Table 3, the converter gain at different switching frequencies can be written as:
M=
Ln fn2
(Ln + 1) fn2 - 1 + j (fn2 - 1) fn Qe Ln
(16)
Because of the FHA, this gain equation is an approximation. When the switching frequency moves away from the
resonant frequency, the error becomes larger. However, this equation can be used as a design tool. The final
results need to be verified by the time-based simulation or hardware test.
15
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
From Equation 16, when the switching frequency is equal to the resonant frequency, fn = 1 and converter voltage
gain is equal to 1. Converter gain at different loads and inductor ratio conditions are shown in Figure 16 through
Figure 19.
2
Qe = 0.1
Qe = 0.2
Qe = 0.5
Qe = 1
Qe = 2
Qe = 5
1.5
1.5
0.5
0
0.1
Qe = 0.1
Qe = 0.2
Qe = 0.5
Qe = 1
Qe = 2
Qe = 5
0.5
0.5
1.5
0
0.1
0.5
fn
Figure 16. M vs fN
2
Qe = 0.1
Qe = 0.2
Qe = 0.5
Qe = 1
Qe = 2
Qe = 5
1.5
Qe = 0.1
Qe = 0.2
Qe = 0.5
Qe = 1
Qe = 2
Qe = 5
1.5
0.5
0
0.1
Figure 17. M vs fN
1.5
fn
0.5
0.5
1.5
0
0.1
fn
0.5
1.5
fn
Figure 18. M vs fN
Figure 19. M vs fN
Based on its theory of operation, the LLC resonant converter is controlled through pulse frequency modulation
(PFM). The output voltage is regulated by adjusting the switching frequency according to the input and output
conditions. Optimal efficiency is achieved at the nominal input voltage by setting the switching frequency close to
the resonant frequency. When the input voltage drops low, the switching frequency is decreased to boost the
gain and maintain regulation.
The UCC25600 resonant half-bridge controller uses variable switching frequency control to adjust the resonant
tank impedance and regulate output voltage. This 8-pin package device integrates the critical functions for
optimizing the system performance while greatly simplifying the design and layout.
16
UCC25600
www.ti.com
(17)
To prevent shoot through when the DT pin accidentally connects to ground, a minimum 120-ns dead time is
inserted into the 2 gate driver outputs. Any dead-time setting less than 120 ns will be limited to 120 ns.
8.1.3 Oscillator
With variable switching frequency control, UCC25600 relies on the internal oscillator to vary the switching
frequency. The oscillator is controlled by the current flowing out of the RT pin. Except during soft start, the
relationship between the gate signal frequency and the current flowing out of the RT pin can be represented as:
fS =
1
1
I RT 83Hz / m A
ns
A
6
1
2
+ 150ns
I RT
(18)
Because the switching frequency is proportional to the current, by limiting the maximum and minimum current
flowing out of the RT pin, the minimum and maximum switching frequency of the converter could be easily
limited. As shown in Figure 20, putting a resistor from the RT pin to ground limits the minimum current and
putting a resistor in series with the opto-coupler limits the maximum current.
UCC25600
Maximum
frequency limiting
RT
R1
Minimum
frequency limiting
R2
17
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
I f max =
I f min =
6ns
1
- 150ns
2 f max
(19)
6ns
1
- 150ns
2 f min
(20)
1
1
I f max = 2.5V +
R1 R2
I f min =
(21)
2.5V
R2
(22)
12V@25A
+
+
11V
12V Bias
(External)
+
18
UCC25600
www.ti.com
TARGET VALUE
Output voltage
12 V
300 W
375 V to 405 V
91%
Switching frequency
Resonant frequency
130 kHz
(23)
(24)
(c) Choose Ln and Q. The Ln range is typically selected from 3 to 9. Choose Q based on the curves below,
where the peak gain must be higher than or equal to the maximum resonant gain required. Based on the
below curves, Q selects 0.45.
Ln = Lm/Lr = 5
(25)
Q = (Lr / Cr ) / Re q = 0.45
(26)
(27)
(28)
19
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
fr =
2p Lr Cr
(g) Combine the above two equations:
(29)
Lr = 55H
(30)
(31)
2. Calculate Rdt. In the UCC25600, dead time can be adjusted through a single resistor from DT pin to ground.
With an internal 2.25-V voltage reference, the current flow through the resistor sets the dead time.
td = 20ns + Rdt 24ns/k
where
td = 300 ns
Rdt = 11.7 k
(32)
(33)
(34)
(35)
4. A 47nF capacitor is selected. Calculate RT1 and RT2. Refer to Oscillator for more details. RT1 and RT2 are
used to limit maximum switching frequency and minimum switching frequency. RT1 and RT2 can be
calculated based on following equations:
Ifmax = 6 ns/(1/2fmax - 150 ns)
Ifmin = 6 ns/(1/2fmin - 150 ns)
Ifmax = 2.5 V(1/RT1 + 1/RT2)
Ifmin = 2.5 V/RT2
(36)
(37)
(38)
(39)
(40)
(41)
6. Calculate Rs, Cs, Rp, and Cp. Refer to Overcurrent Protection for more details.
Rs = 300 k
Cs = 22 pF
Rp = 4.99 k
Cp = 1 F
20
(42)
(43)
(44)
(45)
UCC25600
www.ti.com
60
180
45
135
30
90
15
45
-15
-45
-30
-90
-45
P h as e (D eg )
G a i n (d B )
-135
Gain
Phase
-60
10
100
1000
10000
100000
-180
1000000
Frequency (H z)
21
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
Four-layer layout is recommended
A 1-F ceramic decoupling capacitor is recommended, to be placed as close as possible between the VCC
terminal and GND, and tracked directly to both terminals.
Place CSS, RDT, Rp, Cp, RT1, and RT2 as close as possible to the UCC25600.
Connect a regulated bias supply to the VCC pin.
22
UCC25600
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23
UCC25600
SLUS846C SEPTEMBER 2008 REVISED JUNE 2015
www.ti.com
11.2 Trademarks
E2E is a trademark of Texas Instruments.
is a registered trademark of ~Texas Iinstruments.
All other trademarks are the property of their respective owners.
11.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
24
www.ti.com
29-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
UCC25600D
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
25600
UCC25600DR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
25600
UCC25600DRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
25600
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
www.ti.com
29-Jun-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
29-Jun-2016
Device
UCC25600DR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
29-Jun-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC25600DR
SOIC
2500
367.0
367.0
35.0
Pack Materials-Page 2
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