14nm FDSOI Technology for High Speed and Energy Efficient Applications

O. Weber*, E. Josse, F. Andrieu*, A. Cros, E. Richard, P. Perreau*, E. Baylac, N. Degors**, C. Gallon, E. Perrin, S. Chhun, E. Petitprez, S. Delmedico, J. Simon**, G. Druais,
S. Lasserre**, J. Mazurier*, N. Guillot, E. Bernard, R. Bianchini, L. Parmigiani, X. Gerard, C. Pribat, O. Gourhant, F. Abbate, C. Gaumer, V. Beugin*, P. Gouraud, P. Maury, S. Lagrasta,
D. Barge, N. Loubet, R. Beneyton, D. Benoit, S. Zoll, J.-D. Chapon, L. Babaud, M. Bidaud, M. Gregoire, C. Monget, B. Le-Gratiet, P. Brun*, M. Mellier, A. Pofelski, L.R. Clement,
R. Bingert, S. Puget, J.-F. Kruck, D. Hoguet, P. Scheer, T. Poiroux*, J.-P. Manceau**, M. Rafik, D. Rideau, M.-A. Jaud*, J. Lacord, F. Monsieur, L. Grenouillet*, M. Vinet*, Q. Liu,
B. Doris**, M. Celik, S.P. Fetterolf**, O. Faynot* and M. Haond

STMicroelectronics, *CEA-LETI, **IBM, 850 rue Jean Monnet, 38926 Crolles, France
Email : olivier.weber@st.com ; Phone : +33 438 92 26 02

OM

Device Platform Features

A smart combination of well type, dual gate workfunctions, and
channel (SiGe or Si) enables the construction of two VT flavors for
both the logic devices and SRAM bitcells, while keeping the channel
undoped (Fig.7). These VT flavors and the performance illustrated in
fig.6 are obtained without bias generators for the wells, so that the
design remains similar to a conventional bulk planar one.
Nevertheless, FDSOI offers a unique opportunity for energy
efficient product design in its extended capability of back biasing, as
illustrated in figures 8-11. Well types are adapted to use either a large
reverse back bias (RBB) on LVT minimizing leakage, or a large
forward back bias (FBB) on SLVT maximizing speed (Fig.8) [10].
RBB and FBB ranges in LVT and SLVT, can easily be extended to
the breakdown voltage of the N/P well diode in reverse mode or to
about 5V. The back bias well strap has the same size as a conventional
bulk technology, and the Hybrid CAD layer used to define the
opening in the buried oxide does not induce surface penalties (Fig. 9).
Fig.10 illustrates the dramatic frequency boost using FBB as Vdd
decreases. As a result, devices running at Vdd=0.6V with a 2V FBB
are as fast as devices running at Vdd=0.8V with no back bias,
reflecting an increase of up to 68% in RO frequency gain at Vdd=0.6V
and 2V FBB (Fig.10). Thus, FBB maintains speed with a reduced Vdd,
making FDSOI technology highly suitable for power efficient
applications [5]. At the same dynamic power, 14FDSOI under
nominal conditions (i.e. no back bias application) provides a 30%
frequency boost vs 28FDSOI, or a 55% dynamic power reduction at
the same speed (Fig.11). An additional 40% dynamic power reduction
was experimentally demonstrated by reducing Vdd by ~0.15V and
applying a 2V FBB (Fig.11).
The single-port SRAM offer includes a 0.081m2 high-density
bitcell and two 0.090m2 bitcells one for high speed (HS) and one for
low leakage (LL) memories (Fig.12). A 30A/30pA Icell/ISB with a
Static Noise Margin (SNM) of 166mV (Fig.13) is demonstrated at a
Vdd of 0.9V using the LL 0.090m2 bitcell and +30% Icell is proposed
on the HS one (Fig.12). A low SNM standard deviation (SNM) of
~20mV is achieved thanks to the undoped channel and is consistent
with the sub-0.8V Vmin requirements of the technology (Fig.13).
Back bias in these single PWell bitcells (Fig.7) allows us to tune them
between the slow and fast process corners. It can be used, as shown in
[11], either to boost performance or to reduce leakage (Fig.14), for
process compensation, or to maximize the SNM (Fig.15).

TU
BO

OK

Introduction
As CMOS technology scales down, two paths are pursued by the
industry to overcome the fundamental limits of traditional planar bulk
transistors. One is the introduction of a Tri-Gate or FinFET transistor
at the 22 and 16 nm nodes [1, 2]. These architectures provide
impressive drive currents per footprint at low supply voltages because
of the 3-D conduction channel and excellent electrostatic control.
Conversely, they have high gate and parasitic capacitances,
proportional to the 3-D effective W increase, which negatively
impacts both the speed and active power consumption. Alternatively
FDSOI provides an evolutionary path. First introduced at the 28nm
node [3] and demonstrated using ARM-based chips operating up to a
record frequency of 3 GHz [4], FDSOI includes excellent mismatch
properties, a simplified planar manufacturing process vs 3-D finFET
technology and capitalization of existing design techniques. It also
extends the possibility of back biasing and therefore offers unique
smart solutions for dynamic power optimization [5]. The
technology presented in this paper furthers the appeal of FDSOI to the
14nm node.

gate pitch (CPP) (Fig.3). Since gate-to-drain capacitance (Cgd) is of

high importance in RO effective capacitance (Ceff), as shown in Fig.4,
spacer, poly thickness and raised source-drain epitaxy are used to
minimize Cgd down to ~0.3fF/m for both n and pMOS devices
(Fig.5). As a result, 14FDSOI technology demonstrates a -20% delay
gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage
and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI
technology (Fig.6).

.C

Abstract
This paper presents a 14nm technology designed for high speed and
energy efficient applications using strain-engineered FDSOI
transistors. Compared to the 28nm FDSOI technology, this 14nm
FDSOI technology provides 0.55x area scaling and delivers a 30%
speed boost at the same power, or a 55% power reduction at the same
speed, due to an increase in drive current and low gate-to-drain
capacitance. Using forward back bias (FBB) we experimentally
demonstrate that the power efficiency of this technology provides an
additional 40% dynamic power reduction for ring oscillators working
at the same speed. Finally, a full single-port SRAM offering is
reported, including an 0.081m2 high-density bitcell and two
0.090m2 bitcell flavors used to address high performance and low
leakage-low Vmin requirements.

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Process Technology and Performance

Table 1 highlights key 14nm FDSOI design rules [6] and
technology features. A 0.55x area scaling with respect to the 28nm
FDSOI technology was achieved with the introduction of local
interconnect and the adoption of fixed layout shapes (or constructs)
[6]. Compared to the 28nm technology, new Front-End process
elements include a dual SOI/SiGeOI N/P channel, a dual
workfunction gate-first HKMG integration scheme and a dual in-situ
doped Si:CP/SiGeB N/P raised source-drain [7]. Additionally hybrid
bulk areas, formed before Shallow Trench Isolation (STI), provide a
space for passive devices and ESD FETs to be built [8] (Table 2). A
perfectly flat bulk to SOI transition is achieved (Fig.1) between these
areas. The strained-SiGe channel (cSiGe) is realized before STI
patterning to avoid SiGeOI over-thinning linked to the Ge
condensation process at active edges [9] (Fig.1). As shown in Fig. 2, a
1% compressive strain has been experimentally measured in the 6nm
thin SiGeOI channel (25%Ge).
cSiGe and SiGeB source-drain implementation in 14nm FDSOI
provides a large pMOS Ieff drive current enhancement when compared
to FDSOI technology at the 28nm node [3]. Ieffs of 330A/m and
405A/m at a Vdd of 0.8V and an Ioff of 20nA/m are demonstrated
for both the pMOS and nMOS transistors in a ring oscillator (RO)
environment. In addition, more than 3 decades of leakage is covered
by tuning Lgate in the 20-34nm range in a 90nm minimum contacted

978-1-4799-3332-7/14/$31.00 2014 IEEE

Conclusion
The leading edge FDSOI technology presented in this paper
illustrates the scalability from the 28nm to the 14nm node. We have
demonstrated a 30% speed boost at the same power, or a 55% power
reduction at the same speed, over the 28nm node. Further, it has been
experimentally demonstrated that FBB dramatically extends the
power efficiency of this technology, making it a highly competitive
technology for low voltage and energy efficient CMOS applications.

2014 Symposium on VLSI Technology Digest of Technical Papers

Key features

28FDSOI

14FDSOI

Min Contacted
gate pitch CPP

114nm

90nm

M1 pitch

90nm

64nm

Std cell area

1X

0.55X

VT flavours

RVT / LVT

LVT / SLVT

Lgate in min CPP

24nm 30nm

20nm 34nm

SOI 7nm

Dual SOI/SiGeOI 6nm

Buried oxide

BOX 25nm

BOX 20nm

Gate

HKMG single metal

HKMG dual WF

Source-Drain

Single Si epi + I/I

Dual epi SiGeB/Si:CP

Ezz

100

10

PMOS
Vdd=0.8V
CPP90nm
Lg=20-34nm

1
0.0%

BOX

Si bulk
-0.5%

50

0.1

0.1
100

200

300

Cdov

10

PWELL

28FDSOI 14FDSOI Freq. @ Istat

0.9V

0.9V

+42%

0.9V

0.8V

+25%

0.9V

0.7V

Same

Static leakage (nA/stg)

14

JN

1E-09

0.2

Vdd=0.9V

1E-10

1E-11

SNM (V)

+30%

16

0.14

14

0.12

12

0.1

10

0.08

0.06

0.04

0.02

1E-12
0

20

40

Bitcell read current Icell (A)

60

0
0.4

0.6

0.8

Vdd (V)

1.2

Cgd=Cdov + Cfr + Cpc-ts

GND

P+

pMOS

Device

Logic
LVT

Pmos
channel

SiGe

Gate WF

Nmos : N
Pmos : P

Nmos : N
Pmos : N

Nmos : P
Pmos : P

Well type

Nmos :
Pwell@GND
Pmos :
Nwell@VDD

Nmos :
Nwell@GND
Pmos :
Pwell@GND

Nmos & Pmos :

Pwell@GND

GND

PD & PG

cSi

PU

Back Bias
capability

Full RBB,
FBB up to
VDD/2

Full FBB

RBB & FBB

GND

SRAM
LL

SRAM
HS

Si
Nmos : N
Pmos: P

P+

nMOS

pMOS

SPWELL

PWELL

Logic
SLVT

P+

P+

Bitcell HS single Pwell

600

FO3 ROs
Silicon data
median values

800
700
600

-200mV

500

+25%

+68%

400

FO3 ROs
Silicon data
median values

FBB up to 2V

300
200

500

+30%

0.9V

0.7V
0.8V

400

-55%

300
0.6V

200

-40%

100

100

0.5V
0

0
0.4

0.5

0.6

0.7

0.8

0.9

150

1.1

250

350

450

550

101 stages RO Frequency 1/2n.p (MHz)

Fig.11: RO Frequency vs Pdyn

for various Vdd and various
FBB up to 2V.

Fig.10: SLVT RO Frequency vs

Vdd for various FBB up to 2V.

0.22

1E-09

18

0.16

Cfr
39%

Fig.7: Schematics and table, highlighting logic & SRAM

devices construction for multi VT and back bias optimization.

900

20

0.090LL

0.18

Gate - Epi

Vdd (V)

Fig.9: Example of 14FDSOI std cell

layout, showing the Hybrid CAD
layer (in red) on a well strap.

Other (M1
etc..)

Bitcell LL single Pwell

Gnd
N

PU

SPWELL

NWELL

pMOS

cSi

nMOS

SLVT flip well

Strap cell with

"Hybrid" CAD layer

Cdov
15%

Fig.4: RO Ceff breakup showing

importance of Cgd (61%).

pMOS

NWELL

Fig.6: FO3 RO delay vs Istat vs

28FDSOI, supporting -20% delay
boost with 100mV Vdd reduction.

Cbox
1%

Cpc-ts

P+

N+

nMOS

Delay (ps/stage)

16

Fig.8: Delay vs Istat for LVT

and SLVT flavors with back
bias application.

Standby Leakage (A)

12

0.2

SNM/SNM

14

X
X

SRAMs
PD & PG

cSiGe

Gnd

TU
BO

12

Delay (ps/stage)

500

GND

Vdd

N+

10

ACTIVE

10

Resistors

7%

LVT regular well

0.3m

cSiGe

nMOS

NWELL

0.1

400

Logic

-20%

Cgd (fF/m)

Fig.5: TEM of NMOS, showing Cgd

components (Cdov + Cfr + Cpc-ts) and
experimental N&PMOS Cgd values.

Ieff (A/m)

FO3 ROs
Vdd=0.8V

300

P+

200

Gnd

nMOS pMOS

Varactors

15%

Fig.3: Ieff vs Ioff at Vdd=0.8V for PMOS & NMOS in ring

oscillator design environment (IVX2, W=0.17m).

Static leakage (nA/stg)

Cfr

10

100

500

FO3 ROs

Cpc-ts

100

400

Ieff (A/m)

Position (a.u)

Fig.2: cSiGe strain characterization by

Nano beam electronic diffraction.

Cgc
13%

Pdyn = Idyn.Vdd.f (a.u.)

40

Si0.75Ge0.25
channel

ESD

0.090HS

0.18

SNM (V)

30

Memory

Cpc-pastRX
10%

OK

20

101 stages RO Frequency 1/2n.p (MHz)

10

10

Standby leakage (A)

I/O & Analog

Hybrid

Bipolars, Diodes

NMOS
Vdd=0.8V
CPP90nm
Lg=20-34nm

.C

Exx
0.5%

1000

Ioff (nA/m)

1.0%

FDSOI

FDSOI

Digital

Fig.1: TEM picture before HK deposition, Table 2: 14FDSOI device

illustrating the cSiGeOI pMOS area and
offer: SOI vs Hybrid bulk.
the SOI/Bulk flat transition.

100

Si0.75Ge0.25
strained at
1.0%

Si

Hybrid bulk

1000

1.5%

BOX 20nm

Si

Table1: Key 14FDSOI ground

rules and technology features.

Ioff (nA/m)

Lattice parameter relative to Si (%)

STI

Channel

2.0%

Device offer

cSiGeOI
6nm

OM

References
[1] C.-H.Jan et al., IEDM 2012,
[2] S.-Y.Wu et al., IEDM 2013
[3] N.Planes et al., VLSI 2012,
[4] Press release, EETimes, Feb 2013,
[5] F.Arnaud et al., IEDM 2012,
[6] H.Shang et al., VLSI 2012,
[7] Q.Liu et al., IEDM 2013,
[8] D.Golanski et al., VLSI 2013,
[9] K.Cheng et al., IEDM 2012,
[10] P.Flatresse et al., ISSCC 2013,
[11] R.Ranica et al., VLSI 2013.

1E-10

0.16
0.14

0.090LL

+18%

0.12

-70%

0.1

1E-11
15

25

35

45

Bitcell read current Icell (A)

Fig.12: Icell vs ISB at Vdd=0.9V for Fig.13: 0.090m2 bitcell SNM Fig.14: Icell/ISB vs FBB and
14FDSOI single port SRAM bitcells. vs Vdd and SNM/SNM vs Vdd. RBB application on single PWell
0.090LL and 0.090HS bitcells.

-1

-0.5

0.5

VPWell

Fig. 15: SNM vs FBB and RBB

application on single PWell
0.090LL and 0.090HS bitcells.

2014 Symposium on VLSI Technology Digest of Technical Papers