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Wednesday,September11,2013

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DFTQ&APart2

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6.Ifweprovidecontrollabilityandobservabilitytotheportsofareaundertest,willit
improvethetestcoverage?Ifyes,howmuch%ageofimprovementcanwesee?
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Ans:yes,wecanseeanimprovementincoverage.Thinkabouttheboundinglogicthatwe
usuallygiveformacros...
theimprovementincoveragewilldependontheinitialcoveragewithoutboundandthenooffaults
inthedesignundertest.
7.WhenboththeTransitiondelayandpath_delaytargetfortransitionfaults,whyweshould
havetwodifferentmethodstodetectthesame?

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Ans:YesbothTransitionandPathdelaywilltargetthetransitionfaults,buttheyaredifferentin
thefollowingways
1)Transitiondelayisrelatedtoslowtoriseorslowtofallfaultsataparticularnode.Whereas
pathdelayisrelatedtoslowtoriseorslowtofallfaultsofaparticularpath.
2)Thereasonfortransitiondelayatanodeissomemanufacturingdefectatthatnode(more
resistivenode).Thereasonforpathdelayissomemanufacturingdefectthatisdistributedthrough
outthepath(moreresistivepath).Letmeexplainthisindetailwithanexample.
Letusassumethatinapaththerearesome10nodes,andthetransitiondelayateachnodeis
thatmuchlesswhichwon'tcreateanytimingviolationinthetransitionATPG.Butinpathdelay
thesedelaysateachnodemightgetaccumulatedandresultinnotmeetingthetiming.Soitis
musttohavepathdelaybesidesTransitiondelay.

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Transitiondelayissimilartostuckatatpg,exceptthatitattemptstodetectslowtoriseandslow
tofallnodes,ratherthanstuckat0andstuckat1nodes.Aslowtorisefaultatanodemeans
thatatransitionfrom0to1onthenodedoesntproducethecorrectresultsatthemaximum
operatingspeedofthedesign.Similarlyaslowtofallfaultmeansthatatransitionform1to0ona
nodedoesntproducethecorrectresultsatthemaximumspeedofthedesign.Transitiondelay
faulttargetssinglepointdefects.

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ThePathdelayfaultmodelisusefulfortestingandcharacterizingcriticaltimingpathsinthe
design.Pathdelayfaulttestsexercisecriticalpathsatspeedtodetectwhetherthepathistoo
slowbecauseofmanufacturingdetectsorvariations.

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Pathdelayfaulttestingtargetsphysicaldefectsthatmightaffectdistributedregionofachip.For
example,incorrectfieldoxidethicknessescouldleadtoslowersignalpropagationtimes,which
couldcausetransitionsalongacriticalpathtoarrivetoolate.

DFTQ&APart4

Ifweattain100%coveragewithtransitionatpgtestthenwedontneedtodothepathdelaytest.
Butthisisnotthecaseinmostofourdesigns.ThenhowcanweGUARANTEEthatallthe
criticalpathsaretargetedbyTransitionATPG

DFTQ&APart7

sowegivethecriticalpathtotheatpgtoolandtellittogeneratepatternsforit

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thisiscalledpathdelay.
8.WhatisBurnintest?Whyisitdone?
Ans:Burninistheprocessbywhichdeviceinfantmortalityfailuresare

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acceleratedthroughapplicationoftemperatureandstressvoltagesfor
specificperiodsoftime.Thegoalofburninistostressthedeviceasmuch

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aspossibletherebyacceleratingdeviceinfantmortalityrate.Sincescan

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DesignForTest:DFTQ&APart2
basedtesthashighercoverage,scantestvectorsareusedtostressthelogic
portionofthedevice.Thiscaneitherbedonebyperformingdevicelevel
ATPGbyapplyingexternaltestpatternsononchipLBIST.MemoryBISTis

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usedformemories.
Burnintestisthetechniqueofestimatingthelifetimeofthechipbyprovidingstressintheform
temperature,voltageandcurrent.
Hightoggledatpgvectorsisgeneratedtosensitizetheinternalnodesofthechipsothatchipwill
getmorestress

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.BurninmoniorpinisavailabeforeverySoCtochecktheinternalstatusintheformof
pulses.Chipwillgivepulsestillthedeviceburnout..
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9.WhydowehavedifferentkindsofSDF'slikePrimeTimeSDFandVerilogSDFwhen
thereisanOpenVerilogInternationalstandard?

Followers(55)Next

Ans:TherearenodifferentkindofSDFlikePrimetimeSDForVerilogSDF.
Whenadesignissynthesizeditcreatesnetlist,whichismadeoflibrarycellsonly.Thelibrary
cellshavepathdelays(InputtoOutput)andtherearealsointerconnectdelayinnetlist.SDF
meansStandardDelayFormat.SoSDFbasicallycontainsthecellpathdelayandInterconnect
delaysbetweencells.TheSDFformatcanberead/understoodbyallSTA/simulationtools.
Generarally(1)theSDFcanbegeneratedusingSynthesis(dc_shell)/STA(pt_shell).ThisSDFsare
usedforinitialTiminganalysisandgatesimulation.(2)postroutetoolsalsogeneratesSDF(or
spefandthenyoucangenerateSDFfromspef)files.TheseSDFareusedforfinalTiming
Analysisandfinalgatesimulationforsignoff/tapeout.
Eachlibarycellcanhavemax,minortypicaldelay.soyoucangeneratedSDFbasedonthis
delayandhavedifferentSDFformaxdelayormindelayortypicaldelay,butyoucannothave
primetimeSDForVerilogSDF.
10.IfforaDFTproductionsetwehavebothPATHDelayandTransitionpatternswhich
schemeshouldbedonefirst?
Ans:ItsalwaysbettertodoPath_delayfirstandthenthetransitiondelay.

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Path_delaystartflopandendfloparegivenbytheuser.(i.e)transitionthroughawelldefined
path(Moreeffective)
TransitionStartandendflopisdecidedbythetool,sotrasitionmayhappenthroughashorteror
longerpath(Lesseffective)
1)pathdelaybasicallytargetsforallthecriticalpathsinthedesign.
2)Generatethepath_delaypatternsforallthecriticalpathsinthedesignandwritedownthefaults
forthesame.

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Passinganarraytoamethod
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HashMapVsHashtable

3)Generatethetransdelaypatternbyloadingthefaultsonthepath_delay,suchthatthefaults
detectedinthepath_delayarenotRetargeted.
4)Themajorreasontofollowtheabovesequenceisintransdelaywearenotsureweathera
transitionhasreallyhappenedthroughthecriticalpath.
(A)IfwedothetransitionATPGfirst,wearenotsurewhetherthetransitionhashappened
throughthecriticalpath,Insuchcasewemaynothavepatternwhichmaycatchthefaultthrough
thecriticalpath,butthefaultmaybedetectedthroughsomeothershorterpathswhichmayadd
thefaultstothedetectedlist.
(B)Ifwerunapath_delayaftertheabovestep(A)thenwemayhaveapatternforthecritical
path,butitleadstothepatternredundancybecausewehavealreadyatransition
patternforthesamefault.
11.WhatdowemeanbyfaultsimulationinDFTterminology?
Ans:Faultsimulationconsistsofsimulatingacircuitinthepresenceoffaults(logicalfaults).
Comparingthefaultsimulationresultswiththoseofthefaultfreesimulationof
thesamecircuitsimulatedwiththesameappliedtest,wecandeterminethe
faultsdetectedbythattest.

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Thereareseveraltypesoffaultsimulationtechniquessuchasserialfaultsimulation,parallelfault
simulation,deductivefaultsimulatione.t.
12.WhatismeantbycoverageinDFTterminology?
Ans:Thetermcoveragecanbebraodlyclassifiedas:
1.FaultCoverage:Thisisthetotalnumberofdetctedfaults(duingtesting)dividedbythetotal
numberoffaultsinthedesign.
2.Testcoverage:Thisisthetotalnumberofdetectedfaultsdividedbythenumberoftestable
faultsinthedesign.
Testablefaultsarethefaultsinthedesignthatcanbetestedandobservedbythepatternsused
duringtesting.
Pleasenotethat,heretheword"faults"referstomanufacturingdefects,asDFTdoesnotmerely
targetfunctionalfaults,butratherfocussesoncircuitstructure.
CoverageCalculationsareusedtomeasuretheeffectivenessoftestpatternsandtestgeneration
foragivensetoffaults.
Ex
ABasicANDGatehassixfaults
SA1/SA0InputA
SA1/SA0InputB
SA1/SA0OutputY
TotalfaultsforabasicANDgateis6
Coveragecalculationgoesonhowmanyfaultsweareabletodetectonthesame.
TestCoverageisapercentagedetectedofalldetectablefaultsandgivesthemostmeaningful
measureoftestpatternquality.
TestCoverage=DT+(NP+AP)*PT_credit)/(totalfaultsUD(AN*AU_credit).
FaultCoverage:thefaultcoverageisthepercentagedetectedofallfaults.itgivesnocreditfor
undetectablefaults.
FaultCoverage=(DT+(NP+AP)*PT_credit)/totalfaults.
DTDetected
DRdetectedrobustly
DSdetectedbysimulation
DIDetectedbyimplication
PTPossibltydetected
APATPGuntestablepossiblydetected.
NPnotanalyzed,possiblydetected.
UDUndetectable
UUundectableunused
UTUndectabletied
UBundetectabletied
URundettableredundant
AUATPGuntestable
ANATPGuntestablenotdetected.
NDnotdetected

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NCnotcontrolled.
NOnotobserved.
13.WhatisIDDQTesting?Whyisitdone?
Ans:IDDQTestingcandetectcertaintypesofcircuitfaultsinCMOScircuitsthataredifficultor
impossibletodetectbyothermethods.
IDDQtesting,whenusedwithstandardfunctionalorscantesting,providesanadditionalmeasure
ofqualityassuranceagainstdefectivedevices.
IDDQtestingreferstotheintegratedcircuit(IC)testingmethodbaseduponmeasurementof
steadystatepowersupplycurrent.IddqstandsforquiescentIdd,or
quiescentpowersupplycurrent.MajorityofICsaremanufacturedusingcomplementarymetal
oxidesemiconductor(CMOS)technology.Insteadystate,whenallswitchingtransientsare
settleddown,aCMOScircuitdissipatesalmostzerostaticcurrent.Theleakagecurrent
inadefectfreeCMOScircuitisnegligible(ontheorderoffewnanoamperes).However,incase
ofadefectsuchasgateoxideshortorshortbetweentwometallines,aconduction
pathfrompowersupply(Vdd)toground(Gnd)isformedandsubsequentlythecircuitdissipates
significantlyhighcurrent.Thisfaultycurrentisafewordersofmagnitude
higherthanthefaultfreeleakagecurrent.Thus,bymonitoringthepowersupplycurrent,onemay
distinguishbetweenfaultyandfaultfreecircuits.
WhydoIDDQTesting?
Forfunctionaltesting,atesterappliesasequenceofinputdataanddetectstheresultsinthe
sequenceofoutputdata.Then,theoutputsequenceiscomparedagainsttheexpectedbehavior
ofthedevice.Anadvantageoffunctionaltestingisthatitexercisesthedeviceasitwould
actuallybeusedinthetargetapplication.However,thistypeoftestinghasonlyalimitedabilityto
teststheintegrityofadevice'sinternalnodes.
withfunctionaltestingonly,aninternaldefectcouldslidebyundetected.
Themethodologyforscantestingisallthesequentialelementsofthedeviceareconnectedinto
chainsandusedasprimaryinputsandprimaryoutputsfortestingpurposes.Usingautomatictest
patterngeneration(ATPG)techniques,youhavethecapabilitytotestamuchlargernumberof
internalfaultsthanwithfunctionaltestingalone.ThegoalofATPGistosetallnodesofthecircuit
toboth0and1,andtopropagateanydefectstonodeswheretheycanbedetectedbytest
equipment.
Usingbothfunctionalandscantestingyougreatlyincreasesyouroddsatfindinganinternal
defect,butwhatifthedefectisnotcontrollableorcan'tbeobserved?ThatiswhereIDDQtesting
canhelp.
14.Ifoneneedstodosynthesis/STAwithscanreplacedFF(notstitched)andneeddo
generatetimingandotherreports.WhatshouldbevaluesofSE,SIandSOpinssince
designisnotstitched?
Ans:WeneednotconstraintheSE,SIandSOpinsforsynthesis/STAofascanreplacedbut
notstitcheddesign.ButwewillnotbeabletodoanytestrelatedSTA.
15.Canyoubrieflydescribethepointstobeconsidered,whilereorderingthescanchain
inPhysicalDesign?
Ans:Scanchainreorderingneedstorespect3importantLogicalconstraints.
1.Clockdomaintimingconstraints
2.Userspecifiedscansegmentpositions
3.Minimizingclockdomaintraversals
eachactiveedgeofeachclockisconsideredtobeinaseparateclockdomain.Bothedgesofa
clockandclockswithdifferenttimingsmaybeusedtocontroledgetriggeredscanflipflopsofa
scanchain.
Inordertoconstructfunctionalscanchains,twoconsecutivescanflipflopsAandB(Aserially
drivingB)
1)mustbeclockedatthesametimeor

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2)BmustbeclockedbeforeA.
Inthefirstcase,wesaythatAandBhavecompatibleclockdomains.
Inthesecondcase,wesaythatAandBhaveincompatibleclockdomains.
Theprecedencerelationshipbetweenscanflipflopsimposedbyclockdomaintimingsis
translatedatthescansegmentlevel.Captureandlaunchtimesforascansegmentare
respectivelydeducedfromthecapturetimeofitsfirstscancell(drivenbyitsscaninput)andthe
launchtimeofitslastscancell(drivingitsscanoutput).Therefore,theprecedencerelationship
betweenscansegmentscanbeestablished,andthusrespectedduringscansegments
reordering.Userspecifiedscansegmentpositionsarerespectedduringscanreorderingunless
theyviolateclockdomaintimingconstraints.
Thelastconstraint,minimizingclockdomaintraversals,takespriorityonphysicaldesign
informationbecausewewantourapproachtobeminimallyintrusiveintermofadding
synchronizationlatches.Onlyscansegmentswithcompatibleclockdomainsarereordered.
Reorderingasetofscansegmentswithcompatibleclockdomainsconsistsof:
1.identifyingandmarkingthesetofclusterscontainingthescansegments.
2.Determiningtheentryandexitpointsbetweenwhichthescansegmentsaregoing
tobereordered.
3.Orderingthepreviouslyidentifiedclustersbetweentheentrypointandexitpoints.
4.Reorderingscansegmentswithineachoftheorderedclusters.
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