Professional Documents
Culture Documents
Spring 2011
5. Finite State Machine Design
Web: http://www.cs.columbia.edu/~martha/courses/3827/sp11/
AYellow
BYellow
BGreen
Transitions: Arcs
AGreen
BYellow
AYellow
BGreen
Current State
Inputs
Next State
TA
TB
AGreen
AYellow
AGreen
AGreen
AYellow
BGreen
BGreen
BYellow
BGreen
BGreen
BYellow
AGreen
Inputs
State
S1
S0
AGreen
AYellow
BGreen
BYellow
Next State
S1
S0
TA
TB
S1
S0
AGreen
AYellow
AGreen
AGreen
AYellow
BGreen
BGreen
BYellow
BGreen
BGreen
BYellow
AGreen
output encoding
Output
State
Encoding
Green
Yellow
Red
LA
LB
State
S1
S0
LA1
LA0
LB1
LB0
AGreen
AYellow
BGreen
BYellow
red light
Parade FSM
Unfactored FSM
Factored FSM
Write Boolean equations for the next state and output logic
Sketch the circuit schematic
output
CL 2
N
SY
N
SY
input
N
SY
CL
YN
S
A
FFs
N
SY
MOORE
input
AS
C
N
Y
CL 1
AS
C
N
Y
FFs
SY
NC
output
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Unused states: extra state encodings (e.g., using 3 FFs to represent 6 states
leaves 2 unused states) can be treated as dont care values and used to
simplify the combinational logic
State minimization: two states are equivalent if they transition to the same or
equivalent states on the same inputs (while producing the same outputs in the
case of a Mealy machine)
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