Chapter 5

Interrupt Interface of the 8088 and 8086

Microprocessors

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Mechanism, Types, and Priority

Quickly changing the program environment

Either interrupt from within the processor or from
an external device.
Processor suspend what it is doing in the main
part of the program and passes control to a
special routine.
Interrupt service routine.

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Mechanism
Main Program
Instruction N

Interrupt 32 occurs
during execution of
instruction N in the
main Program

Instruction N+1
:
:
End of Program

Service Subroutine

Service routine
for interrupt 32
Return
Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Priority

Priority is set as below

Increasing
Priority

Reset
Internal interrupts & Exceptions
Software interrupts
Nonmaskable interrupts
External interrupts

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Priority Cont.

Lower priority has to wait.

Example 1,
If the 8088/8086 is servicing interrupt 50 of the
External Hardware. What other interrupts can be
serviced:

Answer

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Activation Mechanism

Up to 256 interrupts
Divided into five groups:

External Hardware interrupts
INTR

Nonmaskable
NMI
Software interrupt
INT n instruction
Internal interrupt
Internal signals / TEST
Reset
RESET

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

The 8088/8086 Pin Layout

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

The Status Register

A 16 bit register to hold indicator bits. Not all bits are used.
11

10

OF

DF

IF

TF

SF

ZF

AF

PF

CF

Carry Flag
Parity Flag
Auxiliary Carry
Zero
Sign Flag
Trap Flag
Interrupt Enable
Direction Flag
Overflow Flag

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Steps to Serve an Interrupt

On interrupt:
1.
2.
3.
4.
5.

Old flags are saved on the stack.

Then IF & TF are cleared.
Old CS & IP pushed onto the stack.
New CS & IP read from memory
Program execution resumes at CSnew:IPnew

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Vector Table

Address Pointer Table

3FE
Vector 3 Breakpoint
Vector 2 NMI

1Kbyte ROM
06

CS1

04

IP1

02

CS0 Base

00

IP0 offset

Processors & Assembly Language

Vector 1 Single Step

Vector 0 Divide Error

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Vector Table

Example 2,
What is the address of the interrupt INT 50, find
the CS and IP address

Answer:

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Software Interrupts

Service subroutines are initiated in response to

the execution of a software interrupts
instructions.
Not an event in external hardware.
INT n initiate a software interrupt
Software interrupts are of a higher priority than
external interrupts.

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Software Interrupt Instructions

INT n:
Software interrupt instruction.
Program will transfer the the subroutine pointed to by
vectors.

Steps for INT n:

1.
2.
3.
4.

MPU saves old flags onto stack.

Clears TF, IF.
Saves CS & IP.
Reads IP50 & CS50 from address 000C8H &
000CAH.
5. CS:IP starts to fetch.

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Software Interrupt Instructions Cont.

IRET

Interrupt Return
Must be used at the end of each ISR
Causes old value of flags to be popped
CS & IP are popped

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

External Hardware Interrupts

Interrupt-enable Flag bit

IF: affects only the external hardware interrupts
to Enable/Disable them.
External input = INTR
During execution of interrupt, the Processor
clears IF

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

The Status Register

A 16 bit register to hold indicator bits. Not all bits are used.
11

10

OF

DF

IF

TF

SF

ZF

AF

PF

CF

Carry Flag
Parity Flag
Auxiliary Carry
Zero
Sign Flag
Trap Flag

Interrupt
Enable
Direction Flag
Overflow Flag

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

16

External Hardware Interrupt Instructions

CLI & STI:

Manipulate the interrupt flag through
software
STI enables the external interrupt request
(INTR)
CLI disables the external interrupt request
(INTR)

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Nonmaskable Interrupt

NMI:
1. Cannot be masked out with the interrupt
flag
2. Apply logic 1 at the NMI input, not INTR
input.
3. NMI input is positive edge-triggered

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Nonemaskable Interrupts Cont.

0  1 on NMI input, NMI flip-flop MPU is set

Must be active two consecutive clock cycles
Current flags, CS & IP pushes into stack
NMI vectors from type 2
NMI type of interrupts must respond to
immediately (power failure & memory-read error)

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Reset Interrupt

Reset: hardware means of initializing the MPU.

Happens at power up, but PC allow time for
warm up
This will synchronize the Reset with the clock.
MPU when it sees RESET, terminates
operations, Bus = Z state

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Internal Interrupts Functions

Divide Error:
IDIV or DIV larger than specified destination
Type 0 interrupt

Overflow Error:

Results of any arithmetic operation

Not like Divide error, transfer is not automatic
INT 0 after arithmetic instruction
Type 4
Could cause a message to be displayed

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Internal Interrupt Instructions

INTO

Interrupt-on-overflow
Must be included after arithmetic instructions
Type 4 interrupt
IP at 0010H & CS at 00012H

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Internal Interrupts Functions Cont.

Single Step:

TF is set, the single step operation is enabled

Software control
Type 1
Program can be executed one instruction at a
time-debugging
Could include WAIT inside the subroutine

Breakpoint:
CC instructions
Cause execution to stop at a certain location

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

The Status Register

A 16 bit register to hold indicator bits. Not all bits are used.
11

10

OF

DF

IF

TF

SF

ZF

AF

PF

CF

Carry Flag
Parity Flag
Auxiliary Carry
Zero
Sign Flag

Trap Flag
Interrupt Enable
Direction Flag
Overflow Flag

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

24

Interrupt Instructions Cont.

HLT & Wait:

Halt: Processor suspends operation & initiates idle
states
Wait: Processor checks the logic level of TEST
input prior to going to idle state only if TEST = 1
Processor will go idle state.
While in idle state, Processor checks the login
level at TEST it goes to zero execution resumes.

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy

Interrupt Instructions
Symbol

Meaning

Format

Operation

Flags affected

CLI

Clear interrupt flag

CLI

0  (IF)

IF

STI

Set interrupt flag

STI

1  (IF)

IF

INT n

Type n software
interrupt

INT n

Flag  ((SP)-2)
0  TF, IF
CS  ((SP)-4)
(2 + 4.n)  (CS)
(IP)  ((SP) 6)
(4.n)  (IP)

TF, IF

IRET

Interrupt Return

IRET

(SP)  (IP)
((SP) + 2 )  (CS)
((SP) + 4 )  (Flags)
((SP) + 6 )  (SP)

All

INTO

Interrupt on overflow

INTO

INT 4 steps

TF, IF

HLT

Halt

HLT

Wait for external interrupt or

reset to occur

None

WAIT

Wait

WAIT

Wait for TEST input to go active

None

Processors & Assembly Language

Dr. Bassel Soudan &

Dr. Ali El-Moursy