Professional Documents
Culture Documents
Course Code
Product
OEB9B2102
USN9810
V900R011C02
1.00
Developer/Modifier
Time
Approver
New/Update
Version
Page 1
USN9810(MME&SGSN)
Hardware&Software
System
www.huawei.com
References
HUAWEI USN9810 Hardware Description
USN9810 Hardware System_SGSN_ISSUE0.1
Page 3
Objectives
Upon completion of this course, you will be able to:
Describe the USN9810 hardware structure.
Describe the USN9810 software structure.
Learn board functions, external interfaces, and cable connections.
Learn the signaling processes between boards.
Page 4
Contents
1. Background Knowledge of the USN9810
2. System Structure of the USN9810
3. Cable Connection of the USN9810
4. Service Flow of the USN9810
Page 5
Contents
1. Background Knowledge of the USN9810
2. System Structure of the USN9810
3. Cable Connection of the USN9810
4. Service Flow of the USN9810
Page 6
Control plane
User plane
BTS
BSC/PCU
MME/SGSN
PCRF
UMTS
NodeB
RNC
Operator
Service
Network
LTE
S-GW
eNodeB
P-GW/GGSN Corporate
Services
CDMA
BTS
BSC/PCF
PDSN/HSGW
Page 7
Control Plane
User Plane
HLR
VPLMN
2G/3G Network
APN-GU
Gp
Gr
GnGp-SGSN
HSS
APN-L
APN-GUL
Gr
S6a/S6d
Gb
GGSN
GERAN
Iu
HPLMN
2G/3G Network
APN-GU
Gn
GnGp-SGSN
Gb
Gn
Gn
UTRAN
HPLMN
LTE/SAE Network
Iu
S3/S16/S10
S10
MME
S1-MME
SGSN/MME
APN-GUL
USN
S4/S11
(SGSN/MME)
S1-U
E-UTRAN
Internet
Gn
S6a/S6d
S5
APN-L
APN-GUL
Serving GW
VPLMN
LTE/SAE Network
PDN GW&GGSN
HSS
S8
S6a
APN-L
PDN GW
Copyright 2010 Huawei Technologies Co., Ltd. All rights reserved.
Page 8
APN-L
HSS
Port
Protocol
Gb
E1/T1/channelized STM-1
SNDCP/LLC/BSSGP/NS/FR or IP (user);
SM/GMM/LLC/BSSGP/MS/FR or IP (control)
STM-1/STM-4
RANAP/SCCP/MTP3B/SAAL/M3UA/SCTP
Iu-PS
S1-AP/SCTP/IP
S6a
Diameter/SCTP/IP
Gr/Gd/Lg/Gf
Gs
MAP/SS7
E1/T1 /channelized STM-1
10 M/100 M/1000 M Ethernet
BSSAP+/SS7
Ge
CAMEL III/SS7
Gn/Gp/S11/S10
GTP/UDP/IP
Ga
X1-1/X2/X3
GTP'/UDP/IP
TCP(UDP)/IP
Page 9
Contents
1. Background Knowledge of the USN9810
2. System Structure of the USN9810
3. Cable Connection of the USN9810
4. Service Flow of the USN9810
Page 10
Contents
2. System Structure of the USN9810
2.1 Hardware Introduction
2.2 Hardware Logical Structure
2.3 Software Logical Structure
Page 11
E
T
I
E
C
U
U E E E T T E E E P
S T T T M M T T T F
I I I I I I I I I I
O E E E S S E E E E
M C C C W W C C C P
U U U U U U U U U U
SMU/SDM
SMU/SDM
Blank Plane (1U)
Subrack 0(14U)
E
T
I
E
C
U
P
F
I
E
P
U
U
S
I
O
M
U
E
T
I
E
S
U
U E E Q T T E Q Q Q Q Q
S T T X M M T X X X X X
I I I I I I I I I I I I
O E E E S S E E E E E E
M S S S W W S S S S S S
U U U U U U U U U U U U
SMU/SDM
SMU/SDM
Blank Plane (1U)
T8280 subrack
T8290 subrack
Page12
Cabinet
4
3
2
6
Page 13
Subrack
Basic subrack
1. air deflector
3. binding slot
4. power distribution block
5. SDM board area
The basic subrack performs inter-subrack exchange. The basic subrack is mandatory and
numbered from 0.
The service subrack is configured based on user capacity. All the service subracks must be
connected to the basic subrack.
Page 14
Service subrack
1. board slot
Service subrack
Rear view
Service subrack
Front view
Subrack
OSTA2.0 T8280 subrack (front view)
Page 15
Subrack
OSTA2.0 T8280 subrack (rear view)
Page 16
Page 17
Fan Box
Function: The fan assembly implements heat dissipation for the OSTA2.0 subracks. The fan
assembly uses the forced cooling mode. The air intake is at the front bottom part of the chassis
and the air exhaust vent is at the rear top part of the chassis.
The T8280 fan assembly uses the integrated and dual-layer design. That is, two fan
assemblies are configured in each subrack to avoid heat dissipation problems due to single
point of failure. The fans support N+1 redundancy mode. When a fan fails, the system
performance is not affected.
As shown in the figure, the fans are located at the bottom of the chassis in a horizontal manner.
Page 18
70 mm
0 1 2 3 4 5 6 7 8 9 10 11 12 13
280 mm
B U U U U U U S S U U U U U U
A
C S S S S S S W W S S S S S S
K I I I I I I I I I I I I I I
F
R U U U U U U S S U U U U U U
O P P P P P P W W P P P P P P
N B B B B B B U U B B B B B B
T
8U
Page 19
Sw itc h
Se rve r
1 2
3 4
6 7 8 9 10 11 12 13 14
SM M 1
SM M 2
FA N
PEM 1
PEM 2
DC A1
D C B2
DC A2
D C B1
Page 20
Page 21
B1 - B10
Switch
1. input terminal
2. output
terminal
5. RJ45
serial port
6. external Boolean
value interface
Device
Control Switch
SUBRACK2
32 A (4PCS)
SUBRACK1
32 A (4PCS)
SUBRACK0
32 A (4PCS)
Page 22
T8290 Subrack
The T8290 subrack interworks with the ESU. The overall hardware structure of
T8290 is similar to that of the T8280. The differences between the two subracks are
as follows:
Difference Item
T8280
T8290
Power supply
92 W
100 W
186 W
821 W
3481 W
Each subrack is configured with two PEMs. Each PEM supports two lines
of power inputs. The maximum input current of each line is 32 A.
Fan
Page 23
T8290 PDB
Page 24
Page25
NA
3
1
1
1
3
2
2
2
3
Power output
Fan subrack 1
Board
(0, 13)
Power output
Board
(7 to 12)
Board
(1 to 6)
Power output
Power output
Power output
Power output
Page 27
Type
Position
Example
Front board
Rear board
Subboard
Backplane
Page 28
Function
The OMU implements system configuration, maintenance, alarm
management, and performance management functions.
ECU
EPU
ESU
SWU
The SWU exchanges data within a subrack or between subracks over the
Base and Fabric switching planes.
The SMU implements device management, sensor/event management,
SMU
Page 29
Function
As a rear board of the OMU, the USI provides precise time and maintenance GE
interfaces.
The ETI provides various interfaces to interconnect to external devices. The ETI must
be used with the UPB.
LFI
As a rear board of the ECU, the LFI provides encryption and compression functions.
As a rear board of the EPU, the PFI is a broadband interface processing board and
interface)
the PFI interworks with the interface subboards to provide access functions for
broadband interfaces such as ATM, POS, and GE interfaces.
As a data module, the SDM specifies the subrack number using eight-bit DIP switches.
The SDM records the subrack information and system performance parameters.
As a rear board of the SMU, the TMI implements clock distribution.
As a rear board of the SMU, the TSI receives clock signals.
As a rear board of the ESU, the QXI is a broadband interface processing board.
Page 30
Physical Board
OMU
UPBA2/UPBA6
USI
USIA7
ECU
UPBA3
ESU
ESUA0
ETI
ETIA0/SSIA2
LFI
LFIA
EPU
MSPB0
PFI
PFIA0
SWU
SWUA0/SWUA1
TSI
SWIA0
TMI
SWIA1
SMU
SMM
SDM
SDM
QXI
QXIA0
Page 31
It is
recommended
that the OMUs
be installed in
slots 0 and 2 in
the basic
subrack.
The SMM,
SDM, SWU,
and SWI are
mandatory for
each subrack.
Page 32
9 10 11 12 13
Slots 4 and 8
U
S
I
E
T
I
U
S
I
E
T
I
U
S
I
E
T
I
T T
M M
I
I
E
T
I
E
T
I
E
T
I
P
F
I
U
S
I
P
F
I
O
M
U
E
C
U
O
M
U
E
C
U
E
C
U
E S S E
C W W C
U U U U
E
C
U
E
C
U
E
P
U
E
C
U
E
P
U
Slots 5 and 9
Rear board
Backplane
Front board
Page 33
Service subrack
Page 34
Service subrack
Page 35
Physical Board
Position
Function
SMU (shelf
management module)
SMM
Front
board
SDM
Rear
board
UPBA2/UPBA6
Front
board
USIA7
Rear
board
Page 36
Board
slot
SMM slot
Fan assembly
(with air intake)
PDB
Serial
SWI
SWI
SWU
SWU
SDM
SDM
SMM
SMM
FAN
FAN
IPMB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
USI
USI
USI
USI
USI
USI
USI
USI
USI
USI
USI
USI
Page 37
Air exhaust
vent
Interface
board slot
Cable
trough
Power
distribution
module
SDM slot
SMM
SMM: Shelf Management Module.
Function:
The SMM manages all the hardware devices in the subrack.
The SMM implements functions such as device, hot-swap, alarm, log, inventory, and power management.
The SMM supports the KVM Over IP function.
The SMM is located at the rear bottom of the subrack and it has two slots. The SMM works in the 1+1
active-standby mode. The active SMM and standby SMM are connected by dedicated Intelligent Platform
Management Bus (IPMB) and network ports for synchronizing data.
Port:
The SMM provides 40 IPMB ports that are connected to the backplane through which these ports are
connected to the Baseboard Management Controllers (BMCs) of each board.
The SMM provides 4 10/100MBase-T FE network ports. Two ports are connected to the SWUs through
the backplane. One is used for synchronizing the data and status of two SMMs. One is a maintenance port
that is connected to the SMM panel.
The SMM provides an RS232 serial port (COM1) on the front panel.
The USN9810 V900R011C02 version adds SMME that can smoothly replace SMMD. SMME and SMMD have
different exteriors.
SMM
SMMD
SMME
1 Minor Alarm
Indicator
2 Severe Alarm
Indicator
3 Urgent Alarm
Indicator
5 ETH0 Network
Port
6 HOTSWAP
Indicator
7 Ejector Lever
8 Reset
9 Subscriber
Indicator
10 HEALTHY
Indicator
SDM
ETH
COM2
ON
DIP
COM1
FRAME ID
1: ejector lever
6: DIP switches
Indicator:
Indicator
Color
HEALTHY
Health status
Red/Green
of the SDM
Indication
Description
Normal Status
Page 40
SDM (Continued)
The SDM ejector levers are used to plug or fix SDMs. The ejector levers cannot be used to power on or
power off the SDMs. One of the active and standby SMMs can be used to provide power for the SDMs.
DIP switches: The DIP switches are used
to set the subrack number.
OFF:0
ON:1
Subrack No.
0
1
2
3
4
5
1
off
off
off
Off
off
off
2
off
off
off
off
off
off
3
off
off
off
off
off
off
4
off
off
off
off
off
off
5
off
off
off
off
off
off
6
off
off
off
off
on
on
7
off
off
on
on
off
off
8
off
on
off
on
off
on
ON:1
Page 41
OMU
The physical boards of the OMU are the Universal Process Blades (UPB)s.
The OMU implements system configuration, maintenance, alarm management, and
performance management functions.
The OMU supports powerful processing capability and works as a hardware
carrier for service running. The full configuration of the OMU is as follows:
CPU: Two Intel low-power consumption 4-core processors are used. The 4-core
processors support 12 MB L2 cache and 1333 MHz front side bus (FSB). The
CPU provides a transmission rate of 21 Gbit/s.
Memory: Six DDR2 RDIMM memories with 24 GB in total are used. Each
memory supports 4 GB dual ranks and ECC. The highest work frequency is 667
MHz. The memories are compatible with 533 MHz VLR DDR2 RDIMM
backwards.
Hard disk: Two hot swappable 2.5-inch SASs are used. The hard disk capacity is
73 GB or 146 GB. The hard disks are configured before they are delivered to the
sites. The hard disks of the OMU use the RAID 1 technology. Two hard disks
work in mirroring mode.
Subboard: none
Page 42
OMU (Continued)
1
14
2
2
HEALTHY
SYS TEM
HD1-ACT HD1-RAID/ALM
13
12
11
10
9
OOS
6
4
4
8
7
HD0-ACT HD0-RAID/ALM
5
5
USB
COM
2. memory
3. cooling fin
4. processor
5. hard disk
6. main board
4
5
(6) HOTSWAP
indicator
(7) HD0_RAID/ALM
indicator
(8) HD0_ACT
indicator
(9) HD1_RAID/ALM
indicator
(10) HD1_ACT
indicator
(11) SYSTEM
indicator
(12) HEALTHY
indicator
(14) ejector
lever
HOTSWAP
Page 43
USI
1
1
2
USB
11
HEALTHY
10
KVM
OOS
3
4
5
J4
(5) HEALTHY
indicator
(6) cover
(7) GE network
interface
(8) HOTSWAP
indicator
(9) GE network
interface indicators
LAN0
10/100/1000M
LAN1
3
J1
10/100/1000M
10/100/1000M
J2
10/100/1000M
HOTSWAP
LAN0
LAN1
8
LAN0
10/100/1000M
J3
LAN1
10/100/1000M
(2) subboard
connector (J4)
(3) subboard
connector (J1)
(5) subboard
connector (J3)
(6) subboard
positioning hole
External ports:
One USB port: connecting to the KVM
One VGA port: connecting to the display.
More than four GE ports
Page 44
Physical Board
Position
SWUA0/SWUA1
Front board
Function
The SWU exchanges data within a
subrack or between subracks over the
Base and Fabric switching planes.
SWIA1
Rear board
interface)
SWIA0
Rear board
Page 45
Switching Module
0
U
Rear board S
I
Backplane
Front board
1
U
S
I
2
U
S
I
3
U
S
I
4
U
S
I
5 6 7 8
USSU
S WW S
I I I I
9 10111213
UUUUU
SSSSS
I I I I I
UUUUUUSSUUUUUU
P P P P P P WW P P P P P P
BBBBBBUUBBBBBB
SWI
SWI
SDM
SDM
SWU
SWU
SMM
SMM
BASE
FABRIC
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
UPB
USI
USI
USI
USI
USI
USI
USI
USI
USI
USI
USI
USI
Page 46
SWU
The SWU is the switching unit.
Function:
The SMU exchanges data between boards
over the backplane and exchange data
between subracks over the cascading ports
provided by the SWI.
Dual-plane: The SMU supports the Base
plane and GE Fabric plane.
Base plane:
1: OOS indicator
3: SYSTEM indicator
5: SYS COM
configuration serial port
7: LAN2 network port
9: HOTSWAP indicator
Page 47
2: HEALTHY indicator
4: BMC COM
configuration serial port
6: LAN1 network port
8: ejector lever
SWU (Continued)
External ports
Name
Function
Description
The SYS COM serial port uses the RS232 protocol. The
port type is RJ-45. The baud rate is 115200 bit/s. The
SYS COM serial port does not provide any indicators.
By default, the SYS COM serial port is used as the
serial port on the Base plane. You can use the BMC
COM serial port CLI to set the SYS COM serial port as
the serial port on the Base, Fabric, or FC plane.
Maintenance
Page 48
SWU (Continued)
Indicators
Name
Color
Indication
Description
Normal Status
1. OOS indicator
Red/Amber (yellow)
Off
2. HEALTHY
indicator
Board health
Green
3. SYSTEM indicator
Green
Board expansion
9. HOTSWAP
indicator
Blue
Page 49
SWU (Continued)
USN9810 V900R011C02 version has a newly added SWU: SWUB/SWIB. The differences between
SWUB/SWIB and SWUA/SWIA are as follows.
Difference Item
SWUA/SWIA
SWUB/SWIB
Switching Capacity
TMI
LINE CLK
2
3
1000M
LAN0
OOS
LAN1
LAN3
HEALTHY
LAN2
2. BASE GE
interfaces (LAN0
to LAN7)
3. FABRIC GE
interfaces (LAN0 to
LAN7)
5. ejector lever
6. HOTSWAP
indicator
7. HEALTHY indicator
8. OOS indicator
8
7
1000M
LAN4
LAN5
LAN6
LAN7
10/100/1000M
LAN0
LAN1
LAN2
LAN3
10/100/1000M
LAN5
HOTSWAP
LAN4
LAN6
2. positioning pin
3. power connector
4. IO connector
LAN7
1. ejector lever
BITS IN
Page 51
TSI
2
3
1000M
LAN0
OOS
LAN1
LAN3
HEALTHY
LAN2
6
5
1. BASE GE
interfaces (LAN0 to
LAN7)
2. FABRIC GE
interfaces (LAN0 to
LAN7)
3. ejector lever
4. HOTSWAP
indicator
5. HEALTHY
indicator
6. OOS indicator
1000M
LAN4
LAN5
LAN6
LAN7
10/100/1000M
LAN0
LAN1
LAN2
LAN3
10/100/1000M
LAN5
HOTSWAP
LAN4
LAN6
LAN7
1. ejector lever
2. positioning pin
3. power connector
4. IO connector
Page 52
Physical Board
Position
Function
UPBA3
Front board
plane unit)
ETI (E1/T1 interface board)
and charging.
ETIA0/SSIA2
Rear board
MSPB0
Front board
PFIA0
Rear board
forward unit)
PFI (packet
forward interface)
ESUA0
Front board
Unit)
QXI (Quad-port 10GE
Rear Interface Unit)
QXIA0
Rear board
Page 53
A processing module consists of multiple blade servers. The general processing blade
servers are classified into front processing board UPBs and rear interface board USIs.
The UPBs and USIs are located at slots 0 to 5 and 8 to 13.
The USN9810 UPB is classified into UPBA2/UPBA6 (OMU) and UPBA3 (ECU).
0
U
Rear board S
Backplane I
1
U
S
I
2
U
S
I
3
U
S
I
4
U
S
I
5
U
S
I
6
S
W
I
7
S
W
I
8
U
S
I
9
U
S
I
10 11 12 13
U U U U
S S S S
I I I I
U U U U U U S S U U U U U U
Front board P P P P P P W W P P P P P P
B B B B B B U U B B B B B B
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Copyright 2010 Huawei Technologies Co., Ltd. All rights reserved.
Page 54
ECU
The UPB is the universal process blade.
The ECU processes the control plane-related services and charging.
CPU: The ECU uses two Intel Xeon low power consumption and 4-core
processors. The 4-core processors support 4 MB L2 cache and 1333 MHz
FSB. The CPU provides a transmission rate of 21 Gbit/s.
Memory: The ECU uses six FBDIMM DDR2 memories. The total capacity
is 24 GB. Each memory supports 4 GB capacity. The memories support
ECC. The highest work frequency is 667 MHz.
Hard disk: The ECU supports two hot swappable 2.5-inch SASs. Generally,
only a hard disk is configured for the ECU.
Subboard: none
Page 55
ECU (Continued)
1
14
2
HEALTHY
HD1-ACT HD1-RAID/ALM
6
4
4
8
7
HD0-ACT HD0-RAID/ALM
USB
COM
2. memory
3. cooling fin
4. processor
5. hard disk
6. main
board
(6) HOTSWAP
indicator
(7) HD0_RAID/ALM
indicator
(8) HD0_ACT
indicator
(9) HD1_RAID/ALM
indicator
(10) HD1_ACT
indicator
(11) SYSTEM
indicator
(12) HEALTHY
indicator
SYS TEM
13
12
11
10
9
OOS
4
5
HOTSWAP
Page 56
ETIA0
1
1. captive screw
2. shielding finger
3. ejector lever
4. OOS indicator
5. HEALTHY
indicator
6. interface on the
sub-board
7. HOTSWAP
indicator
8. 8 kHz clock
port
J27/J28
J6
J25/J26
(2) subboard
connector (J27/J28)
(4) subboard
connector (J25/J26)
(5) subboard
positioning hole
(3) subboard
connector (J6)
Page 57
SSIA2
Figure 1 SSIA2 panel
Function:
1. Each TSCA supports the mapping from 63 E1 or 84 E1s to the STM-1.
2. Each SSIA2 consists of a TSCA and an ETMA. The SSIA2 provides an
external channelized optical port and an E/1T1 port.
3. The SSIA2 provides the line clock extraction function and sends the
clock signals to the SFU over the clock port on the panel.
4. The SSIA2 supports hot swapping.
Indicator:
Name
Color
Indication
Description
4. OCS indicator
Red/Amber
Service
indicator
5. HEALTHY
indicator
Red and
green
Board health
8. HOTSWAP
indicator
Blue
Hot swapping
status
9. Optical port
indicator
Green
Work status of
the optical port
Page 58
SSIA2 (Continued)
External ports
Name
Description
6. E1/T1 port
The board provides the DB-78 port as the E1/T1 port and the subboard identifier is E1/T1_0_15.
7. Optical port
The board provides two RJ-45 clock ports. The board extracts 8K clock signals from E1 lines and
transmits the clock signals to the active and standby SWIA1s. Two ports are identified as 8K_OUT0 and
8K_OUT1 from top to bottom.
1. Captive screw
3. Ejector lever
4. OOS indicator
5. HEALTHY indicator
6. E1/T1 port
7. Optical port
8. HOTSWAP indicator
Page 59
SSIA0
Function
1. Each TSCA supports the STM-1 payload mapping of 63 E1 or 84 T1
ports.
2. Each TSCA supports two channelized STM-1 interfaces and one is
used to enable transmission over SDH through E1/T1 interfaces.
3. The SSIA0 provides the line clock extraction function and sends the
clock signals to the SFU over the clock port on the panel.
4. The SSIA0 supports hot swap.
5. The SSIA0 provides the GEA1, GEA2, and GEA3 encryption functions.
Page 60
SSIA0
(Continued)
1. captive screw
2. Board label
3. Ejector lever
4. OSS indicator
5. HEALTHY indicator
6. Optical port
7. HOTSWAP indicator
Indicators:
Name
OSS indicator
Color
Indication
Red/Amber
Service indicator
Description
The OSS indicator is red and amber in European mode and American mode
respectively.
Run SET OSSCOLOR to set the color of the OSS indicator according to specific
areas.
Off: The board works properly.
On or blinking: The board is not in the service state.
HEALTHY indicator
The color of this indicator depends on the working status of the board.
Off: The board is not powered on.
Green: The hardware system has no alarms.
Red: The board is faulty.
Blinking in red: The hardware system has alarms.
There are 3 types of alarms according to the blinking frequency of the HEALTHY
indicator.
Minor alarm: The indicator blinks at a frequency of 0.5 Hz.
Severe alarm: The indicator blinks at a frequency of 1 Hz.
Urgent alarm: The indicator blinks at a frequency of 4 Hz.
Page 61
EPU
The multimedia service process unit (MSPB), wherein B indicates the board
version, works as an SPU. Service application software can be installed on
the MSPB to process data services.
The MSPB supports a multi-core processor that uses the multi-core and
multi-thread architecture.
The MSPB supports two DIMM memory boards. The capacity of each
memory board is 4 GB. The capacity of the board memory is 8 GB.
The MSPB provides two Ethernet 10/100/1000 M Base-T Base ports.
The MSPB provides two Ethernet 1000 M Base-B Fabric ports.
The MSPB provides one Ethernet 1000 M Base-B Update port.
The MSPB provides a commissioning network port.
The MSPB provides a commissioning serial port on the front panel.
Page 62
EPU (Continued)
1
8
2
7
6
5
2
1. memory
2. cooling fin
3. processor
4
3
2. subboard
filler panel
3. COM serial
port
4. HOTSWAP
indicator
5. ACT
indicator
6. HEALTHY
indicator
7. OOS
indicator
8. ejector
lever
HOTSWAP
C0M
1. captive
screw
Page 63
PFI
1
J27/J28
J6
1. captive screw
2. shielding finger
3. ejector lever
4. OOS indicator
5. HEALTHY
indicator
6. interface on the
sub-board
7. HOTSWAP
indicator
J25/J26
(2) subboard
connector (J27/J28)
(4) subboard
connector (J25/J26)
(5) subboard
positioning hole
(3) subboard
connector (J6)
Page 64
Board: Subboard
Name
Position
Function
AICA
PFIA0
EECA
PFIA0
EFCA
PFIA0
Page 65
ESU
The features of the ESU are as follows:
--Integrates control and forwarding functions.
--Possesses strong service processing and forwarding capability.
--Supports all types of rear boards that can interwork with the ECU or EPU.
--Supports QXI and provides the 10 GE interface.
Hardware description
Supports one Intel Xeon six-core Westmere-EP processor with full power consumption
Provides six DDR3 registered dual in-line memory module (RDIMM) memory slots. Each RDIMM providing the
capacity of 8 GB, with the maximum total capacity of 48 GB.
Two 10/100/1000 M BASE-T Ethernet Base interfaces connecting to the backplane and used for communicating with
the switch blades, supporting boards started from the network.
Two 20 G RXAUI Ethernet Fabric interfaces connecting to the backplane and used for communicating with the switch
blades
One update interface connecting to the backplane and used for communicating with other processor boards. Data
types can be customized.
Four 10 Gbit/s transmission channels connecting to the interface boards for connecting external devices
Four 1 Gbit/s transmission channels connecting to the interface boards for connecting external devices
Provides one serial advanced technology attachment (SATA) port for connecting one solid-state drive (SSD).
ESU (Continued)
1: Board label
2: Ejector lever
3: HOTSWAP indicator
5: USB interface
6: HD_ALM indicator
9: HEALTHY indicator
QXI
The QXI provides external interfaces for the ESU to connect to external devices. The QXI
provides four GE and four10 GE external interfaces to transmit data to other external devices.
1 Board label
2 Ejector lever
3 OOS indicator
4 HEALTHY
indicator
7 HOTSWAP
indicator
5 SFP/SFP+
6 SFP interface
interface
8 LINK indicator -
3 SFP/SFP+
interface
4 SFP interface 5 I/O connector 6 Power connector
7 Positioning
pin
Page68
Contents
2. System Structure of the USN9810
2.1 Hardware Introduction
2.2 Hardware Logical Structure
2.3 Software Logical Structure
Page 69
Overview
Page 70
Page 71
IPMB
IPMB plane (device management plane)
Direction of the management message flow
SWU
SWU
OMU
OMU
SWU
UPB
CSCF
Base
OMU
OMU
Fabric
UPB
USI
UPB
USI
Subrack 0
SWU
SWU
SWU
SMM
SMM
SWU
SWU
SWU
SWU
CSCF
UPB
CSCF
UPB
2
Subrack
1
SMM
2
Subrack
2
Page 72
SMM
SWU
SWU
CSCF
UPB
CSCF
UPB
Page 73
Core
Lanswitch
SWU
SWU
SWU
SWU
SWU
SWU
SWU
UPB
OMU
OMU
USI
USI
USI
USI
SWU
SWU
CSCF
UPB
CSCF
UPB
CSCF
UPB
Subrack
2
2
GE/FE
Maintenance
Lanswitch
LAN Switch
Management and
maintenance
terminal
0 0
Subrack
GE/FE
Maintenance
Lanswitch
LAN
Switch
IP Network
Page 74
SWU
SWU
Plane (device
management plane)
Fabric plane (service plane)
Base plane (management plane)
CSCF
UPB
USI
CSCF
UPB
CSCF
UPB
UPB
USI
GE
GE
Signaling
Lanswitch
LAN Switch
IP Network
Page 75
Page 76
Time Synchronization
Note:
1. The RTC module is located on
the OMU rear board (USI7).
2. The OMU sets and reads board
time using the CPU.
3. The intra-subrack and intersubrack boards synchronize time
using the NTP protocol on the
Base plane.
4. The RTC module provides a
level-2 (0.4 PPM) oscillator that
ensures time precision upon NTP
server failure.
NTP server
OMS
(NTP+RTC)
SWU
SWU
UPB (NTP)
SWU
SWU
UPB (NTP)
UPB (NTP)
OMS
(NTP+RTC)
SWU
SWU
UPB (NTP)
SWU
SWU
UPB (NTP)
UPB (NTP)
Page 77
SWU
SWU
SWU
SWU
SWU
SWU
SWU
CSCF
UPB
SWU
SWU
OMU
OMU
OMU
OMU
USI
USI
USI
USI
UPB
CSCF
UPB
CSCF
CSCF
UPB
Subrack 2
GE/FE
Subrack 0
GE/FE
Maintenance
LAN Switch
Maintenance
LAN Switch
IP Network
Page 78
Contents
2. System Structure of the USN9810
2.1 Hardware Introduction
2.2 Hardware Logical Structure
2.3 Software Logical Structure
Page 79
Software Architecture
Page 80
Page 81
OMU
OMP(1)
SMM
MON(1)
IMU(1)
SMU(1)
ECU
ESU
EPU
SPP(12)
LCP(1)
SGP(12)
UIP(1)
GBP(12)
CDP(1)
LLP(12)
AMP(1)
SPP(8)
SGP(8)
LCP(1)
GBP(8)
UIP(1)
PCP(1)
LLP(8)
CDP(1)
PFP(1)
IMU(1)
MON(1)
IMU(1)
GTP(8)
UMP(1)
UPP(1)
MON(1)
IMU(1)
Page 82
MON(1)
Function
MON
IMU
Page 83
Process: OMU/SMM
Process
Function
OMP
SMU
Page 84
Process: ECU
Process
Function
SPP
The SPP is the main process for processing SGSN or MME services on the control
plane and controlling various services.
SGP
The SGP processes the signaling transmitted over the Iu and S1-MME interfaces
on the control plane and SIGTRAN protocol stacks.
GBP
LLP
CDP
The CDP supports charging data storage and provides Ga interfaces. The CDP
processes half-finished CDRs into finished CDRs. The CDP reports CDRs to the
CG. When all the connected CGs fail, the CDP saves the CDRs in the local hard
disk.
LCP
The LCP controls the heartbeat handshake between the license control center and
the Gb interface.
UIP
Page 85
Process: EPU
Process
Function
GTP
PCP
The PCP manages the GTP paths and bandwidth resources on the
VRP and local EPU in a unified manner.
UMP
The UMP manages the platforms and devices on the user plane.
PFP
LIP
Page 86
Process: ESU
Process
Function
SPP
The SPP is the main process for processing SGSN or MME services on the control plane and
controlling various services.
SGP
The SGP processes the signaling transmitted over the Iu and S1-MME interfaces on the
control plane and SIGTRAN protocol stacks.
GBP
LLP
CDP
The CDP supports charging data storage and provides Ga interfaces. The CDP processes
half-finished CDRs into finished CDRs. The CDP reports CDRs to the CG. When all the
connected CGs fail, the CDP saves the CDRs in the local hard disk.
LCP
The LCP controls the heartbeat handshake between the license control center and the Gb
interface.
UIP
UPP
The UPP processes the GTP and VRP and supports the forwarding function.
AMP
The AMP manages the user-plane platform and the devices on the platform.
Page87
Contents
1. Background Knowledge of the USN9810
2. System Structure of the USN9810
3. Cable Connection of the USN9810
4. Service Flow of the USN9810
Page 88
Contents
3. Cables
3.1 Power Cables
3.2 Signal Cables
3.3 Service Cables
Page 89
Page 90
AC power
supply
DC power
supply
DC power
distribution system
Cabinet
Mount bar
Cable connection diagram (dual-channel cable from the DC power distributing cabinet to the device cabinet)
Page91
Contents
3. Cables
3.1 Power Cables
3.2 Signal Cables
3.3 Service Cables
Page 92
Page 93
8
X1
X2
SDM
ETH
COM2 COM1
ETH
COM2
Page 94
COM1
PEM
FAN
Copyright 2010 Huawei Technologies Co., Ltd. All rights reserved.
ENV
Page 95
Contents
3. Cables
3.1 Power Cables
3.2 Signal Cables
3.3 Service Cables
Page 96
Page 97
Inter-Subrack Cascading
Page 98
Clock Connection
TMI
SS7 clock input
Copyright 2010 Huawei Technologies Co., Ltd. All rights reserved.
Contents
1. Background Knowledge of the USN9810
2. System Structure of the USN9810
3. Cable Connection of the USN9810
4. Service Flow of the USN9810
Page 100
Contents
4. Service Flow
4.1 Service Flow in Gb Mode
4.2 Service Flow in Iu Mode
4.3 Service Flow in S1 Mode
Page 101
Page 102
Page 104
Page105
Page 106
Page 108
Page 110
Page 112
Contents
4. Service Flow
4.1 Service Flow in Gb Mode
4.2 Service Flow in Iu Mode
4.3 Service Flow in S1 Mode
Page 114
Page 115
Page 117
Page 119
Contents
4. Service Flow
4.1 Service Flow in Gb Mode
4.2 Service Flow in Iu Mode
4.3 Service Flow in S1 Mode
Page 121
1. Attach Request
23. Attach Accept
EPU
PFI
2
21
PFP
10
S-GW
14
17
11 6
ECU
HSS
18
20
5
SGP
12
19
13
Page 122
SPP
Page123
Thank you
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