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if reset = 0 then
output <= 0;
elsif set = 0 then
output <= 1;
elsif (clockevent and clock = 1) then
output <= data;
end if;
output <= 1;
end if;
if sel = 0 then
output <= data1;
elsif sel = 1 then
output <= data2;
end if;
if clear = 0 then
shift_reg <= 00000000;
elsif (clockevent and clock = 1) then
shift_reg(7 downto 1) <= (6 downto 0);
shift_reg(0) <= serial;
end if;
if load = 0 then
shift_reg <= parallel;
elsif (clockevent and clock = 1) then
serial <= shift_reg(7);
shift_reg(7 downto 1) <= (6 downto 0);
end if;
if load = 0 then
output <= 1111;
elsif (clockevent and clock = 1) then
output <= data - 1;
end if;
carry <= 0 when output = 0000 else 1;
load <= carry;
if c = 0 then
if (a and b) = 1 then
sum <= 0;
carry <= 1;
elsif (a or b) = 1 then
sum <= 1;
carry <= 0
end if;
elsif c = 1 then
if (a and b) = 1 then
sum <= 1;
carry <= 1;
elsif (a or b) = 1 then
sum <= 0;
carry <= 1;
end if;
end if;
if reset = 0 then
state <= stateA;
output <= 0;
elsif (clockevent and clock) = 1 then
case state is
when stateA
output <= 0;
state <= stateB
when stateB
output <= 1;
if input = 1 then
state <= stateB;
else
state <=stateC;
end if;
when stateC
output <= 0
state <= stateA;
end case;
IEEE-1076: Standard VHDL Language Reference Manual IEEE Compute
VHDL code for a D Flip Flop
if reset = 0 then
output <= 0;
elsif set = 0 then
output <= 1;
elsif (clockevent and clock = 1) then
output <= data;
end if;
if sel = 0 then
output <= data1;
elsif sel = 1 then
output <= data2;
end if;
if clear = 0 then
shift_reg <= 00000000;
elsif (clockevent and clock = 1) then
shift_reg(7 downto 1) <= (6 downto 0);
shift_reg(0) <= serial;
end if;
if load = 0 then
shift_reg <= parallel;
elsif (clockevent and clock = 1) then
serial <= shift_reg(7);
shift_reg(7 downto 1) <= (6 downto 0);
end if;
if load = 0 then
output <= 1111;
elsif (clockevent and clock = 1) then
output <= data - 1;
end if;
carry <= 0 when output = 0000 else 1;
load <= carry;
if c = 0 then
if (a and b) = 1 then
sum <= 0;
carry <= 1;
elsif (a or b) = 1 then
sum <= 1;
carry <= 0
end if;
elsif c = 1 then
if (a and b) = 1 then
sum <= 1;
carry <= 1;
elsif (a or b) = 1 then
sum <= 0;
carry <= 1;
end if;
end if;
if reset = 0 then
state <= stateA;
output <= 0;
elsif (clockevent and clock) = 1 then
case state is
when stateA
output <= 0;
state <= stateB
when stateB
output <= 1;
if input = 1 then