Proc.

of the 2014 International Symposium on Electromagnetic Compatibility (EMC Europe 2014), Gothenburg, Sweden, September 1-4, 2014

Forward Wave Analysis of Vertical Distribution of

Power Supply Noise in Multilayer PCB
Umberto Paoletti, Yasumaro Komiya, Takashi Suga, Hideki Osaka
Hitachi Ltd., Yokohama Research Laboratory,
292 Yoshida-cho, Totsuka-ku, Yokohama 244-0817, Japan
Email: umberto.paoletti.ff@hitachi.com

AbstractPower supply noise generated by integrated circuits

is one of the major sources of EM radiation from PCBs. The
reduction of power supply noise can be realized by means of
devices that bypass the current among power supply planes, such
as bypass capacitors, ground vias and so on. In a previous work
the effect of current bypass devices on the far field radiation
from multilayer PCBs was very efficiently estimated by means
of a new technique called forward wave analysis. In this work
it is shown that forward wave analysis can be used also to
study the vertical distribution of the power supply noise in
multilayer PCBs. This allows to understand some important noise
propagation mechanisms and to take low-cost countermeasures
at early stage of PCB design.
Index Termscomponent; formatting; style; styling; insert

I. I NTRODUCTION
Power supply noise of printed circuit boards (PCBs) is a
major source of high frequency electromagnetic interferences
(EMI). The simultaneous switching noise (SSN) generated by
large scale of integration integrated circuits (LSI) propagates
as an electromagnetic (EM) wave between the power supply
planes and is radiated from the edges (e.g. Fig. 1).
Forward Bypass Noise source
Reflected
capacitor
LSI
Bypass capacitor
backward wave wave

Radiated
noise

Trace
Component
Component Bypass
capacitor

LSI

II. F ORWARD WAVE ANALYSIS

Power plane

Fig. 1: Multi-layer PCB.

The state of the art for efficiently estimating the radiation
consists in evaluating the voltage along the edges of the power
supply planes and in replacing the edge voltage with an equivalent magnetic current that is used to calculate the radiated field
(e.g. [1]). One problem of this method is that simulations of the
whole PCB planes are required, including all the components
connected to the planes. Although very important progresses
have been made recently in PCB simulation techniques (e.g.
[2], [3]), this still requires considerable calculation time, and
must be repeated when the layout is changed during the
design phase. Another problem is that models of LSIs and

978-1-4799-3226-9/14/$31.00 2014 IEEE

other components are not always available, compromising the

accuracy of the calculation.
In [4] the authors proposed an approximate but very efficient
way to estimate the effect of current bypass devices, such as
capacitors or ground vias, on the radiation by considering the
radiation effective forward wave voltage, which is the voltage
between the top and bottom power supply planes after that
all the planes have been ideally extended to infinite. The ratio
of the far field before and after adding some current bypass
devices resulted to be well approximated by the ratio of the
power associated with the radiation effective forward wave
voltage, except for minor resonances associated with the finite
size of the planes.
In section II some key concepts of forward wave analysis
are summarized, with particular consideration for the noise
injected in each single substrate layer between adjacent power
supply planes. In section III an example will be presented and
the simulation results will be compared with a commercial
tool. In section IV the simulation results will be discussed
and important considerations related to the vertical noise
distribution will be made by using forward wave analysis.

The technique is based on the observation that under certain

circumstances the effect of current bypass devices is dominant
over the effect of board resonances, and therefore their effect
on the radiation can be estimated in terms of the ratio of
the power injected into an infinite board before and after
introducing these devices. This is the case for example for
frequencies well above the first parallel plane resonance, where
the quality factor of the plane resonances is relatively small.
The term forward wave is used for the EM wave between
two infinite planes, that is without reflection from the plane
edges and from any other components or discontinuities outside the simulation region of interest. Hence, simulations can
be made using the local layout close to the noise source,
greatly simplifying the calculations. The calculation time is
further decreased by the fact that very efficient formulas for
vias in infinite planes exist, which are based on the cylindrical
expansion of the EM wave (e.g. [5]).
A second important concept to underline is that the radiation
from the edges of a PCB is determined by the total edge
voltage between top and bottom planes. Therefore, in [4] the
authors used the term equivalent radiation effective forward

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Proc. of the 2014 International Symposium on Electromagnetic Compatibility (EMC Europe 2014), Gothenburg, Sweden, September 1-4, 2014

wave or more simply radiation effective forward wave to

indicate the superposition of the forward waves in all the
substrate layers of infinite planes, which can be represented in
terms of the voltage between top and bottom planes.
When the source current and impedance are known, by
looking at the two-dimensional distribution of the radiation
effective forward wave voltage at one particular frequency, it
is possible to clearly distinguish in which direction the noise
is injected into the PCB, and to decide the position of current
bypass devices such as ground vias. Furthermore, radiation
effective forward waves can be used to estimate the ratio
of the radiated far field after and before introducing current
bypass devices. Finally, the forward wave power injected in
each dielectric substrate can be estimated also separately, revealing very important information regarding the vertical noise
distribution among the layers, which can be used for example
in the selection of the layer stack-up, and eventually also for
power integrity (PI) and signal integrity (SI) applications.
Assuming a linear behavior of the noise source, the noise
model consists in general in a multiport Norton equivalent
circuit, that is frequency dependent complex current sources
with multi-port impedances. In practice such complex models
are often not available and the design must be conducted using
simplified models. The simplest model consists of unitary
real current sources without any impedance (that is infinite
impedance or zero admittance). The noise source models are
connected to the vias on the first plane close to the LSI. Since
usually the first plane is a ground plane, the noise sources are
connected between the first ground plane and power vias.
The calculation of the inter-plane voltage Vi in the observation positions (, ) of the substrate layer i can be made
with cylindrical harmonics, as long as the current in all the
via ports of the adjacent conductor layers is known. One
possible method to calculate the via port current makes use of
the analysis technique for multilayer PCBs described in [3],
including the physical model definition of the via ports for
multilayer PCBs. In short, first the PCB admittance matrix
is calculated according to [3], next the port voltages and
currents at the LSI-PCB interface are calculated, then with a
sort of back-substitution, the PCB internal via port currents are
calculated, and finally from the port via current the inter-plane
voltage Vi (, ) in the observation positions can be calculated.
Since the radiated power from the edges of a finite board
is determined by the total edge voltage, we introduce the
Poynting vector of the radiation effective forward wave, SE ,
by first averaging the electric and magnetic fields in the vertical
direction as follows:
1
SE = 2
h


i


z
Ezi hi


Hti

hi

(1)

where Ezi = Vi /hi is the vertical component

 of the electric
field in the substrate i of thickness hi , h = i hi is the total
substrate height,
z is the unitary vector in the vertical direction
and Hti is the horizontal magnetic field in the substrate i.
The average power PE of the radiation effective forward wave

can be calculated from the real part  of the integral of the

Poynting vector on a cylindrical surface with thickness h and
contour C with outwards oriented normal vector n
as follows:



1
SE n
dl = 
VE
z Ht n
dl ,
2
C
C
(2)

Ezi hi is the radiation effective wave
where VE = i
voltage and Ht =
i Hti hi /h is the horizontal magnetic
field of the radiation effective wave.
PE =

1
h
2



III. S IMULATION EXAMPLE

In this case a complex stack-up with seven ground planes
and one power plane is considered as shown in Fig. 2. The
LSI is placed on the top layer. All the planes have the same
dimensions of 250 mm 250 mm. The reference layout has
31 ground vias and 5 power vias close to one PCB edge,
namely at approximately 40-47 mm from the closest edge and
83-93 mm from the second one. Five unitary ideal current
sources connected to the power vias have been used in the
calculation. Figs. 3(a) and (b) show the mapping of the forward
wave voltage VE between the top and bottom ground planes
at 1 GHz and 6 GHz, respectively. The noise generated by the
power vias is clearly visible.
LSI
Substrate layer 1
Substrate layer 2
Substrate layer 3
Substrate layer 4

0.2mm
0.1mm
0.1mm
0.2mm

Substrate layer 5

0.8mm

Substrate layer 6

0.2mm

Substrate layer 7

0.2mm

Ground
Ground
Power
Ground

Radiation
effective
voltage

Ground

Ground
Ground
Ground

Bypass capacitors

Fig. 2: Layer stack-up with eight planes.

In order to reduce the radiated noise, 5 ground vias have
been added adjacent to the power vias in the direction of
the noise lobes, as shown in Fig. 3(c) and (d). Other five
vias adjacent to the power vias have been added as well.
These latter 5 vias are connected to the power planes but
not to the LSI, and they have been used to connect 5 bypass
capacitors on the bottom layer. Other 5 capacitors on the
bottom layer have been directly connected to the power vias.
Very small capacitance values have been selected (C = 0.3 pF,
ESL = 0.34 nH, ESR = 0.48 and C = 0.4 pF, ESL = 0.34 nH,
ESR=0.35 ) in such a way that, considering also the trace
and PCB parasitics, the noise injected into the substrate layer
above the power plane is reduced at 6 GHz.

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Proc. of the 2014 International Symposium on Electromagnetic Compatibility (EMC Europe 2014), Gothenburg, Sweden, September 1-4, 2014

(a)

(b)

(c)

(d)

Fig. 3: Mapping of voltage between bottom and top planes at

1 GHz (a,c) and 6 GHz (b,d) before (a,b) and after (c,d) the
introduction of 5 ground vias and 10 bypass capacitors.

With and without 5 ground vias and 10 capacitors

5

Expected field ratio ||Ew|| / ||Ew/o|| [dB]

In Fig. 3(c) a reduction of the noise at 1 GHz is clearly

visible, and it is mainly due to the added ground vias, as it
will become more clear later. However, Fig. 3(d) shows that all
the vias connected to the power planes act as noise sources
for the forward waves at 6 GHz, and that in particular the
additional power vias connected to the bypass capacitors are
more effective because they are less shielded by the ground
vias. In order to understand the physical reason of the increase
in radiation, in section IV some very important considerations
regarding the layer stack-up will be made using the forward
wave approach.
In order to confirm the results, the ratio of the power
associated with the radiation effective forward wave after and
before modifying the layout between 1 GHz and 8 GHz has
been calculated, and compared with the far field ratio obtained
with a commercial tool (Ansoft SIwave) that analyzes the
whole board, as shown in Fig 4. Except for the considerable
resonances that appear in the lower frequency range, the
dominant effect has been remarkably predicted by the forward
wave approach. The calculation time with the Matlab program
using forward wave analysis was approximately 1/40 of that
of SIwave, which is well known to be a very fast tool when
compared to full wave simulations. A compiled version of the
forward wave program is expected to be even faster.
A large reduction of the radiation can be observed at 1 GHz
in Fig 4, but almost no effect is visible at 6 GHz, which was
the target frequency of the bypass capacitor design. The reason
for this can be individuated with forward wave analysis of the
vertical noise distribution, as shown in the following section.

Commercial tool
Forward waves
0
5
10
15
20
25
1

Frequency [GHz]

Fig. 4: Expected far field ratio with (Ew ) and without (Ew/o )
capacitors with a commercial tool and forward waves.

IV. V ERTICAL NOISE DISTRIBUTION

In the calculation of the radiated power from the PCB
edges, the total edge voltage is the relevant quantity, that is the
algebraic summation of the voltage among all the conducting
layers considering their complex phase. For this reason in the
previous section the forward wave voltage mapping between
the top and bottom planes was shown and discussed. However,
in order to understand the results, it is very interesting to
consider also the power injected into each layer separately.
The power of the forward wave injected into each substrate
layer is shown in Figs. 5 and 6, for the reference configuration
and for that with additional ground vias and capacitors, respectively. In the same figures with the label Total the radiation
effective forward wave power calculated by summing up the
layer voltages is also shown, which has been used to calculate
the expected field ratio in Fig. 4. Since unitary current sources
have been used in the calculation, the absolute value of the
power is not relevant.
The first thing that can be observed is that in the reference
configuration the power injected into the top three substrate
layers is much larger than that into the bottom four layers.
Second, among the bottom four substrate layers, the injected
power decreases when the distance from the noise sources is
increased, except for the fifth substrate layer, which is the
thickest one. The reason for this is that by using a 3-port via
model (e.g. in [3]), the via current decreases along the vertical
direction while injecting power into the above substrate layers.
Furthermore, for a given current entering one substrate layer
from one via port, the injected power is proportional to the
substrate layer thickness.
The power injected into the second and third substrate
layers, which are the layers adjacent to the power plane, is
even larger than the total radiation effective forward wave
power. The physical meaning of this is that their contributions
are approximately opposite in phase and partially cancel out.
The combined contribution of the two layers adjacent to the

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Proc. of the 2014 International Symposium on Electromagnetic Compatibility (EMC Europe 2014), Gothenburg, Sweden, September 1-4, 2014

Reference configuration

plotted in Fig. 6. In the lower frequency range it can be

observed that the power injected into the first substrate layer is
strongly reduced, and that the contributions of the second and
third layers become much more similar to each other, resulting
in an overall reduction of the total radiation. This is due to
the broadband effect of the added five ground vias.

20
30

50
60
70

90
100
110
120
1

Configuration with 5 ground vias and 10 capacitors

Total
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7

80

Frequency [GHz]

0
10
20

Injected power [dBW]

Injected power [dBW]

40

Fig. 5: Injected power into each infinite substrate layer of the

reference configuration.

30
40
50
Total
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7

60
70
80
90

power plane appears in the figure to be comparable to the

contribution from the first top substrate layer, which in this
example is enclosed by two ground planes placed between the
LSI and the power plane.
A confirmation of the cancel-out effect of the noise of
substrate layers 2 and 3 comes from the horizontal forward
wave voltage distribution Vi at 1 GHz on the first four substrate
layers shown in Fig. 7. It is evident that the second and
third substrate layers are the hottest ones, that their voltage
distribution is very similar in amplitude, that the fourth layer is
practically cold, and that the voltage distribution in the first
substrate layer is not at all negligible, since it is quantitatively
very similar to that of the total voltage shown in Fig. 3(a). The
voltage distributions of the bottom three substrate layers have
not been plot in the figure because they are not distinguishable
from that of layer 4 and for the sake of conciseness.
The fact that the noise in the substrate layers close to the
power plane is very large may have a considerable impact on
SI and PI, and should be taken into account when selecting the
signal and plane layout, as well as the stack-up. Unfortunately,
it might become also a cause of failure of the proposed
radiation estimation approach in some situations, because the
strong power supply noise could follow other paths and couple
to other radiation mechanisms.
The voltage distribution at 6 GHz shown in Fig. 8 is
qualitatively very similar to that at 1 GHz, except for the
fact that the second and third substrate layers are less hot
with respect to the first substrate layer than at 1 GHz. This
confirms the faster increasing trend of the contribution to the
radiated power from the first substrate layer that is visible in
Fig. 5. The substrate layers 4, 6 and 7 do not present any
visible voltage, similarly at 1 GHz, and have not been plot in
the figure for the sake of conciseness. A weak noise voltage
is only slightly visible in substrate layer 5.
After the introduction of vias and bypass capacitors, the
forward wave power injected into each substrate layer is

100
1

Frequency [GHz]

Fig. 6: Injected power into each infinite substrate layer after

the introduction of current bypass devices.
At 6 GHz the effect of the bypass capacitors is clearly
visible in the reduction of the injected power into the second
and third substrate layers. This was realized by selecting the
values of the capacitors in such a way that they create a
resonance together with the PCB parasitics at this frequency.
However, the power injected into the lower four bottom layers
increases very fast with the frequency and reaches a maximum
approximately at 6 GHz. In particular the fifth substrate layer,
which according to Fig. 2 is the thickest one, gives now the
dominant contribution to the radiation effective forward wave
indicated in the figure with Total. This effect is clearly related
to the fact that the capacitors were mounted on the bottom
conducting layer, providing a low impedance path at 6 GHz
for the current through otherwise cold substrate layers.
The voltage distribution at 1 GHz in each single layer
becomes that shown in Fig. 9. The main visible effects of
the bypass capacitors are that the voltage in the first substrate
layer has been reduced, and that the voltage distribution on
the second and third layers are more similar to each other.
It is important to observe that the effect of ground vias is
to balance the voltage distribution on the two substrate layers
adjacent to the power planes, without significantly reducing
the noise in the single layers. This means that even though
the radiation is reduced, these two layers remain very noisy.
The voltage distribution at 6 GHz in each single layer
becomes that shown in Fig. 10. By comparing this figure with
Fig. 8, it is evident that the first three substrate layers are now
colder than before, whereas the bottom four substrate layers,
and in particular the thick fifth layer, become more noisy. By
looking with more attention to the fifth layer, it is also evident

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Proc. of the 2014 International Symposium on Electromagnetic Compatibility (EMC Europe 2014), Gothenburg, Sweden, September 1-4, 2014

(a) Substrate layer 1

(b) Substrate layer 2

(c) Substrate layer 3

(d) Substrate layer 4

Fig. 7: Mapping of voltage between the first five adjacent planes at 1 GHz of the reference configuration.

(a) Substrate layer 1

(b) Substrate layer 2

(c) Substrate layer 3

(d) Substrate layer 5

Fig. 8: Mapping of voltage in the first three substrate layers and in the fifth one at 6 GHz of the reference configuration.

that the vias connected to the bypass capacitors are now the
main noise sources, confirming the fact that low impedance
paths provided by the bypass capacitors are carrying the noise
towards the otherwise cold bottom layers.
It must be observed that the 6 GHz resonance in the example
above was determined by the selected extremely low values
of the capacitors. Capacitors that are typically used for power
integrity in PCBs have much larger capacitance, and above
1 GHz their parasitic inductance is usually dominant. However,
above a few GHz the traces used for connecting the capacitors are electrically long and behave like transmission lines,
creating low impedance paths at some resonance frequencies.
Therefore, the mechanism observed here for a particular ideal
PCB can be present also in PCBs of real products.

to affect traces and power islands that may be present in the

same layers.
As a general rule it is preferable to use ground vias to
reduce power supply noise radiation in boards with many
layers, particularly at high frequencies, because they provide
a broadband noise reduction by concentrating the power close
to the noise sources, and do not have negative side effects. A
suitable distribution of the ground vias can be estimated based
on the radiation effective forward wave voltage distribution.
R EFERENCES
[1]

[2]

V. C ONCLUSION
The proposed forward wave analysis has been confirmed to
be a very efficient method to estimate the effect of current
bypass devices on the radiation from power supply planes.
Furthermore, when applied to study the vertical distribution
of the SSN injected between power supply planes, it can help
to understand the propagation mechanism and therefore to take
proper countermeasures at early stage of the design. It must
be remarked that these results are of relevant importance for
PI and SI as well, because noisy substrate layers are likely

[3]
[4]
[5]

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2010.

Proc. of the 2014 International Symposium on Electromagnetic Compatibility (EMC Europe 2014), Gothenburg, Sweden, September 1-4, 2014

(a) Substrate layer 1

(b) Substrate layer 2

(e) Substrate layer 5

(c) Substrate layer 3

(f) Substrate layer 6

(d) Substrate layer 4

(g) Substrate layer 7

Fig. 9: Mapping of voltage between adjacent planes at 1 GHz after the introduction of 5 ground vias and 10 bypass capacitors.

(a) Substrate layer 1

(b) Substrate layer 2

(e) Substrate layer 5

(c) Substrate layer 3

(f) Substrate layer 6

(d) Substrate layer 4

(g) Substrate layer 7

Fig. 10: Mapping of voltage between adjacent planes at 6 GHz after the introduction of 5 ground vias and 10 bypass capacitors.

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