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Library Modelling for Isolation Cells

About
Magic Blue Smoke is a blog
dedicated to discussing the
challenges of low power ASIC
Design

Posted by Godwin Maben on 1st October 2007

Categories
Architecture
chip finishing
implementation
Infrastructure
Library Modelling
low power general
Power Format
Uncategorized

I Forgot to add the syntax of Modelling Isolation cells. Thanks Sampath for reminding me on this. Here is
one way to model ISOLATION cells
cell (isolation_cell) {
cell_leakage_power : 2.382 ;
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pin(data_in) {
direction : input;
capacitance : 0.001867;
rise_capacitance : 0.001234;
fall_capacitance : 0.004567;
}
pin(isolation_enable) {
direction : input;
capacitance : 0.007890;
rise_capacitance : 0.001234;
fall_capacitance : 0.005678;
isolation_cell_enable_pin : true;
}
pin(clamped_data) {
direction : output;
max_capacitance : 0.09876;
function : (data_in+isolation_enable);
timing() {
related_pin : isolation_enable;
timing_sense : positive_unate;
.
}
.
}
Posted in Library Modelling | 1 Comment

How to model Special Cells in libraries?

Posted by Godwin Maben on 8th September 2007
I have been post-poning explaining about the library requirements for quite sometime. Today let me
explain little bit on library modelling of special cells such as
(1) Level Shifter
(2) Isolation Cell

https://blogs.synopsys.com/magicbluesmoke/category/library-modelling/[8/12/2016 12:30:51 PM]

I have worked in
the VLSI industry
for 14 years as a
digital IC designer. My recent
work has been focused on
low-power challenges
associated with multi-voltage/
multi-supply designs. The goal
of this blog is to open a free
exchange of ideas with
regards to low power. Please
participate!
- Godwin Maben

Magic Blue Smoke Library Modelling

(3) Retention flop
(4) Always On Cell
(5) Switch
Most important information to note here is, these special cells may have multiple power pins and hence
we have to describe these models with pg_pin so that the timing arcs are w.r.t to these power and
ground pins as well
(1) Level Shifter:
cell (low2high_ls) {
level_shifter_type : LH;
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
std_cell_main_rail : true;
}
pg_pin(VDDL) {
voltage_name : VDDL;
pg_type : primary_power;
}
is_level_shifter : true;
pin(I) {
direction : input;
capacitance : 0.0034;
rise_capacitance : 0.0032;
fall_capacitance : 0.0034;
input_signal_level : VDDL;
related_power_pin : VDDL;
related_ground_pin : VSS;
}
br> pin(Z) {
direction : output;
output_signal_level : VDD;
related_power_pin : VDD;
related_ground_pin : VSS;
..
}
(3) Retention Flop:
cell (retention_flop) {
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin (VDD_retain) {
voltage_name : VDD_retain;
pg_type : backup_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
..
cell_footprint : retention_flop ;
power_gating_cell : retention_flop ;
ff(IQ,IQN) {
next_state : ((D !SE) + (SE SI)) (wakeup !sleep);
clocked_on : CP;
}
pin(wakeup) {
always_on : true;
direction : input;
capacitance : 0.0012;

https://blogs.synopsys.com/magicbluesmoke/category/library-modelling/[8/12/2016 12:30:51 PM]

Magic Blue Smoke Library Modelling

rise_capacitance : 0.0012;
fall_capacitance : 0.0012;
power_gating_pin (power_pin_1, 1);

}
(4) Always on Buffer:
cell (always_on_buffer) {
always_on : true;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin (VDD_retain) {
voltage_name : VDD_retain;
pg_type : backup_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
.
}
(5) Switch Cell:
cell (header_switch) {
switch_cell_type : coarse_grain;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
direction : input;
}
pg_pin(VDD_internal) {
voltage_name : VDD_internal;
pg_type : internal_power;
switch_function : sleepin;
pg_function : VDD;
direction : output;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
direction : input;
}

pin(sleepin) {
switch_pin : true;
always_on : true;
direction : input;
capacitance : 0.0046;
rise_capacitance : 0.0046;
fall_capacitance : 0.0046;
}
pin(sleepout) {
power_down_function : !VDD + VSS;
direction : output;
max_capacitance : 0.1694;
function : sleepin;
..
}
If the required attributes highlighted in the above .lib model is present, most of the tools will be able to
identify them as special cells and optimize them accordingly.
Posted in Library Modelling | 8 Comments

https://blogs.synopsys.com/magicbluesmoke/category/library-modelling/[8/12/2016 12:30:51 PM]

Magic Blue Smoke Library Modelling

Modelling of Library cells for Multi-Voltage

Posted by Godwin Maben on 9th May 2007
Guys, I really apologise for not updating my blog more frequently. Next 2 weeks I will be away on a
business trip, will try to post atleast a couple of times.
Today lets look at the modelling of logical library cells specifically for MV. Accurate modelling of libraries
is one of the crucial requirement for any design as we are going to sign-off using these libraries.
(1) Modelling of regular Std Cell library.
Traditionally this used to be very straight forward. But with MV, there are a couple of questions that need
to be addressed:
(a) Standard cell for different Voltages
(b) Whats the derating model used? K-Factor based is not recommended due to lack of
accuracy.
(c) One of the reason why this is so important is,if we are running IR Drop basedStatic
TimingAnalysis,how will my timing be derated ?For example cell is characterized at 0.9V, but if the
Voltage at the cell in question is 0.82V, how will this be timed?
(d) IMHO, the timing accuracy is not very reliable if IR-Drop is more than 5%, if regular NLDM
models are used.
(e) I would look at more options available today in terms of modelling libraries for better
accuracy. One such option would be to move towards CCS timing/power models, rather than traditional
NLDM models.
(f) IMHO, we should also include power/ground pins in the logical libraries. I will talk about the
reasoning behind this in the later blogs.
Let me discuss modelling of other library cells in my next post. Guys jump in and throw in your
questions/thoughts.
Posted in Library Modelling | 2 Comments

2016 Sy nopsys, In c. A l l Ri g h ts Reser ved.

https://blogs.synopsys.com/magicbluesmoke/category/library-modelling/[8/12/2016 12:30:51 PM]

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