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PRINTED CIRCUIT
DESIGN & FAB
pcdandf.com
circuitsassembly.com
November 2016
C I R C U I TS
Our Stencil-less jet printer eliminates the need for stencils. This allows us to
turn your assemblies around in a day! No more waiting 1-3 days for stencils!
Our State of the art equipment allows quick changeovers, eliminating downtime
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FIRST PERSON
6
PRINTED CIRCUIT
DESIGN & FAB
CAVEAT LECTOR
Plugging the leaks.
Mike Buetow
MONEY MATTERS
15 ROI
FEATURES
20
THERMAL MANAGEMENT
Peter Bigelow
Past articles looked at the relationship between trace current and temperature for pulses that propagated through the
trace. A look at the slightly more complicated topic of analog
16
FOCUS ON BUSINESS
Mike Buetow
18
24
PCB MATERIALS
GLOBAL SOURCING
Greg Papandrew
TECH TALK
ON THE COVER
BTC voiding on a 64-pin
QFP. (Photo courtesy Alpha
Assembly Solutions)
30
EMS
Jabil Steps Up
Move over Nike: A new plant in a new market has one of the worlds top ODM/EMS companies
19
DESIGNERS NOTEBOOK
For reference or not?
by MIKE BUETOW
32
Duane Benson
38
Timothy ONeill
40
GETTING LEAN
Shedding light on wastes in
LED assembly.
of comparative results. Observed were the effects with both high-voiding and low-voiding pastes.
by BROOK SANDY-SMITH
ONLINE AT PCDANDF.COM
ONLINE AT CIRCUITSASSEMBLY.COM
43
DEFECTS DATABASE
Spitting it out.
Robert Boguski
How Can the IoT Be a Solid Rock to Build Products and Profits On?
by JON HOWES
42
How Stencil Design and Reflow Profiles Affect Variation in QFN Voiding
Data: A Case Study
A review of several cases where changing the stencil design or reflow profile dialed in the variation
TECH TIPS
Getting to the bottom of
void problems on QFNs.
PROCESS CONTROL
DEPARTMENTS
8 AROUND
THE WORLD
14
MARKET WATCH
46 MARKETPLACE
44
46
AD INDEX
Martin Wickham
48
TECHNICAL ABSTRACTS
POSTMASTER: Send address changes to PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY,
P.O. Box 35621, Tulsa, OK 74153-0621
Increase your
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pcdandf.com
com
circuitsassembly.
February 2013
pg. 28-32
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Visit www.pcbwest.com for information about our conference and trade show
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HALL B4, STAND 106
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PRINTED CIRCUIT
DESIGN & FAB
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circuitsassembly.com
EDITORIAL
EDITOR IN CHIEF: Mike Buetow, 617-327-4702, mbuetow@upmediagroup.com
SENIOR EDITOR: Chelsey Drysdale, 949-295-3109, cdrysdale@upmediagroup.com
DESIGN TECHNICAL EDITOR: Pete Waddell
EDITORIAL OFFICE: P.O. Box 470, Canton, GA 30169,
See us at ELECTRONICA,
HALL A1, STAND 665
888-248-7020
PRODUCTION
ART DIRECTOR: Rebekah Venturini, rventurini@upmediagroup.com
SALES
SALES DIRECTOR:
Frances Stewart, 678-817-1286,
fstewart@upmediagroup.com
SALES ASSISTANT
Rebecca Handler, 770-617-7864,
rhandler@upmediagroup.com
EXHIBIT SALES:
Frances Stewart, 678-817-1286,
fstewart@upmediagroup.com
CIRCULATION
DIRECTOR OF AUDIENCE DEVELOPMENT:
Jennifer Schuler
NOVEMBER 2016
CAVEAT LECTOR
NOVEMBER 2016
POWERED
BY SCIENCE
and Industrys
Best Technical
Team
ENIG
The industry standard for producing
uniform mid-phos EN deposits with a
thin topcoat of immersion gold, over
copper. Solderable and aluminum wire
bondable; no dummy plating.
ENEPIG
www.uyemura.com
Corporate Headquarters: Ontario, CA ph: (909) 466-5635 (800) 969-4842
PCD&F People
Photomachining named Mathew Hannon
laser applications engineer.
Seacole Specialty Chemical named Walt
Forgacs printed circuit board account
manager.
Taiyo named Alyssa Orellana customer
service representative.
Ventec appointed Denis McCarthy Jr. technical sales account manager - USA.
PCD&F Briefs
Altium completed its acquisition of Transfer
BV, a longtime reseller of Altiums PCB
CAD tools. The acquisition includes a combination of cash, plus additional payments
based on sales performance over the next
three years.
ATLANTA UP Media Group seeks abstracts for PCB West 2017, to be held Sept.
12 - 14 in Santa Clara, CA. The event includes a three-day technical conference and
one-day exhibition to be held at the Santa Clara Convention Center.
PCB West annually provides a conference and exhibition focused on the design
and manufacture of PCBs, HDI, electronics assembly and circuit board test. The
September 2016 event attracted nearly 2,000 attendees.
Papers and presentations of the following durations are sought for the technical
conference: one-hour lectures and presentations; two-hour workshops; and halfday (3.5 hour) and full-day seminars.
Papers and presentations must be noncommercial in nature and should focus on
technology, techniques or methodology.
Abstracts of 100 to 300 words and speaker biographies should be submitted to
UPMG atpcbwest.com/submit-an-abstractby Feb. 3.
Anyone may submit an abstract to present a course at PCB West 2017, and
presenters may present more than one paper or teach more than one course. A separate abstract must be submitted for each course. If selected, a detailed presentation
outline and final paper or presentation is due Jul. 25. MB
Nano Dimension will form a new subsidiary and will transition its 3D printing activities to the new entity.
Solo-Labs announced the 5,000th download of its SoloPCB-Designer 2.0 free PCB
design software.
Zentech Manufacturing in September
acquired Interconnect Design Solutions,
a Charleston, SC-based electronics design
engineering company. IDS founder Mike
Brown will remain with Zentech as vice
president of engineering services.
CA People
Benchmark
Electronics
announced Paul J. Tufano as
president and chief executive officer. Tufano was CFO of
Alcatel-Lucent from 2008-2013,
and was CFO of Solectron. He
replaces Gayla Delly, who resigned as both
the top executive and as a member of the
board to pursue other interests.
ATLANTA PCB West 2016 show attendance rose 3% year-over-year, to nearly 2,000
attendees, UP Media Group announced. It was the annual PCB industry trade shows
highest turnout since 2001.
Registration for the 25th annual show was up 6% from 2015, added UPMG.
Overall, nearly 2,000 printed circuit board designers, fabricators and electronics
assemblers, managers and suppliers attended the September trade show, UPMG said.
It was the seventh straight year both show registration and actual attendance
figures have climbed.
Technical conference registration rose more than 20% year-over-year. Attendees
gravitated toward sessions on resolving fundamentals and practical solutions to engineering and design problems. More than 24 designers underwent IPC certification
during the conference as well.
The sold-out show floor featured more than 100 companies occupying 110
booths, and exhibitors were outwardly pleased about their leads from the consistently busy show.
It is remarkable how, after 25 years, the demand for printed circuit board
knowledge continues unabated, said Mike Buetow, editorial director of UPMG.
This years show was our largest ever in terms of the number of exhibitors, with
twice the number we had just five years ago. And the technical conference just keeps
growing, too.
NOVEMBER 2016
youtube.com/user/aimsolderaim
CA Briefs
AIM Solder added Alfatec Indstria e Comrcio as a licensed manufacturer of AIMs line
of solder assembly materials in Brazil.
Asteelflashinstalled four Fuji NXT IIIs and
one Fuji XPF component mounter at its
manufacturing facility in La Soukra, Tunisia.
Creation Technologiesinstalled two Ace
Production Technologies Kiss-102IL selective soldering systems in Mexicali, Mexico.
Enics Schweizwill cut up to 25% of its
workforce in Turgi, Switzerland.
10
PCB West 2017 will take place Sept. 12-14 at the Santa Clara (CA) Convention
Center. MB
business for $3.2 billion to a private equity firm, according to published reports.
In sealing the deal, Carlyle Group reportedly beat out other private equity
firms, including CVC Capital Partners and Cinven.
Berlin-based Atotech has annual sales of $1.1 billion. Carlyle reportedly
says it expects continued growth for Atotech, but hasnt divulged its plans for
the company.
In May,Total announced it was putting Atotechon the block,saying the
unit no longer fit Totals strategic vision. CD
ment and inspection capabilities for fine circuit pattern substrates used in high
bandwidth applications.
Integrated silicon packages such as SiP are becoming more popular as electronic packaging solutions, and this technology is driving the need for finer and
finer circuit pattern designs. However, optical inspection methodologies are
reaching their limits in detecting defects efficiently at these smaller dimensions.
This potential technology gap could negatively impact yield performance and
quality validation of the substrates or boards used for integrated SiP packages.
The lack of inspection capability for fine lines and spaces (<5m) on the
panel size substrates/boards used to fabricate SiP carriers supporting high I/O
or high bandwidth memory or other components could have a negative impact
on yield performance or reliability, iNEMI says.
As such, the consortium is conducting a survey to assess the measurement
and inspection capability for the substrates. This problem is defined as a technical gap in the iNEMI package roadmap as 2m/2m line space design
rules, and iNEMI is planning to make recommendations in this area relative to
product requirements and process/material capabilities needed to close the gap.
To participate, visit surveymonkey.com/r/WPLBCLJ. CD
interests in its two PFG Fiber Glass joint ventures from PPG. Nan Ya and PPG
currently each hold a 50% stake in the JVs.
The transaction is expected to close by the end of 2016. Financial terms
were not disclosed.
PFG manufactures yarn fibers for laminates and fiber-glass reinforcement
materials for automotive applications. It has production facilities in Chia Yi,
Taiwan, and Kunshan, China.
The companies formed the joint venture in 1987 to establish the Taiwan
plant. In 2001 it formed a second JV to create the China site. MB
12
NOVEMBER 2016
Something BIG
is About to
BE REVEALED
pcdandf.com/pcdesign/index.php/editorial/npi-award
MARKET WATCH
METALS INDEX
DATE
MILITARY CHATTER
Trends in the U.S. electronics equipment market (shipments only).
% CHANGE
JUNE JULY AUG. YTD%
0.4
2.4
0.2
Storage devices
-3.4
21.6
-12.4
4.2
-7.0
5.2
-1.7
-20.0
Nondefense
communications equipment
4.3
15.0
-7.7
A/V equipment
-0.6
1.7
1.6
44.8
Components1
3.2
2.0
-1.8
10.1
0.7
3.9
-4.2
1.2
-0.5
2.5
0.5
6.8
Production
Inventories
Customer inventories
Backlogs
14
$0.74
$0.82
$0.81
$0.88
$0.96
$2.17
$2.20
$2.09
$2.19
New orders
Hot Takes
$9.21
PMI
$8.75
SAN JOSE PCB and MCM design software sales rose 8.1%
$8.10
*Preliminary.
semiconductors. Seasonally adjusted.
Source: U.S. Department of Commerce Census Bureau, Oct. 5, 2016
$7.90
1Includes
US MANUFACTURING INDICES
$7.11
3.5
Computers
KEY COMPONENTS
Book-to-bills of various components/equipment.
Semiconductor
Semiconductors2
PCBs3 (North America)
1.01
0.98
0.94
1.02
NOVEMBER 2016
In the Clouds
Cybersecurity can seem like a dense fog that threatens commerce.
ANYONE WHO TOUCHES an electronic device has
PETER BIGELOW
is president and CEO
of IMI (imipcb.com);
pbigelow@imipcb.
com. His column
appears monthly.
15
FOCUS ON BUSINESS
Mike Buetow is
editor in chief of
PCD&F/Circuits
Assembly; mbuetow@
upmediagroup.com.
16
One industry observer noted to me that the situation recalls the rise to power of Lee Kuan Yew, the
founding father of Singapore. When Lee took over,
he made his mission the scrubbing of antisocial
behavior, especially drug use. Drug lords and traffickers were put to death after quick trials. Other
lawbreakers were dealt with harshly as well. He
also declared Singapore open for business, and the
city-state has become the 20th largest exporter in the
world. Its possible, this observer says, the new crop
of leaders are taking a page from Lees playbook.
Supply chain effects. Every national leader has
an obligation to improve the lot of their constituents. Its not at all obvious, however, that each
of these leaders is acting rationally. The political
unrest, to say nothing of the violence, cant be
good for business.
Many of these nations, of course, have deep
ties to the electronics supply chain. Any country
that seeks to become a major player in electronics will end up doing considerable business with
the US.
Contacts in the Philippines indicate great discomfort with the positions of Duterte. OEMs that
want to move programs from China due to IP or
other concerns now suddenly find themselves in
the awkward position of not knowing whether
their preferred landing spot will be any better. And
while there has been no immediate outward impact
to the bottom line, given the long lead times in
electronics, the better indicator will come 12 to 18
months from now.
To put all this in context, perhaps rather than
Singapore, a more timely comparison is with
Mexico. Mexico has suffered enormous casualties
from the drug wars. Kidnappings and murders
have been par for the course, and non-nationals
are often advised not to travel outside in certain
cities after 5 pm. Talk on returning programs to
North America has been noticeably muted of late.
Is the safety factor at play? If so, is the heavyhanded approach of these Southeast Asian nations
the smart long-term play, even if it means a loss
of business in the short run? And despite its blind
eye toward IP and ever-changing regulations, will
Chinas relative stability make that nation the
beneficiary? CA
NOVEMBER 2016
!
s
U
n
i
Jo
Microelectronic Symposium
Best of Today,
Preview of Tomorrow
Material Advances
Strategic Direction/Roadmaps
Nanotechnology
Supporting Partners
www.smta.org/panpac
GLOBAL SOURCING
GREG
PAPANDREW is
a PCB sales and
marketing advisor;
greg@ledlogistics.com.
18
DUANE BENSON
is marketing
manager at
Screaming Circuits
(screamingcircuits.
com); dbenson@
screamingcircuits.com.
19
THERMAL MANAGEMENT
TRACE
The waveform generator settings were extremely flexible. The output voltage could be set from 0.0 to 10.0V.
The frequency could be set from 0.01Hz to over 20MHz.
And the signal DC offset could be set from -10.0 to
+10.0V DC. Three waveforms were employed during this
analysis: sine, triangle (actually sawtooth) and square.
The duty cycle for the square and triangular waveforms
could be set from 0.0 to 99.9%. The duty cycle for the
triangular waveform was set at 99.9% (sawtooth), and the
duty cycles for the square waves were set at 50%, 75%
and 99%. Output levels were set to result in large output
currents, but not large enough to switch the transistor off,
nor to bring it into saturation. Samples of the waveform
generator output waveforms are shown in FIGURE 2. The
generator waveforms exhibited no measurable distortion.
THERMAL MANAGEMENT
RMS signal levels. Next, we need
to consider how to calculate the
rms values of the signals.3 There
are some reference lines drawn on
Figure 2:
A1
Peak voltage
A0
Minimum voltage
rmsoffset = rms 2 + dc 2
See us at ELECTRONICA,
HALL B4, STAND 351
21
THERMAL MANAGEMENT
TABLE 1. Summary Results of Testing
PEAK V
TROUGH V
TRACE TEMP C
Sine
7.5
2.1
5.39
65.5
Sawtooth
7.15
5.68
68.5
Sq. 50%
2.25
5.11
62
Sq. 75%
7.68
2.25
6.12
75
Sq. 99%
7.9
2.25
7.27
97
Conclusions
We conclude the results of this analysis
are consistent with the prior results:
1. The effective current of an analog
ac waveform is the RMS (root mean
square) current, and
2. The temperature of an analog ac
waveform is independent of frequency
(at least over the tested range). PCD&F
Acknowledgments
The empirical measurements could not
have been done without the help and
support of Prototron Circuits (Redmond, WA, and Tucson, CA).
Notes
1.
NOVEMBER 2016
PCB MATERIALS
24
NOVEMBER 2016
PCB MATERIALS
adhesion, a desmear treatment is
used by modifying the resin surface
roughness. It seems there is difficulty
removing contamination from electroless plating on the desmear surface. FIGURE 1 illustrates the process
comparison of subtractive and semiadditive processes.
Top
18.3m
17.8m
Bottom
26.7m
20.9m
EF
2.8
5.9
25
PCB MATERIALS
From an electrical point of view, a flat
surface is desired for high-speed applications with high-frequency signals.
A nanoscale profile copper foil has
been developed, which shows wellbalanced etching capability and adhesion. An acid cleaning process removes
the oxidized copper layer prior treatment (FIGURE 4, left). Nanoscale nodules are formed on the copper surface
by chemical reaction using a proprietary treatment solution (Figure 4,
right). Then the surface of copper
foil is covered with a uniform and
dense layer. The nanoscale nodules
have a large contact area that offers
secure bonding to prepreg by means of
the anchoring effect. Scanning probe
microscope (SPM) images are shown
in FIGURE 5. For the conventional
very-low profile copper foil, the SPM
images are similar to SEM images.
However, SPM shows a quite different
image of nanoscale profile copper foil.
It seems probes have difficulty tracing
the sharp nano surface.
Fine line capability. The nodule of
copper foil is embedded in the prepreg
as it is subjected to hot press lamination. In the case of a subtractive process using conventional copper foil, it
has to be etched completely because
the large-size nodules get stuck in the
prepreg. This may cause over-etching
of the wiring pattern. FIGURE 6 shows
3D images from a confocal microscope
of 9m thick copper foil and nanoscale
foil. The nanoscale profile copper has
twice the etch factor (TABLE 1). The
surfaces of prepreg and the anchored
part of copper are completely different
in appearance. SEM images comparing
etching characteristics of a copper foil
profile are shown in FIGURE 7.
Adhesion behavior. Peel strength is
performed with 30m thick specimens
by performing additional copper plating. The prepreg of FR-4 was laminated with copper foil. Results are shown
in FIGURE 8. There is no significant
difference between the 9m and 18m
thick copper foil with nanoscale profile copper. The adhesion strength is
acceptable on both copper foils. The
nanoscale profile copper foil demonstrated 20 to 30% lower peel strength
than the conventional copper foil.
The samples showed different fracture
26
PCB MATERIALS
behavior, even though they shared the same adhesion failure.
The fracture location of nanoscale profile copper is close to
the copper surface (FIGURE 9). The surface of nanoscale copper foil is covered with resin of prepreg (FIGURE 10).
Finite element simulations. To address this behavior of
nanoscale copper foil, FEM (finite element modeling) was
used for stress analysis. The maximum principal stress was
conducted. Typically copper foil is laminated with prepreg or
buildup material at high temperature. The maximum principal stress is conducted by calculation of the accumulated
principal stress at -55C using Ansys 16.1 software. Prepreg
and copper foil are contained in the model. The material supplier describes typical properties of the prepreg. It is
FIGURE 11. The image-processing algorithm.
overall property of prepreg, but it is not
localized property. Segmented, accurate
parameters are required for prepreg. Prepreg material is a mixture of glass fabric,
resin and filler. The glass fabric layer and
resin/filler layer are separated. Filler is
distributed in the resin.
Filler volume information was
extracted from a cross-sectioned SEM
image. The image-processing algorithm is outlined in FIGURE 11. The
SEM image was split into 500nm thick
images for resin filler layer of prepreg.
Binary images were generated, which
highlighted the filler parts (in green)
within the selected region. The filler
defines the shape of the target. FIGURE
12 shows the binary image obtained
from the contrast-enhanced image. The
volume of filler is calculated on each
tomographic image. CTE (coefficient
of thermal expansion) and modulus are
conducted by a curve-fitting technique
based on filler volume information.
Then, segmented model parameters for
prepreg are conducted. The parameters
of FR-4 type prepreg are shown in FIG- FIGURE 12. Binary image processing for filler distribution in prepreg.
URE 13. A localized realistic model of
copper foil is implemented in this study
for FEM, which can recognize the nanostructure with representative prepreg.
Localized realistic model for
nanoscale profile copper. The simulation model used a 1 to 4m size
nodule with a simplified conventional
profile (FIGURE 14). Given the adhesion
results, higher maximum principal stress
is expected on nanoscale copper foil.
Simulation results are shown in FIGURE
15. Simplified nanoscale profile is flat
model, resulting in low stress distribution, as indicated. The maximum principal stress of conventional foil is greater
than that of the nanoscale profile copper.
These results contradict the adhesion test
NOVEMBER 2016
27
PCB MATERIALS
Conclusion
Acknowledgments
The authors would like to thank
KTT Inc. for kind advice and further
evaluation.
REFERENCES
NOVEMBER 2016
PCB MATERIALS
29
EMS
JABIL Steps Up
A small New England city is now home to a new ODM plant,
but its not the typical electronics kind. by MIKE BUETOW
NOVEMBER 2016
Unitech UC-250M-CV
Board Cleaner
Winner of the 2016 NPI
The UC-250M-CV Board Cleaner
offers a dual cleaning feature using
a combination of a brush roller with
the silicone/adhesive cleaning rollers.
The combination dual dust removal
system assures better results than a
single brush or adhesive roller system.
The UC-250M-CV has the ability to
clean the top surface of PCB even
chip components attached on the
bottom-side. Additionally, the cleaner
features an antistatic bar (ionizer) to
neutralize static and prevent dust
from collecting on the top surface
of the PCB.
email: info@seikausa.com
web: seikausa.com
NOVEMBER 2016
Atlanta Office
1580 Boggs Rd.
Suite 900
Duluth, GA 30096
Main: 770-446-3116
Fax: 770-446-3118
4/19/16 3:14 PM
31
PROCESS CONTROL
A CASE STUDY
Introduction
Void reduction in large, confined solder joints has been a
hot topic for more than a decade. The affected component
may be evolving, but the same challenge exists. Many
papers have reviewed process recommendations to lower
voiding,3 looked at material modifications to mitigate the
NOVEMBER 2016
PROCESS CONTROL
studies several cases in which voiding
data were collected using a standardized method. The trends in these
data sets led to further test method
development.
Stencil Designs
In the component application notes,5
a few stencil designs are suggested, as
shown in FIGURE 2, all with varying
levels of solder coverage on the thermal
pad. The suggested designs break up
the solder deposit on the center pad
into several deposits. The coverage by
area ranges from 37 to 81%.
These recommendations take into
account considerations for thermal
vias in the pad. The test board design
has no vias. This removes a large
33
PROCESS CONTROL
complicating factor from this applesto-apples comparison test method.
For designs using vias, some of this
discussion of solder volume will
nonetheless apply.
The original stencil design (FIGURE
3) split the thermal pad area into nine
square deposits with a wide windowpane pattern. The panes between
deposits measured 20 mils thick. Basic
area calculations show the coverage
by area is 75.1%. This is within the
suggested range.
When a geometric calculation is
made for the 5 mil stencil, assuming
solder is approximately 50% solid by
volume, the deposit will be 13.5%
less than the ideal volume. The ideal
volume is based on the pad size and
the component application note, which
recommends a minimum of 50 microns
of standoff for reliability.
A new stencil was designed to
increase the coverage of the solder
paste and vary the volume of solder to
see the impact on voiding results. As
shown in FIGURE 4, the four designs
chosen were a full pad print, nine windowpanes with finer spacing (10 mils),
quadrants with the same finer spacing,
and quadrants with 20 mil panes.
These designs have a range from
0.0 to 12.9% reduction in solder paste
coverage by area. By obtaining both 4
mil- and 5 mil-thick stencils, volumes
will range from insufficient to excessive, as tabulated in TABLE 1.
AREA REDUCTION
12.9%
-19.7%
12.9%
-19.7%
6.6%
-13.9%
Original design
24.9%
-13.5%
0.0%
-7.8%
12.9%
0.4%
12.9%
0.4%
6.6%
7.6%
No window pane
0.0%
15.2%
FIGURE 5. Voiding for Case 1 with the original 5 mil stencil design, showing results
at two profiles.
Results
Case 1 demonstrates a typical data set
that was collected using the original 5
mil stencil design. Two profiles were
used to demonstrate the low and high
side of the reflow profile window.
Figure 3 shows voiding results for
four different commercially available
solder pastes. Each condition had three
associated boards. The voiding results
are plotted by component to determine
whether any location had an effect on
the results. Generally, the higher reflow
profile seems to yield lower voiding
percentages and lower variation for
all four pastes. This result is easily
assessed visually; however, it is also
clear there seem to be intermittent high
voiding results.
Viewing all the results by profile as
distributions (FIGURE 6), there is one
group of voiding results that is distinctly
34
PROCESS CONTROL
higher than the general distribution.
Highlighting only benchmark paste A in
darker green, the distribution and averages are low, but a couple outliers have
voiding >35%. Case 2 is a comparison
of several different solder pastes with
different flux and alloy combinations.
The results in FIGURE 7 are presented by
alloy and flux, plotted by component.
In this case, two boards were reflowed
per paste with a typical ramp to peak
profile. Benchmark paste E with alloy 1
shows acceptable results as far as voiding percent, as well as low variation.
The experimental formulations do not
approach this result. Some pastes show
intermittent low voiding components,
which led to investigation of the individual x-ray images.
FIGURE 8 shows a selection of comFIGURE 7. Voiding for case 2 using typical reflow profile and original 5 mil
stencil design.
ponent images. The minimum voided
component shows different characteristic voiding, depending on the solder paste. The maximum
voided component has drastically larger voids. Benchmark
paste Bs largest voids do not seem to follow any pattern.
35
PROCESS CONTROL
Many images of experimental pastes
were shown to have a similar frowny
face pattern. This resembles voids congregating along the pathways created by
the nine windowpane pattern. Benchmark C shows large voids, which almost
seem to correspond to the deposits created by the nine windowpane pattern.
Looking back at the maximum voided components in many data sets, the
same pattern emerged.
There may be many sources for this
variation. Was this trend in the pattern
of voiding with this design real? One
possible source of this inconsistency was
variation in placement height. The placement machine used in this test places
components at some height above an
ideal zero. Since the board thickness and
flatness varies, the amount the component is pressed into the paste could also
be a variable. Could the variation be
another characteristic of the solder paste
formulation? Experimental solder pastes
typically showed many small voids and
the frowny face pattern. These considerations always return to the question
of how the solder paste outgassing is FIGURE 10. Case 3 voiding results plotted by aperture design.
affected by the choice of stencil aperture
design. This led to development of stencils with new designs, as discussed in the previous section.
With an increase in the solder volume, could these intermittent high voiding levels be mitigated? Would a different
pattern with the same amount of coverage yield different
results? Overall, the goal was to reduce voiding percentages,
mitigate largest voids, and reduce variation in the voiding
test results.
Case 3 was conducted on several different fluxes tested
with a low-silver alloy. All boards were reflowed using the
standard ramp to peak profile. FIGURE 9 shows the variabilFIGURE 11. X-ray images of maximum voided components in
ity of the voiding results with the new stencil designs at both
case 3.
thicknesses. Overall, the standard deviation has fallen below
10% for all of the results. There are still a few intermittent
high voiding results. When the data are plotted, separating
boards was analyzed, but the number of components was not
the results by design (FIGURE 10), the intermittent high voiding results do not correlate with a particular stencil or design.
normalized. It may be possible to yield more definitive results
The associated x-ray images (FIGURE 11) do not seem to have
with more replicates.
a common pattern.
Conclusion
Case 4 simply compares the stencil designs, all other facThe first case studied was one directed to show the impact
tors being equal. This trial was carried out with two SAC 305
of reflow profiling on voiding results. The data presented
commercially available pastes: one with typically low voiding
strongly support lower voiding with a longer, hotter profile.
and low variation, and one with typically higher voiding. The
One additional set of results from Case 2, found in FIGURE
results that were plotted based on stencil and aperture design
13, shows where the profile is varied, but there is little cor(FIGURE 12) show relatively consistent results for benchmark
paste A. For the other paste, the new 5 mil stencil showed
relation between profile and voiding results. The main difhigher variation than either the original stencil or the new
ference is Case 2 shows pastes with different alloys, as well
4 mil stencil. The average voiding with new stencil designs
as different profiles. Each paste combination may have a
was marginally lower. The comparison of variation is slightly
different trend.
skewed because there are more components with the same
Generally, the profile influence will have a few general
pattern for the original stencil because the same number of
trends resulting in higher voiding:
36
NOVEMBER 2016
PROCESS CONTROL
Low peak temperature tends to require more time for complete solder wetting.
Excessive peak temperature or profile length results in
oxidation on surfaces, increasing the potential for voiding.
To reduce the sources of variation in voiding comparison
data, two new stencils with four different aperture designs
were tested. Generally, these stencils yielded results with less
variation than was experienced with the original stencil. The
intermittent high voiding results were also less frequent with
the new designs; however, some pastes still showed more
variation than others.
Designs with higher volumes did not show signs of
defects from the excess. (Solder balling or poor fillet formation were the downsides stated in the component application note.5) Designs with less volume (4 mil stencil) did not
intrinsically show more voiding or variation. This implies
there is not a direct correlation to voiding percent and solder volume. This is especially evident looking at the results
for Benchmark paste A in Figure 10, where all stencils and
designs show very similar results. This seems to indicate that
for some pastes that have a chemistry designed to reduce
QFN voiding, the results will also be good for a wide range
of designs and conditions. CA
Acknowledgments
FIGURE 12. Results from case 4, comparing stencils and
aperture designs.
Thanks to Mark Reece and Sarah Bjornland for their assistance collecting much of these data. Thanks to Dr. Arnab
Dasgupta for providing many of the experimental formulas.
Ed.: This article was first published at the SMTA International Conference on Soldering and Reliability in June 2016, and is republished
with permission of the author.
REFERENCES
1. Brook Sandy-Smith, Reliability Challenges for Bottom Termination
Components, SMTA International Conference on Soldering and Reliability, May 2013.
2. Matthew Kelly, et al, Via-in-pad Plated Over (VIPPO) Design Considerations for Enterprise Server and Storage Hardware, SMTAI
Proceedings, October 2015.
3. Brook Sandy-Smith and Seth Homer, Optimizing Assembly of QFNs,
SMTAI Proceedings, October 2013.
4. BrandonJuddand MariaDurham, The Benefits of Flux-Coated
Solder Preforms in a QFN Assembly Process, IMAPS, October 2015.
5. Application Notes for Surface Mount Assembly of Amkors MicroLeadFrame Packages, Rev G, September 2008.
NOVEMBER 2016
37
TECH TIPS
TIM ONEILLis
technical marketing
manager at AIM
Solder (aimsolder.
com);toneill@aimsolder.com.
38
FIGURE 2. Repeated results in reduced voiding resulting from I/O aperture design in larger DoE with more
input variables.
CELEBRATING 60 YEARS
OF BEING THE TURNING POINT
FOR THE ELECTRONICS INDUSTRY
GETTING LEAN
YOUSEF
HEIDARI is
vice president of
engineering, West
Coast operations
at SigmaTron;
yousef.heidari@
sigmatronintl.com.
DENNIS
MCNAMARA
is vice president
of engineering,
Mexico operations
at SigmaTron
International
(sigmatronintl.com);
dennis.mcnamara@
sigmatronintl.com.
40
TECH TIPS
possible to minimize the impact of peak
temperatures on the wire-bonded die. If
the profile is not hot enough and long
enough in duration, the flux does not
properly activate and then deactivate.
If peak temperatures are held too long
and higher temperature profiles are used
for Pb-free solder, yields go down due to
silver die attach failures. The die attach
failure is normally caused by some type
of force acting on the lens or due to an
LED vendor wire bonding issue.
Mitigating the waste of inappropriate processing also plays a factor
in test strategy. In this case, the issue
is most related to cost of test. Simpler
equipment achieves the desired result
at lower cost.
LED PCBAs are typically tested
using in-circuit test (ICT). However,
standard ICT will not test for brightness. At this contractor, testing is done
using cameras and software that analyzes pixel values. The alternative test
option measures LED hue using a
spectrophotometer with an integrating
sphere, which requires precise distance
between the LED and test equipment.
From a cost and test time perspective,
the latter method was deemed too costly
when the two methods were analyzed in
terms of cost and accuracy. In the camera method for white LEDs, the ratio of
blue pixel intensity to red pixel intensity
is measured to verify the correct hue.
11/24/15
11:00 AM
41
Basic qualifications:
ROBERT
BOGUSKI is
president of Datest
Corp., (datest.com);
rboguski@datest.
42
Bachelors of science (or equivalent work experience) in electrical engineering, computer engineering, computer science, mechanical engineering, or
materials science.
Attention to detail; daring; self-confident; selfmotivated. How self-confident? Willingness to
call the Boss out when he says something stupid.
Fearlessness a definite differentiator.
Exceptional written and verbal communication
skills. And when we say exceptional, we aint
blowin smoke!
Possessed of an innate aversion to Groupthink.
Intellectual curiosity and a willingness to learn,
especially concerning why systems work, and even
more especially, why they dont.
Not shy or afraid to ask questions, the most important being, why?
Not being afraid to fail and make mistakes,
learning from those mistakes, applying what was
learned, and (hopefully) not making the same
mistake twice.
Knows how, or at least is willing to learn how, to
read, interpret, and potentially create a test design
from a customers statement of work, while being
cognizant of the probability the customer has at best
wire during heating. The image on the right shows solder balling due to unprepared wire.
NOVEMBER 2016
43
MACHINES
MATERIALS
TOOLS
SYSTEMS
SOFTWARE
Advanced Circuits
Tektronix
Sunstone Circuits
pcbartist.com
tek.com
pcb123.com
OTHERS OF NOTE
44
PLM/MRP-CAD INTEGRATION
ACE Translator 3000 v 7.0 offers twoway translation between most common EDA, CAD, and 3D formats, in a
single intuitive environment. Converts
DXF, GDSII, Gerber, Postscript, PDF,
ODB++, TIFF, BITMAP, STEP, STL, and
more. Built-in viewer verifies translation results. Includes rulers, measurement tools, query, cell browser, hierarchy browser, HighLite broken polygons,
plus new editing and repair features.
T-Tech
Numerical Innovations
ema-eda.com/connect
t-tech.com
numericalinnovations.com/collections/ace-translator-3000
EM SIMULATION SOFTWARE
HIGH-FREQUENCY LAMINATE
CST Studio Suite v. 17 accurately simulates phenomena that appear when components are combined into systems. New features permit individual components to be combined and simulated
effectively. Filter Designer 3D, a design and synthesis tool for cross-coupled cavity filters, can design
for arbitrary filter response with easy placement of
transmission zeros and a wide range of coupling
resonator topologies available to realize the corresponding filter response. Also extracts coupling
matrix, which helps analyze and tune a device.
Shengyi Technology
SnapEDA
cst.com
shengyi-usa.com
snapeda.com
NOVEMBER 2016
MACHINES
MATERIALS
TOOLS
SYSTEMS
SOFTWARE
TABLETOP VPS
MASTER TENSIONING FRAME
tensoRED is designed to provide more
tension than Alpha Tetra frame. No
air pressure on the frame is needed.
Reportedly delivers less paste smearing, reduced variation in volume deposits, and improved positional alignment
compared to Tetra frames.
Zero Smog EL provides fume extraction for up to two workplaces. Provides clean, reconditioned air with a
combination ultrafine H13 HEPA/10%
active carbon foam filter that captures
0.3m, plus low-volume gas. Includes
M5 dust pre-filter that captures 40 to
50% of particles up to 100m. Features maintenance-free, brushless turbine, energy-saving air recirculation, a
simple filter replacement process and
optional remote control. Has blower
capacity of 220m3/h and extraction
power of 2,500Pa.
IBL Technologies
Weller
alphaassembly.com
ibl-tech.com
weller-toolsus.com
OTHERS OF NOTE
LED PANEL X-RAY
Glenbrook Technologies
Dymax
Chemtronics
glenbrooktech.com
dymax.com
chemtronics.com
PASTE CLEANER
Nano Stencil Clean is for cleaning solder paste from nanocoated stencils and
misprinted boards. Is environmentally
safe with a low pH and nearly zero
VOC content. Contains no CFCs, HCFCs,
terpenes, alcohol or other hazardous
ingredients. Performs in ultrasonic,
spray or manual cleaning applications.
Safe on metals and plastics and is
REACH and RoHS compliant.
Henkel
Nano Stencil
JTAG Technologies
henkel-adhesives.com/electronics
NanoStencil.com
jtag.com
NOVEMBER 2016
45
MARKETPLACE
Vertrel
These cleaning solvents are excellent for removing particulates, flux, light and heavy
oil and grease. Other Vertrel solvents are effective rinsing and drying agents. High
purity, nonflammable, low toxicity.
Vertrel XF Vertrel MCA Vertrel X-T85
Vertrel XSi Vertrel MCA Plus Vertrel SMT
Vertrel XMS Plus Vertrel XMS Vertrel MCA
Vertrel SFR Vertrel SDG Vertrel X-P10
AD INDEX
Visit pcdandf.com or circuitsassembly.com to access the digital edition for links to advertisers' websites.
Company
Page No.
AIM, aimsolder.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Beta Layout, pcb-pool.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Directory of EMS Companies, circuitsassembly.com/dems. . . 19, 46
DownStream Technologies, downstreamtech.com. . . . . . . . . . . . . . 4
EMA, go.ema-eda.com/172-3D-1. . . . . . . . . . . . . . . . . . . . . . . . . . C4
HKPCA, hkpca-ipc-show.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Imagineering, Inc., PCBnet.com . . . . . . . . . . . . . . . . . . . . . . . . . 1, 47
IPC Apex Expo, ipcapexexpo.org. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Master Bond, masterbond.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Miller-Stephenson, cav.mschem.com. . . . . . . . . . . . . . . . . . . . . . . 46
Online Electronics, pcb4less.com. . . . . . . . . . . . . . . . . . . . . . . . . . 47
Uyemura, uyemura.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
The advertising index is published as an additional service. The publisher does not assume any liability for errors or omissions.
Advertising Sales
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NOVEMBER 2016
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47
TECHNICAL ABSTRACTS
Implantable Electronics
Materials Qualification
BTC/QFN Test Board Design Considerations and
Method for Qualifying Soldering Materials and
Cleaning Processes
Authors: Mike Bixenman, Mark McMeen and
Jason Tynes; mikeb@kyzen.com.
Solder
Improving the PCB Assembly Manufacturing Process by Utilizing an Alternative Solder Paste: A Statistical Evaluation
Author: Denis Barbini, Ph.D.; barbini@uic.com.
Abstract: Results from an investigation that studied and characterized a novel lead-free solder paste
compared to traditional solder materials. As a basis
for the analysis, solder materials were exposed to
harsh environments to understand if the new solder
paste technology is capable of withstanding the realities of modern manufacturing processes for fine-pitch
components (0.3mm CSPs and 01005/0201 passives).
Evaluation of solder paste printing performance was
a primary focus of the investigation, taking into
consideration numerous common board finishes and
stencil aperture designs. Paste volume measurements
acquired by SPI were used to verify solder paste volume on pads to quantify performance. Challenging
manufacturing processes were simulated by aging the
pastes at room versus elevated temperatures and then
printing at defined time intervals. Simulated extended
continuous printing was also examined. A detailed
statistical analysis identifies the relationship between
the condition of the solder paste and the paste volume on the pad of a given component type. (SMTAI,
September 2016)
NOVEMBER 2016
Will it Fit?
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Do you find yourself crossing your fingers the first
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collision detection and advanced 3D analysis
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