Performance Analysis of Tunnel Field Effect

Transistor Using Charge Plasma Concept

Ishu Agrawal, P.N Kondekar
Department of Electronics and Communication Engineering,
PDPMIIITDM Jabalpur, MP, India.
Email:(ishu.agrawal, pnkondekar)@iiitdmj.ac.in

AbstractIn this paper, we have analyzed the impact of gate

dielectric, device width, metal electrodes on Tunnel Field Effect
Transistor (T-FET). A numerical TCAD device simulator 3-D
ATLAS version 2.10.18.R shows that reducing the width can
reduce the effective threshold voltage and applied voltages.
Transistor with a high ION /IOFF ratio of 1010 sub- threshold swing
of 57 mV/decade for the channel length of 50 nm with Hafnium
oxide as gate dielectric material. The performance analysis of
Tunnel field effect transistor is done by taking doping less T-FET
and taking tantalum as the drain electrode, gold as the source
electrode and varying dielectric material, width of the device,
applied voltages and metal contacts. The simulation results
indicate the suitability of the proposed novel structure for
replacing the conventional CMOS device.
KeywordsBand to band tunneling, double gate (DG), Gated
p+-i-n+ diode, tunnel field effect transistor (T-FET),subthreshold swing (SS), charge plasma.

I. INTRODUCTION
Decreasing the dimension will decrease the threshold
voltage of the device which in turn will decrease the applied
voltages. It can be regarded as a novel device structure for
use in high speed and low power electronic devices owing
to its excellent SCE, ideal subthreshold swing, excellent
gate controllability, low leakage current and good carrier
transport efficiency The simulations are carried out using
non local band-to-band tunneling model without impact
ionization to account for highly doped channel, band-gap
narrowing (BGN), Shockley Read Hall (SRH) recombination,
Lombardi model and Auger recombination models. The
mobility model includes both doping and transverse-field
dependence. In Shockley Read Hall (SRH) recombination
both generation and recombination is the major parameters
which should be taken in consideration.

100

50 nm

100

Fig.1. (a) Conventional T-FET (b) Proposed T-FET

TABLE I.

Parameters

T-FET

Channel length (L g )

50 nm

Device layer Doping

(Source-p type,
channel p type, drain
n-type )
Device layer thickness
(TSi )
Gate-oxide material
Gate-oxide thickness
(tox )
Gate bias
Drain bias
Device width

1.01017cm3

10 nm
SiO2 and Hf O2
1 nm to 6 nm
0.0 V to 1V
1 V
10 nm to 50 nm

II. CHARACTERISTICS OF DEVICE

In this section, we have analyzed the various device char
acteristics of the T-FET such as threshold voltage Vth , ION /IOFF
ratio and subthreshold swing (SS) by varying the Device width,
electrode contacts, applied voltage and gate dielectric
materials. Fig.1 depicts the device with gold electrode at
source, tantalum electrode at the drain and hafnium dioxide as
the dielectric material with doping concentration equivalent to
1.0 1017. Figure.2 shows the threshold voltage Vth variations
at width of 5nm, 10nm, 15nm, 20 nm, 25 nm, 30 nm, 35 nm 40
nm, 45nm, and 50 nm, taking the gate dielectric HfO2 .It is
evident that with the increase in width, threshold voltage
increases. HfO2 is having the highest ION/IOFF ratio out of the
two dielectric materials. The optimized simulation results of
proposed device shows analyzed characteristics as compared
with other TFET and conventional CMOS device [1], [2] and
[5].For creating drain n with very high doping, tantalum
(work function = 4.2 eV) is employed as the drain metal
electrode. Similarly, for creating the p source region by

inducing holes with the very high concentration gold (work

function=5.1 eV) is employed as the source metal electrode.
There are two essential features in this concept. First the work
functions of the gates should be different from that of silicon in
which (
+
) and (
+
) are the
, <
, >
work function for tantalum and gold. Other parameters are the
elementary charge (q) the electron affinity of the bulk silicon
(
= 4.17eV), and the band gap of bulk silicon(Eg). For the
best rectifying behavior, the difference between both work
functions should be at least ~0.5eV. Second the thickness of
the silicon body should be less than the Debye length, i.e.
=

Similarly, Figure. 4 shows the variations in parameters

for reference at different gate dielectric materials and we
observed that there is great effect on ON current of the device
for high-K gate dielectric material which leads to more
deviation in ON to OFF current ratio of the device. Table
III shows the slight effect on the parameters with change in
width, dielectric constant, dielectric thickness and electrode
contacts on threshold and switching characteristics, in
indicating excellent control of the dielectric, because of the TFET structure

With the reduction in width of the device, fringing effect

starts dominating because the channel length and width ratio
starts to approach each other [1].

Fig.4. Characteristic analysis for Different gate dielectric material

IV. CONCLUSION
In this paper, we have analyzed the impact of gate
dielectric, devise width, electrode contacts and channel
engineering on characteristics of T-FET by using a numerical
TCAD device simulator 3-D ATLAS version 2.10.18.R [9].
The simulation results show high ION/IOFF current ratio and
increased Vth. with the increase in device dimensions.

Fig.2. Threshold voltage (Vth ) at different width

REFERENCES
[1]

[2]

[3]
Fig.3. ION /IOFF at different applied voltage and doping concentration
[4]

III. CHARACTERISTIC TABLE OF DEVICE

In this section, we have analyzed the various device char
acteristics of the T-FET such as threshold voltage Vth, by
varying the device width, electrode contacts. Table III.
depicts the threshold variations at different channel length of
gate dielectric Hf O2.

[5]

[6]

TABLE II.

Parameters

Vth
ION / IOF F

Width of Electrode contacts Dielectric Dielectric

the device work function Constant thickness

constant

[7]
[8]
[9]

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