Sadasd

entity primo4b is
port (a,b,c,d: in bit;

f: out bit);
end primo4b;
architecture aa of primo4b is
begin
f<=(
((not d) and (not c) and (not b) and a) or
((not d) and (not c) and b and (not a)) or
((not d) and (not c) and b and a) or
((not d) and c and (not b) and a) or
((not d) and c and b and a) or
(d and (not c ) and b and a) or
(d and c and (not b ) and a )
);
end aa;
entity primo4b is
f: out bit);
end primo4b;
begin
f<=(
);
end aa;entity primo4b is
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
architecture aa
begin
f<=(
((not d) and
((not d) and
((not d) and
of primo4b is
(not c) and (not b) and a) or
(not c) and b and (not a)) or
(not c) and b and a) or

);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
architecture aa
begin
f<=(
((not d) and
((not d) and
((not d) and
of primo4b is

);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
architecture aa
begin
f<=(
((not d) and
((not d) and
((not d) and
of primo4b is

);
f: out bit);
end primo4b;
begin
f<=(
);
f: out bit);
end primo4b;
begin
f<=(
);
end aa;

Sadasd

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Sadasd

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entity primo4b is

port (a,b,c,d: in bit;

((not d) and c and (not b) and a) or

((not d) and c and (not b) and a) or

((not d) and c and (not b) and a) or

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